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https://github.com/holub/mame
synced 2025-07-05 01:48:29 +03:00
Kill off some AM_BASE_LEGACYs.
This commit is contained in:
Aaron Giles
parent
f987a35e27
commit
dbf2cb905a
@ -297,7 +297,7 @@ WRITE32_MEMBER(aristmk5_state::sram_banksel_w)
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/* U.S games have no dram emulator enabled */
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static ADDRESS_MAP_START( aristmk5_map, AS_PROGRAM, 32, aristmk5_state )
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AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
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AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
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AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
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/* MK-5 overrides */
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AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write
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@ -323,7 +323,7 @@ ADDRESS_MAP_END
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/* with dram emulator enabled */
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static ADDRESS_MAP_START( aristmk5_drame_map, AS_PROGRAM, 32, aristmk5_state )
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AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(aristmk5_drame_memc_logical_r, archimedes_memc_logical_w)
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AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
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AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
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/* MK-5 overrides */
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AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write
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@ -294,16 +294,14 @@ WRITE8_MEMBER(asuka_state::asuka_msm5205_stop_w)
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m_adpcm_pos &= 0xff00;
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}
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static UINT8 *cadash_shared_ram;
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READ16_MEMBER(asuka_state::cadash_share_r)
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{
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return cadash_shared_ram[offset];
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return m_cadash_shared_ram[offset];
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}
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WRITE16_MEMBER(asuka_state::cadash_share_w)
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{
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cadash_shared_ram[offset] = data & 0xff;
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m_cadash_shared_ram[offset] = data & 0xff;
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}
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@ -433,7 +431,7 @@ m68k M -> z180 M <-> z180 S <- m68k S
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static ADDRESS_MAP_START( cadash_sub_map, AS_PROGRAM, 8, asuka_state )
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AM_RANGE(0x0000, 0x7fff) AM_ROM
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AM_RANGE(0x8000, 0x87ff) AM_RAM AM_BASE_LEGACY(&cadash_shared_ram)
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AM_RANGE(0x8000, 0x87ff) AM_RAM AM_SHARE("sharedram")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( cadash_sub_io, AS_IO, 8, asuka_state )
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@ -296,8 +296,8 @@ static ADDRESS_MAP_START( backfire_map, AS_PROGRAM, 32, backfire_state )
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AM_RANGE(0x160000, 0x161fff) AM_WRITE(backfire_nonbuffered_palette_w) AM_SHARE("paletteram")
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AM_RANGE(0x170000, 0x177fff) AM_RAM AM_SHARE("mainram")// main ram
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// AM_RANGE(0x180010, 0x180013) AM_RAM AM_BASE_LEGACY(&backfire_180010) // always 180010 ?
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// AM_RANGE(0x188010, 0x188013) AM_RAM AM_BASE_LEGACY(&backfire_188010) // always 188010 ?
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// AM_RANGE(0x180010, 0x180013) AM_RAM AM_SHARE("backfire_180010") // always 180010 ?
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// AM_RANGE(0x188010, 0x188013) AM_RAM AM_SHARE("backfire_188010") // always 188010 ?
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AM_RANGE(0x184000, 0x185fff) AM_READWRITE(backfire_spriteram1_r, backfire_spriteram1_w)
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AM_RANGE(0x18c000, 0x18dfff) AM_READWRITE(backfire_spriteram2_r, backfire_spriteram2_w)
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@ -36,7 +36,7 @@ lev 7 : 0x7c : 0000 05be - xxx
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static ADDRESS_MAP_START( bigstrkb_map, AS_PROGRAM, 16, bigstrkb_state )
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AM_RANGE(0x000000, 0x07ffff) AM_ROM
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// AM_RANGE(0x0c0000, 0x0cffff) AM_READWRITE_LEGACY(megasys1_vregs_C_r, megasys1_vregs_C_w) AM_BASE_LEGACY(&megasys1_vregs)
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// AM_RANGE(0x0c0000, 0x0cffff) AM_READWRITE_LEGACY(megasys1_vregs_C_r, megasys1_vregs_C_w) AM_SHARE("megasys1_vregs")
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AM_RANGE(0x0C2004, 0x0C2005) AM_WRITENOP
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AM_RANGE(0x0C200C, 0x0C200d) AM_WRITENOP
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@ -105,7 +105,7 @@ static ADDRESS_MAP_START( boogwing_map, AS_PROGRAM, 16, boogwing_state )
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AM_RANGE(0x24e6c0, 0x24e6c1) AM_READ_PORT("DSW")
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AM_RANGE(0x24e138, 0x24e139) AM_READ_PORT("SYSTEM")
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AM_RANGE(0x24e344, 0x24e345) AM_READ_PORT("INPUTS")
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AM_RANGE(0x24e000, 0x24e7ff) AM_WRITE_LEGACY(deco16_104_prot_w) AM_BASE_LEGACY(&deco16_prot_ram)
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AM_RANGE(0x24e000, 0x24e7ff) AM_WRITE_LEGACY(deco16_104_prot_w) AM_SHARE("prot16ram")
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AM_RANGE(0x260000, 0x26000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
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AM_RANGE(0x264000, 0x265fff) AM_DEVREADWRITE_LEGACY("tilegen1", deco16ic_pf1_data_r, deco16ic_pf1_data_w)
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@ -581,6 +581,8 @@ DRIVER_INIT_MEMBER(boogwing_state,boogwing)
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deco56_remap_gfx(machine(), "gfx6");
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deco102_decrypt_cpu(machine(), "maincpu", 0x42ba, 0x00, 0x18);
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memcpy(dst, src, 0x100000);
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decoprot_reset(machine());
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}
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GAME( 1992, boogwing, 0, boogwing, boogwing, boogwing_state, boogwing, ROT0, "Data East Corporation", "Boogie Wings (Euro v1.5, 92.12.07)", GAME_SUPPORTS_SAVE )
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@ -181,8 +181,8 @@ static ADDRESS_MAP_START( cninja_map, AS_PROGRAM, 16, cninja_state )
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AM_RANGE(0x1a4000, 0x1a47ff) AM_RAM AM_SHARE("spriteram") /* Sprites */
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AM_RANGE(0x1b4000, 0x1b4001) AM_DEVWRITE("spriteram", buffered_spriteram16_device, write) /* DMA flag */
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AM_RANGE(0x1bc000, 0x1bc0ff) AM_WRITE_LEGACY(deco16_104_cninja_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection writes */
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AM_RANGE(0x1bc000, 0x1bcfff) AM_READ_LEGACY(deco16_104_cninja_prot_r) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
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AM_RANGE(0x1bc000, 0x1bc0ff) AM_WRITE_LEGACY(deco16_104_cninja_prot_w) AM_SHARE("prot16ram") /* Protection writes */
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AM_RANGE(0x1bc000, 0x1bcfff) AM_READ_LEGACY(deco16_104_cninja_prot_r) AM_SHARE("prot16ram") /* Protection device */
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AM_RANGE(0x308000, 0x308fff) AM_WRITENOP /* Bootleg only */
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ADDRESS_MAP_END
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@ -234,7 +234,7 @@ static ADDRESS_MAP_START( edrandy_map, AS_PROGRAM, 16, cninja_state )
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AM_RANGE(0x188000, 0x189fff) AM_RAM_DEVWRITE_LEGACY("deco_common", decocomn_nonbuffered_palette_w) AM_SHARE("paletteram")
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AM_RANGE(0x194000, 0x197fff) AM_RAM AM_SHARE("ram") /* Main ram */
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AM_RANGE(0x198000, 0x1987ff) AM_READWRITE_LEGACY(deco16_60_prot_r, deco16_60_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
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AM_RANGE(0x198000, 0x1987ff) AM_READWRITE_LEGACY(deco16_60_prot_r, deco16_60_prot_w) AM_SHARE("prot16ram") /* Protection device */
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AM_RANGE(0x199550, 0x199551) AM_WRITENOP /* Looks like a bug in game code, a protection write is referenced off a5 instead of a6 and ends up here */
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AM_RANGE(0x199750, 0x199751) AM_WRITENOP /* Looks like a bug in game code, a protection write is referenced off a5 instead of a6 and ends up here */
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@ -280,7 +280,7 @@ static ADDRESS_MAP_START( mutantf_map, AS_PROGRAM, 16, cninja_state )
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AM_RANGE(0x160000, 0x161fff) AM_RAM_DEVWRITE_LEGACY("deco_common", decocomn_nonbuffered_palette_w) AM_SHARE("paletteram")
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AM_RANGE(0x180000, 0x180001) AM_DEVWRITE_LEGACY("deco_common", decocomn_priority_w)
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AM_RANGE(0x180002, 0x180003) AM_WRITENOP /* VBL irq ack */
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AM_RANGE(0x1a0000, 0x1a07ff) AM_READWRITE_LEGACY(deco16_66_prot_r, deco16_66_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
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AM_RANGE(0x1a0000, 0x1a07ff) AM_READWRITE_LEGACY(deco16_66_prot_r, deco16_66_prot_w) AM_SHARE("prot16ram") /* Protection device */
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AM_RANGE(0x1c0000, 0x1c0001) AM_DEVWRITE("spriteram", buffered_spriteram16_device, write) AM_DEVREAD_LEGACY("deco_common", decocomn_71_r)
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AM_RANGE(0x1e0000, 0x1e0001) AM_DEVWRITE("spriteram2", buffered_spriteram16_device, write)
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@ -875,6 +875,8 @@ static MACHINE_START( cninja )
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state->save_item(NAME(state->m_scanline));
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state->save_item(NAME(state->m_irq_mask));
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decoprot_reset(machine);
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}
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static MACHINE_RESET( cninja )
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@ -786,7 +786,7 @@ static ADDRESS_MAP_START( fghthist_map, AS_PROGRAM, 32, deco32_state )
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AM_RANGE(0x16c000, 0x16c01f) AM_READNOP
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AM_RANGE(0x17c000, 0x17c03f) AM_READNOP
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_BASE_LEGACY(&deco32_prot_ram)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_SHARE("prot32ram")
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AM_RANGE(0x208800, 0x208803) AM_WRITENOP /* ? */
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ADDRESS_MAP_END
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@ -816,7 +816,7 @@ static ADDRESS_MAP_START( fghthsta_memmap, AS_PROGRAM, 32, deco32_state )
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AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_rowscroll_w) AM_SHARE("pf4_rowscroll32")
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AM_RANGE(0x1e0000, 0x1e001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_BASE_LEGACY(&deco32_prot_ram)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE_LEGACY(deco16_146_fghthist_prot_r, deco16_146_fghthist_prot_w) AM_SHARE("prot32ram")
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ADDRESS_MAP_END
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// the video drawing (especially sprite) code on this is too slow to cope with proper partial updates
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@ -956,7 +956,7 @@ static ADDRESS_MAP_START( tattass_map, AS_PROGRAM, 32, deco32_state )
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AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_rowscroll_w) AM_SHARE("pf4_rowscroll32")
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AM_RANGE(0x1e0000, 0x1e001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE(tattass_prot_r, tattass_prot_w) AM_BASE_LEGACY(&deco32_prot_ram)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE(tattass_prot_r, tattass_prot_w) AM_SHARE("prot32ram")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( nslasher_map, AS_PROGRAM, 32, deco32_state )
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@ -997,7 +997,7 @@ static ADDRESS_MAP_START( nslasher_map, AS_PROGRAM, 32, deco32_state )
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AM_RANGE(0x1d4000, 0x1d5fff) AM_RAM_WRITE(deco32_pf4_rowscroll_w) AM_SHARE("pf4_rowscroll32")
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AM_RANGE(0x1e0000, 0x1e001f) AM_DEVREADWRITE_LEGACY("tilegen2", deco16ic_pf_control_dword_r, deco16ic_pf_control_dword_w)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE(nslasher_prot_r, nslasher_prot_w) AM_BASE_LEGACY(&deco32_prot_ram)
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AM_RANGE(0x200000, 0x200fff) AM_READWRITE(nslasher_prot_r, nslasher_prot_w) AM_SHARE("prot32ram")
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ADDRESS_MAP_END
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/******************************************************************************/
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@ -1669,6 +1669,7 @@ static MACHINE_RESET( deco32 )
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{
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deco32_state *state = machine.driver_data<deco32_state>();
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state->m_raster_irq_timer = machine.device<timer_device>("int_timer");
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decoprot_reset(machine);
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}
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static INTERRUPT_GEN( deco32_vbl_interrupt )
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@ -275,7 +275,7 @@ static ADDRESS_MAP_START( decomlc_map, AS_PROGRAM, 32, deco_mlc_state )
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AM_RANGE(0x0500000, 0x0500003) AM_WRITE(avengrs_eprom_w) AM_MIRROR(0xff000000)
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AM_RANGE(0x0600000, 0x0600007) AM_DEVREADWRITE8_LEGACY("ymz", ymz280b_r, ymz280b_w, 0xff000000) AM_MIRROR(0xff000000)
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AM_RANGE(0x070f000, 0x070ffff) AM_READ(stadhr96_prot_146_r) AM_MIRROR(0xff000000)
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// AM_RANGE(0x070f000, 0x070ffff) AM_READ_LEGACY(stadhr96_prot_146_w) AM_BASE_LEGACY(&deco32_prot_ram)
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// AM_RANGE(0x070f000, 0x070ffff) AM_READ_LEGACY(stadhr96_prot_146_w) AM_SHARE("prot32ram")
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ADDRESS_MAP_END
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/******************************************************************************/
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@ -57,7 +57,7 @@ READ32_MEMBER(ertictac_state::ertictac_podule_r)
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static ADDRESS_MAP_START( ertictac_map, AS_PROGRAM, 32, ertictac_state )
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AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
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AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
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AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
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AM_RANGE(0x03340000, 0x0334001f) AM_READ(ertictac_podule_r)
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AM_RANGE(0x033c0000, 0x033c001f) AM_READ(ertictac_podule_r)
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@ -105,7 +105,7 @@ static ADDRESS_MAP_START( funkyjet_map, AS_PROGRAM, 16, funkyjet_state )
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AM_RANGE(0x120000, 0x1207ff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_word_w) AM_SHARE("paletteram")
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AM_RANGE(0x140000, 0x143fff) AM_RAM
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AM_RANGE(0x160000, 0x1607ff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0x180000, 0x1807ff) AM_READWRITE_LEGACY(deco16_146_funkyjet_prot_r, deco16_146_funkyjet_prot_w) AM_BASE_LEGACY(&deco16_prot_ram)
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AM_RANGE(0x180000, 0x1807ff) AM_READWRITE_LEGACY(deco16_146_funkyjet_prot_r, deco16_146_funkyjet_prot_w) AM_SHARE("prot16ram")
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AM_RANGE(0x184000, 0x184001) AM_WRITENOP
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AM_RANGE(0x188000, 0x188001) AM_WRITENOP
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AM_RANGE(0x300000, 0x30000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
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@ -304,6 +304,8 @@ static MACHINE_START( funkyjet )
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state->m_maincpu = machine.device<cpu_device>("maincpu");
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state->m_audiocpu = machine.device<cpu_device>("audiocpu");
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state->m_deco_tilegen1 = machine.device("tilegen1");
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decoprot_reset(machine);
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}
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static MACHINE_CONFIG_START( funkyjet, funkyjet_state )
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@ -130,7 +130,7 @@ static ADDRESS_MAP_START( sgx_mem , AS_PROGRAM, 8, ggconnie_state )
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AM_RANGE( 0x000000, 0x0fffff) AM_ROM
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AM_RANGE( 0x110000, 0x1edfff) AM_NOP
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AM_RANGE( 0x1ee800, 0x1effff) AM_NOP
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AM_RANGE( 0x1f0000, 0x1f5fff) AM_RAM AM_BASE_LEGACY(&pce_user_ram)
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AM_RANGE( 0x1f0000, 0x1f5fff) AM_RAM
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AM_RANGE( 0x1f7000, 0x1f7000) AM_READ_PORT("SWA")
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AM_RANGE( 0x1f7100, 0x1f7100) AM_READ_PORT("SWB")
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AM_RANGE( 0x1f7200, 0x1f7200) AM_READ_PORT("SWC")
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@ -105,12 +105,12 @@ WRITE16_MEMBER(goodejan_state::mahjong_panel_w)
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static ADDRESS_MAP_START( goodejan_map, AS_PROGRAM, 16, goodejan_state )
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AM_RANGE(0x00000, 0x0afff) AM_RAM
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AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_BASE_LEGACY(&seibucrtc_sc0vram)
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AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_BASE_LEGACY(&seibucrtc_sc3vram)
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AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_SHARE("crtc_sc0vram")
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AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_SHARE("crtc_sc3vram")
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AM_RANGE(0x0d000, 0x0dfff) AM_RAM_WRITE(paletteram_xxxxBBBBGGGGRRRR_word_w) AM_SHARE("paletteram")
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/*Guess: these two aren't used/initialized at all.*/
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AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_BASE_LEGACY(&seibucrtc_sc1vram)
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AM_RANGE(0x0e800, 0x0efff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_BASE_LEGACY(&seibucrtc_sc2vram)
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AM_RANGE(0x0e000, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_SHARE("crtc_sc1vram")
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AM_RANGE(0x0e800, 0x0efff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_SHARE("crtc_sc2vram")
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AM_RANGE(0x0f800, 0x0ffff) AM_RAM AM_SHARE("spriteram")
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AM_RANGE(0xc0000, 0xfffff) AM_ROM
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ADDRESS_MAP_END
|
||||
@ -128,12 +128,12 @@ static ADDRESS_MAP_START( common_io_map, AS_IO, 16, goodejan_state )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( totmejan_io_map, AS_IO, 16, goodejan_state )
|
||||
AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_BASE_LEGACY(&seibucrtc_vregs)
|
||||
AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_SHARE("crtc_vregs")
|
||||
AM_IMPORT_FROM(common_io_map)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static ADDRESS_MAP_START( goodejan_io_map, AS_IO, 16, goodejan_state )
|
||||
AM_RANGE(0x8040, 0x807f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_BASE_LEGACY(&seibucrtc_vregs)
|
||||
AM_RANGE(0x8040, 0x807f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_SHARE("crtc_vregs")
|
||||
AM_IMPORT_FROM(common_io_map)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -285,7 +285,7 @@ static ADDRESS_MAP_START( gstriker_map, AS_PROGRAM, 16, gstriker_state )
|
||||
AM_RANGE(0x1c0000, 0x1c0fff) AM_RAM_WRITE(paletteram_xRRRRRGGGGGBBBBB_word_w) AM_SHARE("paletteram")
|
||||
|
||||
AM_RANGE(0x200000, 0x20000f) AM_RAM_WRITE(MB60553_0_regs_w)
|
||||
AM_RANGE(0x200040, 0x20005f) AM_RAM //AM_BASE_LEGACY(&gs_mixer_regs)
|
||||
AM_RANGE(0x200040, 0x20005f) AM_RAM
|
||||
AM_RANGE(0x200060, 0x20007f) AM_RAM
|
||||
AM_RANGE(0x200080, 0x200081) AM_READ_PORT("P1")
|
||||
AM_RANGE(0x200082, 0x200083) AM_READ_PORT("P2")
|
||||
@ -321,7 +321,7 @@ static ADDRESS_MAP_START( vgoal_map, AS_PROGRAM, 16, gstriker_state )
|
||||
AM_RANGE(0x181000, 0x181fff) AM_RAM AM_SHARE("lineram")
|
||||
AM_RANGE(0x1c0000, 0x1c4fff) AM_RAM_WRITE(paletteram_xRRRRRGGGGGBBBBB_word_w) AM_SHARE("paletteram")
|
||||
AM_RANGE(0x200000, 0x20000f) AM_RAM_WRITE(MB60553_0_regs_w)
|
||||
AM_RANGE(0x200040, 0x20005f) AM_RAM //AM_BASE_LEGACY(&gs_mixer_regs)
|
||||
AM_RANGE(0x200040, 0x20005f) AM_RAM
|
||||
|
||||
AM_RANGE(0x200080, 0x200081) AM_READ_PORT("P1")
|
||||
AM_RANGE(0x200082, 0x200083) AM_READ_PORT("P2")
|
||||
|
||||
@ -110,12 +110,8 @@
|
||||
static MACHINE_START(konamigx);
|
||||
static MACHINE_RESET(konamigx);
|
||||
|
||||
UINT32 *gx_psacram, *gx_subpaletteram32;
|
||||
|
||||
static int konamigx_cfgport;
|
||||
|
||||
static UINT32 *gx_workram; /* workram pointer for ESC protection fun */
|
||||
static UINT16 *gx_sndram;
|
||||
static int gx_rdport1_3, gx_syncen;
|
||||
|
||||
static emu_timer *dmadelay_timer;
|
||||
@ -323,17 +319,17 @@ static void generate_sprites(address_space *space, UINT32 src, UINT32 spr, int c
|
||||
|
||||
static void tkmmpzdm_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4)
|
||||
{
|
||||
konamigx_esc_alert(gx_workram, 0x0142, 0x100, 0);
|
||||
konamigx_esc_alert(space->machine().driver_data<konamigx_state>()->m_workram, 0x0142, 0x100, 0);
|
||||
}
|
||||
|
||||
static void dragoonj_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4)
|
||||
{
|
||||
konamigx_esc_alert(gx_workram, 0x5c00, 0x100, 0);
|
||||
konamigx_esc_alert(space->machine().driver_data<konamigx_state>()->m_workram, 0x5c00, 0x100, 0);
|
||||
}
|
||||
|
||||
static void sal2_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4)
|
||||
{
|
||||
konamigx_esc_alert(gx_workram, 0x1c8c, 0x172, 1);
|
||||
konamigx_esc_alert(space->machine().driver_data<konamigx_state>()->m_workram, 0x1c8c, 0x172, 1);
|
||||
}
|
||||
|
||||
static void sexyparo_esc(address_space *space, UINT32 p1, UINT32 p2, UINT32 p3, UINT32 p4)
|
||||
@ -544,7 +540,7 @@ static struct { UINT32 offs, pc, mask, data; } waitskip;
|
||||
|
||||
READ32_MEMBER(konamigx_state::waitskip_r)
|
||||
{
|
||||
UINT32 data = gx_workram[waitskip.offs+offset];
|
||||
UINT32 data = m_workram[waitskip.offs+offset];
|
||||
|
||||
if (space.device().safe_pc() == waitskip.pc && (data & mem_mask) == (waitskip.data & mem_mask))
|
||||
{
|
||||
@ -1158,7 +1154,7 @@ static ADDRESS_MAP_START( gx_base_memmap, AS_PROGRAM, 32, konamigx_state )
|
||||
AM_RANGE(0x000000, 0x01ffff) AM_ROM // BIOS ROM
|
||||
AM_RANGE(0x200000, 0x3fffff) AM_ROM // main program ROM
|
||||
AM_RANGE(0x400000, 0x7fffff) AM_ROM // data ROM
|
||||
AM_RANGE(0xc00000, 0xc1ffff) AM_RAM AM_BASE_LEGACY(&gx_workram) // work RAM
|
||||
AM_RANGE(0xc00000, 0xc1ffff) AM_RAM AM_SHARE("workram") // work RAM
|
||||
AM_RANGE(0xd00000, 0xd01fff) AM_READ_LEGACY(K056832_5bpp_rom_long_r)
|
||||
AM_RANGE(0xd20000, 0xd20fff) AM_READWRITE_LEGACY(K053247_long_r, K053247_long_w)
|
||||
AM_RANGE(0xd21000, 0xd23fff) AM_RAM
|
||||
@ -1198,7 +1194,7 @@ static ADDRESS_MAP_START( gx_type1_map, AS_PROGRAM, 32, konamigx_state )
|
||||
AM_RANGE(0xe20000, 0xe2000f) AM_WRITENOP
|
||||
AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
|
||||
AM_RANGE(0xe80000, 0xe81fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) // chips 21L+19L / S
|
||||
AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_BASE_LEGACY(&gx_psacram) // chips 20J+23J+18J / S
|
||||
AM_RANGE(0xec0000, 0xedffff) AM_RAM_WRITE(konamigx_t1_psacmap_w) AM_SHARE("psacram") // chips 20J+23J+18J / S
|
||||
AM_RANGE(0xf00000, 0xf3ffff) AM_READ(type1_roz_r1) // ROM readback
|
||||
AM_RANGE(0xf40000, 0xf7ffff) AM_READ(type1_roz_r2) // ROM readback
|
||||
AM_RANGE(0xf80000, 0xf80fff) AM_RAM // chip 21Q / S
|
||||
@ -1220,7 +1216,7 @@ static ADDRESS_MAP_START( gx_type3_map, AS_PROGRAM, 32, konamigx_state )
|
||||
AM_RANGE(0xe40000, 0xe40003) AM_WRITE(konamigx_type3_psac2_bank_w) AM_BASE_LEGACY(&konamigx_type3_psac2_bank)
|
||||
AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl)
|
||||
AM_RANGE(0xe80000, 0xe83fff) AM_RAM AM_SHARE("paletteram") // main monitor palette
|
||||
AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_BASE_LEGACY(&gx_subpaletteram32)
|
||||
AM_RANGE(0xea0000, 0xea3fff) AM_RAM AM_SHARE("subpaletteram")
|
||||
AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r)
|
||||
//AM_RANGE(0xf00000, 0xf07fff) AM_RAM
|
||||
AM_IMPORT_FROM(gx_base_memmap)
|
||||
@ -1234,9 +1230,9 @@ static ADDRESS_MAP_START( gx_type4_map, AS_PROGRAM, 32, konamigx_state )
|
||||
AM_RANGE(0xe40000, 0xe40003) AM_WRITENOP
|
||||
AM_RANGE(0xe60000, 0xe60fff) AM_RAM AM_BASE_LEGACY((UINT32**)&K053936_0_linectrl) // 29C & 29G (PSAC2 line control)
|
||||
AM_RANGE(0xe80000, 0xe87fff) AM_RAM AM_SHARE("paletteram") // 11G/13G/15G (main screen palette RAM)
|
||||
AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_BASE_LEGACY(&gx_subpaletteram32) // 5G/7G/9G (sub screen palette RAM)
|
||||
AM_RANGE(0xea0000, 0xea7fff) AM_RAM AM_SHARE("subpaletteram") // 5G/7G/9G (sub screen palette RAM)
|
||||
AM_RANGE(0xec0000, 0xec0003) AM_READ(type3_sync_r) // type 4 polls this too
|
||||
AM_RANGE(0xf00000, 0xf07fff) AM_RAM_WRITE(konamigx_t4_psacmap_w) AM_BASE_LEGACY(&gx_psacram) // PSAC2 tilemap
|
||||
AM_RANGE(0xf00000, 0xf07fff) AM_RAM_WRITE(konamigx_t4_psacmap_w) AM_SHARE("psacram") // PSAC2 tilemap
|
||||
// AM_RANGE(0xf00000, 0xf07fff) AM_RAM
|
||||
AM_IMPORT_FROM(gx_base_memmap)
|
||||
ADDRESS_MAP_END
|
||||
@ -1290,7 +1286,7 @@ WRITE16_MEMBER(konamigx_state::tms57002_control_word_w)
|
||||
/* 68000 memory handling */
|
||||
static ADDRESS_MAP_START( gxsndmap, AS_PROGRAM, 16, konamigx_state )
|
||||
AM_RANGE(0x000000, 0x03ffff) AM_ROM
|
||||
AM_RANGE(0x100000, 0x10ffff) AM_RAM AM_BASE_LEGACY(&gx_sndram)
|
||||
AM_RANGE(0x100000, 0x10ffff) AM_RAM
|
||||
AM_RANGE(0x200000, 0x2004ff) AM_DEVREADWRITE8("konami1", k054539_device, read, write, 0xff00)
|
||||
AM_RANGE(0x200000, 0x2004ff) AM_DEVREADWRITE8("konami2", k054539_device, read, write, 0x00ff)
|
||||
AM_RANGE(0x300000, 0x300001) AM_READWRITE(tms57002_data_word_r, tms57002_data_word_w)
|
||||
|
||||
@ -76,7 +76,7 @@ INPUT_PORTS_END
|
||||
|
||||
static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, paranoia_state )
|
||||
AM_RANGE( 0x000000, 0x03FFFF) AM_ROM
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_BASE_LEGACY(&pce_user_ram )
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
|
||||
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
|
||||
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
|
||||
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w )
|
||||
|
||||
@ -90,7 +90,7 @@ static ADDRESS_MAP_START( pktgaldx_map, AS_PROGRAM, 16, pktgaldx_state )
|
||||
|
||||
AM_RANGE(0x161800, 0x16180f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
|
||||
AM_RANGE(0x164800, 0x164801) AM_WRITE(pktgaldx_oki_bank_w)
|
||||
AM_RANGE(0x167800, 0x167fff) AM_READWRITE_LEGACY(deco16_104_pktgaldx_prot_r,deco16_104_pktgaldx_prot_w) AM_BASE_LEGACY(&deco16_prot_ram)
|
||||
AM_RANGE(0x167800, 0x167fff) AM_READWRITE_LEGACY(deco16_104_pktgaldx_prot_r,deco16_104_pktgaldx_prot_w) AM_SHARE("prot16ram")
|
||||
AM_RANGE(0x170000, 0x17ffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -320,6 +320,8 @@ static MACHINE_START( pktgaldx )
|
||||
|
||||
state->m_maincpu = machine.device<cpu_device>("maincpu");
|
||||
state->m_deco_tilegen1 = machine.device("tilegen1");
|
||||
|
||||
decoprot_reset(machine);
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_START( pktgaldx, pktgaldx_state )
|
||||
|
||||
@ -138,7 +138,7 @@ static ADDRESS_MAP_START( rohga_map, AS_PROGRAM, 16, rohga_state )
|
||||
AM_RANGE(0x200000, 0x20000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
|
||||
AM_RANGE(0x240000, 0x24000f) AM_DEVWRITE_LEGACY("tilegen2", deco16ic_pf_control_w)
|
||||
|
||||
AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
|
||||
AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_SHARE("prot16ram") /* Protection device */
|
||||
|
||||
AM_RANGE(0x2c0000, 0x2c0001) AM_READ_PORT("DSW3")
|
||||
|
||||
@ -191,7 +191,7 @@ static ADDRESS_MAP_START( wizdfire_map, AS_PROGRAM, 16, rohga_state )
|
||||
AM_RANGE(0x380000, 0x381fff) AM_RAM_DEVWRITE_LEGACY("deco_common", decocomn_buffered_palette_w) AM_SHARE("paletteram")
|
||||
AM_RANGE(0x390008, 0x390009) AM_DEVWRITE_LEGACY("deco_common", decocomn_palette_dma_w)
|
||||
|
||||
AM_RANGE(0xfe4000, 0xfe47ff) AM_READWRITE_LEGACY(deco16_104_prot_r,deco16_104_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
|
||||
AM_RANGE(0xfe4000, 0xfe47ff) AM_READWRITE_LEGACY(deco16_104_prot_r,deco16_104_prot_w) AM_SHARE("prot16ram") /* Protection device */
|
||||
AM_RANGE(0xfdc000, 0xffffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -224,7 +224,7 @@ static ADDRESS_MAP_START( nitrobal_map, AS_PROGRAM, 16, rohga_state )
|
||||
AM_RANGE(0x390008, 0x390009) AM_DEVWRITE_LEGACY("deco_common", decocomn_palette_dma_w)
|
||||
|
||||
AM_RANGE(0xfec000, 0xff3fff) AM_RAM
|
||||
AM_RANGE(0xff4000, 0xff47ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_146_nitroball_prot_r,deco16_146_nitroball_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
|
||||
AM_RANGE(0xff4000, 0xff47ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_146_nitroball_prot_r,deco16_146_nitroball_prot_w) AM_SHARE("prot16ram") /* Protection device */
|
||||
AM_RANGE(0xff8000, 0xffffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -232,7 +232,7 @@ static ADDRESS_MAP_START( schmeisr_map, AS_PROGRAM, 16, rohga_state )
|
||||
AM_RANGE(0x000000, 0x0fffff) AM_ROM
|
||||
AM_RANGE(0x200000, 0x20000f) AM_DEVWRITE_LEGACY("tilegen1", deco16ic_pf_control_w)
|
||||
AM_RANGE(0x240000, 0x24000f) AM_DEVWRITE_LEGACY("tilegen2", deco16ic_pf_control_w)
|
||||
AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_BASE_LEGACY(&deco16_prot_ram) /* Protection device */
|
||||
AM_RANGE(0x280000, 0x2807ff) AM_MIRROR(0x800) AM_READWRITE_LEGACY(deco16_104_rohga_prot_r,deco16_104_rohga_prot_w) AM_SHARE("prot16ram") /* Protection device */
|
||||
|
||||
AM_RANGE(0x2c0000, 0x2c0001) AM_READ_PORT("DSW3")
|
||||
AM_RANGE(0x300000, 0x300001) AM_READ_PORT("DSW3") AM_WRITE(rohga_buffer_spriteram16_w) /* write 1 for sprite dma */
|
||||
@ -1544,6 +1544,8 @@ DRIVER_INIT_MEMBER(rohga_state,wizdfire)
|
||||
deco74_decrypt_gfx(machine(), "gfx1");
|
||||
deco74_decrypt_gfx(machine(), "gfx2");
|
||||
deco74_decrypt_gfx(machine(), "gfx3");
|
||||
|
||||
decoprot_reset(machine());
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(rohga_state,nitrobal)
|
||||
|
||||
@ -117,10 +117,10 @@ READ16_MEMBER(sengokmj_state::sengokmj_system_r)
|
||||
static ADDRESS_MAP_START( sengokmj_map, AS_PROGRAM, 16, sengokmj_state )
|
||||
AM_RANGE(0x00000, 0x07fff) AM_RAM
|
||||
AM_RANGE(0x08000, 0x09fff) AM_RAM AM_SHARE("nvram")
|
||||
AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_BASE_LEGACY(&seibucrtc_sc0vram)
|
||||
AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_BASE_LEGACY(&seibucrtc_sc1vram)
|
||||
AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_BASE_LEGACY(&seibucrtc_sc2vram)
|
||||
AM_RANGE(0x0d800, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_BASE_LEGACY(&seibucrtc_sc3vram)
|
||||
AM_RANGE(0x0c000, 0x0c7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc0vram_w) AM_SHARE("crtc_sc0vram")
|
||||
AM_RANGE(0x0c800, 0x0cfff) AM_RAM_WRITE_LEGACY(seibucrtc_sc1vram_w) AM_SHARE("crtc_sc1vram")
|
||||
AM_RANGE(0x0d000, 0x0d7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc2vram_w) AM_SHARE("crtc_sc2vram")
|
||||
AM_RANGE(0x0d800, 0x0e7ff) AM_RAM_WRITE_LEGACY(seibucrtc_sc3vram_w) AM_SHARE("crtc_sc3vram")
|
||||
AM_RANGE(0x0e800, 0x0f7ff) AM_RAM_WRITE(paletteram_xBBBBBGGGGGRRRRR_word_w) AM_SHARE("paletteram")
|
||||
AM_RANGE(0x0f800, 0x0ffff) AM_RAM AM_SHARE("spriteram")
|
||||
AM_RANGE(0xc0000, 0xfffff) AM_ROM
|
||||
@ -129,7 +129,7 @@ ADDRESS_MAP_END
|
||||
static ADDRESS_MAP_START( sengokmj_io_map, AS_IO, 16, sengokmj_state )
|
||||
AM_RANGE(0x4000, 0x400f) AM_READWRITE_LEGACY(seibu_main_word_r, seibu_main_word_w)
|
||||
/*Areas from 8000-804f are for the custom Seibu CRTC.*/
|
||||
AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_BASE_LEGACY(&seibucrtc_vregs)
|
||||
AM_RANGE(0x8000, 0x804f) AM_RAM_WRITE_LEGACY(seibucrtc_vregs_w) AM_SHARE("crtc_vregs")
|
||||
|
||||
// AM_RANGE(0x8080, 0x8081) CRTC extra register?
|
||||
// AM_RANGE(0x80c0, 0x80c1) CRTC extra register?
|
||||
|
||||
@ -280,7 +280,7 @@ INPUT_PORTS_END
|
||||
|
||||
static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, tourvision_state )
|
||||
AM_RANGE( 0x000000, 0x0FFFFF) AM_ROM
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_BASE_LEGACY(&pce_user_ram )
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
|
||||
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
|
||||
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
|
||||
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w )
|
||||
|
||||
@ -285,7 +285,7 @@ INPUT_PORTS_END
|
||||
|
||||
static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, uapce_state )
|
||||
AM_RANGE( 0x000000, 0x09FFFF) AM_ROM
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_BASE_LEGACY(&pce_user_ram )
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
|
||||
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE_LEGACY(vdc_0_r, vdc_0_w )
|
||||
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE_LEGACY(vce_r, vce_w )
|
||||
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE_LEGACY("c6280", c6280_r, c6280_w )
|
||||
|
||||
@ -36,8 +36,6 @@
|
||||
|
||||
/*----------- defined in machine/archimds.c -----------*/
|
||||
|
||||
extern UINT32 *archimedes_memc_physmem;
|
||||
|
||||
void archimedes_init(running_machine &machine); // call at MACHINE_INIT
|
||||
void archimedes_reset(running_machine &machine); // call at MACHINE_RESET
|
||||
void archimedes_driver_init(running_machine &machine); // call at DRIVER_INIT
|
||||
|
||||
@ -8,7 +8,8 @@ class asuka_state : public driver_device
|
||||
{
|
||||
public:
|
||||
asuka_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag) { }
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_cadash_shared_ram(*this, "sharedram") { }
|
||||
|
||||
/* memory pointers */
|
||||
// UINT16 * paletteram; // this currently uses generic palette handlers
|
||||
@ -28,6 +29,8 @@ public:
|
||||
/* misc */
|
||||
int m_adpcm_pos;
|
||||
int m_adpcm_data;
|
||||
|
||||
optional_shared_ptr<UINT8> m_cadash_shared_ram;
|
||||
|
||||
/* devices */
|
||||
cpu_device *m_maincpu;
|
||||
|
||||
@ -22,8 +22,5 @@ WRITE32_HANDLER( deco16_146_fghthist_prot_w );
|
||||
|
||||
void decoprot_reset(running_machine &machine);
|
||||
|
||||
extern UINT16 *deco16_prot_ram;
|
||||
extern UINT32 *deco32_prot_ram;
|
||||
|
||||
READ16_HANDLER( dietgo_104_prot_r );
|
||||
WRITE16_HANDLER( dietgo_104_prot_w );
|
||||
|
||||
@ -3,10 +3,16 @@ class konamigx_state : public driver_device
|
||||
public:
|
||||
konamigx_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this,"maincpu")
|
||||
m_maincpu(*this,"maincpu"),
|
||||
m_workram(*this,"workram"),
|
||||
m_psacram(*this,"psacram"),
|
||||
m_subpaletteram32(*this,"subpaletteram")
|
||||
{ }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_shared_ptr<UINT32> m_workram;
|
||||
optional_shared_ptr<UINT32> m_psacram;
|
||||
optional_shared_ptr<UINT32> m_subpaletteram32;
|
||||
DECLARE_WRITE32_MEMBER(esc_w);
|
||||
DECLARE_WRITE32_MEMBER(eeprom_w);
|
||||
DECLARE_WRITE32_MEMBER(control_w);
|
||||
@ -52,11 +58,6 @@ public:
|
||||
};
|
||||
|
||||
|
||||
/*----------- defined in drivers/konamigx.c -----------*/
|
||||
|
||||
extern UINT32 *gx_psacram, *gx_subpaletteram32;
|
||||
|
||||
|
||||
/*----------- defined in video/konamigx.c -----------*/
|
||||
|
||||
// 2nd-Tier GX/MW Hardware Functions
|
||||
|
||||
@ -1,7 +1,5 @@
|
||||
/*----------- defined in video/sei_crtc.c -----------*/
|
||||
|
||||
extern UINT16 *seibucrtc_sc0vram,*seibucrtc_sc1vram,*seibucrtc_sc2vram,*seibucrtc_sc3vram;
|
||||
extern UINT16 *seibucrtc_vregs;
|
||||
extern UINT16 seibucrtc_sc0bank;
|
||||
|
||||
WRITE16_HANDLER( seibucrtc_sc0vram_w );
|
||||
|
||||
@ -38,7 +38,7 @@ static const int page_sizes[4] = { 4096, 8192, 16384, 32768 };
|
||||
|
||||
#define IOC_LOG 0
|
||||
|
||||
UINT32 *archimedes_memc_physmem;
|
||||
static UINT32 *archimedes_memc_physmem;
|
||||
static UINT32 memc_pagesize;
|
||||
static int memc_latchrom;
|
||||
static UINT32 ioc_timercnt[4], ioc_timerout[4];
|
||||
@ -422,6 +422,7 @@ DIRECT_UPDATE_HANDLER( a310_setopbase )
|
||||
|
||||
void archimedes_driver_init(running_machine &machine)
|
||||
{
|
||||
archimedes_memc_physmem = reinterpret_cast<UINT32 *>(machine.root_device().memshare("physicalram")->ptr());
|
||||
// address_space *space = machine.device<arm_device>("maincpu")->space(AS_PROGRAM);
|
||||
// space->set_direct_update_handler(direct_update_delegate(FUNC(a310_setopbase), &machine));
|
||||
}
|
||||
|
||||
@ -83,8 +83,8 @@ static int decoprot_last_write=0, decoprot_last_write_val=0;
|
||||
static UINT16 decoprot_buffer_ram[0x800];
|
||||
static UINT16 decoprot_buffer_ram2[0x800];
|
||||
|
||||
UINT16 *deco16_prot_ram;
|
||||
UINT32 *deco32_prot_ram;
|
||||
static UINT16 *deco16_prot_ram;
|
||||
static UINT32 *deco32_prot_ram;
|
||||
|
||||
/***************************************************************************/
|
||||
|
||||
@ -94,6 +94,9 @@ void decoprot_reset(running_machine &machine)
|
||||
deco16_mask=0xffff;
|
||||
decoprot_last_write=decoprot_last_write_val=0;
|
||||
decoprot_buffer_ram_selected=0;
|
||||
|
||||
deco16_prot_ram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("prot16ram")->ptr());
|
||||
deco32_prot_ram = reinterpret_cast<UINT32 *>(machine.root_device().memshare("prot32ram")->ptr());
|
||||
|
||||
state_save_register_global(machine, deco16_xor);
|
||||
state_save_register_global(machine, deco16_mask);
|
||||
|
||||
@ -5,8 +5,6 @@
|
||||
#include "cpu/h6280/h6280.h"
|
||||
|
||||
/* system RAM */
|
||||
unsigned char *pce_user_ram; /* scratch RAM at F8 */
|
||||
|
||||
struct pce_struct pce;
|
||||
|
||||
/* joystick related data*/
|
||||
|
||||
@ -11,7 +11,6 @@
|
||||
|
||||
#define PCE_MAIN_CLOCK 21477270
|
||||
|
||||
extern unsigned char *pce_user_ram; /* scratch RAM at F8 */
|
||||
WRITE8_HANDLER ( pce_joystick_w );
|
||||
READ8_HANDLER ( pce_joystick_r );
|
||||
|
||||
|
||||
@ -1817,18 +1817,18 @@ TILE_GET_INFO_MEMBER(konamigx_state::get_gx_psac_tile_info)
|
||||
int tileno, colour, col, flip = 0;
|
||||
if (tile_index&1)
|
||||
{
|
||||
tileno = gx_psacram[tile_index/2] & 0x00001fff;
|
||||
col =(gx_psacram[tile_index/2] & 0x00002000)>>13;
|
||||
if (gx_psacram[tile_index/2] & 0x00004000) flip |= TILE_FLIPX;
|
||||
if (gx_psacram[tile_index/2] & 0x00008000) flip |= TILE_FLIPY;
|
||||
tileno = m_psacram[tile_index/2] & 0x00001fff;
|
||||
col =(m_psacram[tile_index/2] & 0x00002000)>>13;
|
||||
if (m_psacram[tile_index/2] & 0x00004000) flip |= TILE_FLIPX;
|
||||
if (m_psacram[tile_index/2] & 0x00008000) flip |= TILE_FLIPY;
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
tileno = (gx_psacram[tile_index/2] & 0x1fff0000)>>16;
|
||||
col = (gx_psacram[tile_index/2] & 0x20000000)>>29;
|
||||
if (gx_psacram[tile_index/2] & 0x40000000) flip |= TILE_FLIPX;
|
||||
if (gx_psacram[tile_index/2] & 0x80000000) flip |= TILE_FLIPY;
|
||||
tileno = (m_psacram[tile_index/2] & 0x1fff0000)>>16;
|
||||
col = (m_psacram[tile_index/2] & 0x20000000)>>29;
|
||||
if (m_psacram[tile_index/2] & 0x40000000) flip |= TILE_FLIPX;
|
||||
if (m_psacram[tile_index/2] & 0x80000000) flip |= TILE_FLIPY;
|
||||
|
||||
}
|
||||
|
||||
@ -1913,14 +1913,14 @@ TILE_GET_INFO_MEMBER(konamigx_state::get_gx_psac1a_tile_info)
|
||||
flip=0;
|
||||
colour = 0;
|
||||
|
||||
tileno = (gx_psacram[tile_index*2] & 0x00003fff)>>0;
|
||||
tileno = (m_psacram[tile_index*2] & 0x00003fff)>>0;
|
||||
|
||||
// scanrows
|
||||
//flipx = (gx_psacram[tile_index*2+1] & 0x00800000)>>23;
|
||||
//flipy = (gx_psacram[tile_index*2+1] & 0x00400000)>>22;
|
||||
//flipx = (m_psacram[tile_index*2+1] & 0x00800000)>>23;
|
||||
//flipy = (m_psacram[tile_index*2+1] & 0x00400000)>>22;
|
||||
// scancols
|
||||
flipy = (gx_psacram[tile_index*2+1] & 0x00800000)>>23;
|
||||
flipx = (gx_psacram[tile_index*2+1] & 0x00400000)>>22;
|
||||
flipy = (m_psacram[tile_index*2+1] & 0x00800000)>>23;
|
||||
flipx = (m_psacram[tile_index*2+1] & 0x00400000)>>22;
|
||||
|
||||
if (flipx) flip |= TILE_FLIPX;
|
||||
if (flipy) flip |= TILE_FLIPY;
|
||||
@ -1935,14 +1935,14 @@ TILE_GET_INFO_MEMBER(konamigx_state::get_gx_psac1b_tile_info)
|
||||
flip=0;
|
||||
|
||||
colour = 0;
|
||||
tileno = (gx_psacram[tile_index*2+1] & 0x00003fff)>>0;
|
||||
tileno = (m_psacram[tile_index*2+1] & 0x00003fff)>>0;
|
||||
|
||||
// scanrows
|
||||
//flipx = (gx_psacram[tile_index*2+1] & 0x00800000)>>23;
|
||||
//flipy = (gx_psacram[tile_index*2+1] & 0x00400000)>>22;
|
||||
//flipx = (m_psacram[tile_index*2+1] & 0x00800000)>>23;
|
||||
//flipy = (m_psacram[tile_index*2+1] & 0x00400000)>>22;
|
||||
// scancols
|
||||
flipy = (gx_psacram[tile_index*2+1] & 0x00200000)>>21;
|
||||
flipx = (gx_psacram[tile_index*2+1] & 0x00100000)>>20;
|
||||
flipy = (m_psacram[tile_index*2+1] & 0x00200000)>>21;
|
||||
flipx = (m_psacram[tile_index*2+1] & 0x00100000)>>20;
|
||||
|
||||
if (flipx) flip |= TILE_FLIPX;
|
||||
if (flipy) flip |= TILE_FLIPY;
|
||||
@ -2547,6 +2547,8 @@ SCREEN_UPDATE_RGB32(konamigx_left)
|
||||
|
||||
SCREEN_UPDATE_RGB32(konamigx_right)
|
||||
{
|
||||
konamigx_state *state = screen.machine().driver_data<konamigx_state>();
|
||||
|
||||
if (konamigx_current_frame==1)
|
||||
{
|
||||
copybitmap(bitmap, *dualscreen_right_tempbitmap, 0, 0, 0, 0, cliprect);
|
||||
@ -2560,7 +2562,7 @@ SCREEN_UPDATE_RGB32(konamigx_right)
|
||||
{
|
||||
for (offset=0;offset<0x4000/4;offset++)
|
||||
{
|
||||
UINT32 coldat = gx_subpaletteram32[offset];
|
||||
UINT32 coldat = state->m_subpaletteram32[offset];
|
||||
|
||||
set_color_555(screen.machine(), offset*2, 0, 5, 10,coldat >> 16);
|
||||
set_color_555(screen.machine(), offset*2+1, 0, 5, 10,coldat & 0xffff);
|
||||
@ -2572,9 +2574,9 @@ SCREEN_UPDATE_RGB32(konamigx_right)
|
||||
{
|
||||
int r,g,b;
|
||||
|
||||
r = (gx_subpaletteram32[offset] >>16) & 0xff;
|
||||
g = (gx_subpaletteram32[offset] >> 8) & 0xff;
|
||||
b = (gx_subpaletteram32[offset] >> 0) & 0xff;
|
||||
r = (state->m_subpaletteram32[offset] >>16) & 0xff;
|
||||
g = (state->m_subpaletteram32[offset] >> 8) & 0xff;
|
||||
b = (state->m_subpaletteram32[offset] >> 0) & 0xff;
|
||||
|
||||
palette_set_color(screen.machine(),offset,MAKE_RGB(r,g,b));
|
||||
}
|
||||
@ -2606,11 +2608,11 @@ WRITE32_MEMBER(konamigx_state::konamigx_palette2_w)
|
||||
{
|
||||
int r,g,b;
|
||||
|
||||
COMBINE_DATA(&gx_subpaletteram32[offset]);
|
||||
COMBINE_DATA(&state->m_subpaletteram32[offset]);
|
||||
|
||||
r = (gx_subpaletteram32[offset] >>16) & 0xff;
|
||||
g = (gx_subpaletteram32[offset] >> 8) & 0xff;
|
||||
b = (gx_subpaletteram32[offset] >> 0) & 0xff;
|
||||
r = (state->m_subpaletteram32[offset] >>16) & 0xff;
|
||||
g = (state->m_subpaletteram32[offset] >> 8) & 0xff;
|
||||
b = (state->m_subpaletteram32[offset] >> 0) & 0xff;
|
||||
|
||||
offset += (0x8000/4);
|
||||
|
||||
@ -2640,8 +2642,8 @@ WRITE32_MEMBER(konamigx_state::konamigx_555_palette_w)
|
||||
WRITE32_MEMBER(konamigx_state::konamigx_555_palette2_w)
|
||||
{
|
||||
UINT32 coldat;
|
||||
COMBINE_DATA(&gx_subpaletteram32[offset]);
|
||||
coldat = gx_subpaletteram32[offset];
|
||||
COMBINE_DATA(&state->m_subpaletteram32[offset]);
|
||||
coldat = state->m_subpaletteram32[offset];
|
||||
|
||||
offset += (0x4000/4);
|
||||
|
||||
@ -2666,7 +2668,7 @@ WRITE32_MEMBER(konamigx_state::konamigx_tilebank_w)
|
||||
// type 1 RAM-based PSAC tilemap
|
||||
WRITE32_MEMBER(konamigx_state::konamigx_t1_psacmap_w)
|
||||
{
|
||||
COMBINE_DATA(&gx_psacram[offset]);
|
||||
COMBINE_DATA(&m_psacram[offset]);
|
||||
gx_psac_tilemap->mark_tile_dirty(offset/2);
|
||||
gx_psac_tilemap2->mark_tile_dirty(offset/2);
|
||||
}
|
||||
@ -2674,7 +2676,7 @@ WRITE32_MEMBER(konamigx_state::konamigx_t1_psacmap_w)
|
||||
// type 4 RAM-based PSAC tilemap
|
||||
WRITE32_MEMBER(konamigx_state::konamigx_t4_psacmap_w)
|
||||
{
|
||||
COMBINE_DATA(&gx_psacram[offset]);
|
||||
COMBINE_DATA(&m_psacram[offset]);
|
||||
|
||||
gx_psac_tilemap->mark_tile_dirty(offset*2);
|
||||
gx_psac_tilemap->mark_tile_dirty((offset*2)+1);
|
||||
|
||||
@ -60,8 +60,8 @@ List of default vregs (title screen):
|
||||
#include "includes/sei_crtc.h"
|
||||
|
||||
static tilemap_t *sc0_tilemap,*sc2_tilemap,*sc1_tilemap,*sc3_tilemap_0,*sc3_tilemap_1;
|
||||
UINT16 *seibucrtc_sc0vram,*seibucrtc_sc1vram,*seibucrtc_sc2vram,*seibucrtc_sc3vram;
|
||||
UINT16 *seibucrtc_vregs;
|
||||
static UINT16 *seibucrtc_sc0vram,*seibucrtc_sc1vram,*seibucrtc_sc2vram,*seibucrtc_sc3vram;
|
||||
static UINT16 *seibucrtc_vregs;
|
||||
UINT16 seibucrtc_sc0bank;
|
||||
|
||||
/*******************************
|
||||
@ -255,6 +255,12 @@ static void draw_sprites(running_machine &machine, bitmap_ind16 &bitmap,const re
|
||||
|
||||
VIDEO_START( seibu_crtc )
|
||||
{
|
||||
seibucrtc_sc0vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc0vram")->ptr());
|
||||
seibucrtc_sc1vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc1vram")->ptr());
|
||||
seibucrtc_sc2vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc2vram")->ptr());
|
||||
seibucrtc_sc3vram = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_sc3vram")->ptr());
|
||||
seibucrtc_vregs = reinterpret_cast<UINT16 *>(machine.root_device().memshare("crtc_vregs")->ptr());
|
||||
|
||||
sc0_tilemap = tilemap_create(machine, seibucrtc_sc0_tile_info,TILEMAP_SCAN_ROWS,16,16,32,32);
|
||||
sc2_tilemap = tilemap_create(machine, seibucrtc_sc2_tile_info,TILEMAP_SCAN_ROWS,16,16,32,32);
|
||||
sc1_tilemap = tilemap_create(machine, seibucrtc_sc1_tile_info,TILEMAP_SCAN_ROWS,16,16,32,32);
|
||||
|
||||
@ -69,7 +69,10 @@ class a310_state : public driver_device
|
||||
{
|
||||
public:
|
||||
a310_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag) { }
|
||||
: driver_device(mconfig, type, tag),
|
||||
m_physram(*this, "physicalram") { }
|
||||
|
||||
required_shared_ptr<UINT32> m_physram;
|
||||
|
||||
DECLARE_READ32_MEMBER(a310_psy_wram_r);
|
||||
DECLARE_WRITE32_MEMBER(a310_psy_wram_w);
|
||||
@ -95,19 +98,18 @@ static WRITE_LINE_DEVICE_HANDLER( a310_wd177x_drq_w )
|
||||
|
||||
READ32_MEMBER(a310_state::a310_psy_wram_r)
|
||||
{
|
||||
return archimedes_memc_physmem[offset];
|
||||
return m_physram[offset];
|
||||
}
|
||||
|
||||
WRITE32_MEMBER(a310_state::a310_psy_wram_w)
|
||||
{
|
||||
COMBINE_DATA(&archimedes_memc_physmem[offset]);
|
||||
COMBINE_DATA(&m_physram[offset]);
|
||||
}
|
||||
|
||||
|
||||
DRIVER_INIT_MEMBER(a310_state,a310)
|
||||
{
|
||||
UINT32 ram_size = machine().device<ram_device>(RAM_TAG)->size();
|
||||
archimedes_memc_physmem = auto_alloc_array(machine(), UINT32, 0x01000000);
|
||||
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_readwrite_handler( 0x02000000, 0x02000000+(ram_size-1), read32_delegate(FUNC(a310_state::a310_psy_wram_r), this), write32_delegate(FUNC(a310_state::a310_psy_wram_w), this));
|
||||
|
||||
@ -129,7 +131,7 @@ static MACHINE_RESET( a310 )
|
||||
|
||||
static ADDRESS_MAP_START( a310_mem, AS_PROGRAM, 32, a310_state )
|
||||
AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE_LEGACY(archimedes_memc_logical_r, archimedes_memc_logical_w)
|
||||
// AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE_LEGACY(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
|
||||
AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_SHARE("physicalram") /* physical RAM - 16 MB for now, should be 512k for the A310 */
|
||||
AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE_LEGACY(archimedes_ioc_r, archimedes_ioc_w)
|
||||
AM_RANGE(0x03400000, 0x035fffff) AM_READWRITE_LEGACY(archimedes_vidc_r, archimedes_vidc_w)
|
||||
AM_RANGE(0x03600000, 0x037fffff) AM_READWRITE_LEGACY(archimedes_memc_r, archimedes_memc_w)
|
||||
|
||||
@ -53,7 +53,7 @@ ADDRESS_MAP_END
|
||||
#if 0
|
||||
static ADDRESS_MAP_START( pce_mem , AS_PROGRAM, 8, x1twin_state )
|
||||
AM_RANGE( 0x000000, 0x09FFFF) AM_ROM
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000) AM_BASE(&pce_user_ram )
|
||||
AM_RANGE( 0x1F0000, 0x1F1FFF) AM_RAM AM_MIRROR(0x6000)
|
||||
AM_RANGE( 0x1FE000, 0x1FE3FF) AM_READWRITE( vdc_0_r, vdc_0_w )
|
||||
AM_RANGE( 0x1FE400, 0x1FE7FF) AM_READWRITE( vce_r, vce_w )
|
||||
AM_RANGE( 0x1FE800, 0x1FEBFF) AM_DEVREADWRITE( "c6280", c6280_r, c6280_w )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user