mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
m68hc05: implement edge-sensitive external interrupts
This commit is contained in:
Vas Crabb
parent
2ba14a09f8
commit
dc27585476
@ -552,13 +552,13 @@ OP_HANDLER( swi )
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// $8E STOP inherent ----
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OP_HANDLER( stop )
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{
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fatalerror("m6805: unimplemented STOP");
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fatalerror("m6805[%s]: unimplemented STOP", tag());
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}
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// $8F WAIT inherent ----
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OP_HANDLER( wait )
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{
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fatalerror("m6805: unimplemented WAIT");
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fatalerror("m6805[%s]: unimplemented WAIT", tag());
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}
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@ -78,6 +78,8 @@ constexpr u16 M68705_VECTOR_INT = 0xfffa;
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constexpr u16 M68705_VECTOR_SWI = 0xfffc;
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constexpr u16 M68705_VECTOR_RESET = 0xfffe;
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constexpr u16 M68705_INT_MASK = 0x03;
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} // anonymous namespace
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@ -352,7 +352,6 @@ protected:
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* 68705 section
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****************************************************************************/
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#define M68705_INT_MASK 0x03
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#define M68705_IRQ_LINE (M6805_IRQ_LINE + 0)
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#define M68705_INT_TIMER (M6805_IRQ_LINE + 1)
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#define M68705_VPP_LINE (M6805_IRQ_LINE + 2)
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@ -72,10 +72,15 @@ ROM_END
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//constexpr u16 M68HC05_VECTOR_SPI = 0xfff4;
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//constexpr u16 M68HC05_VECTOR_SCI = 0xfff6;
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constexpr u16 M68HC05_VECTOR_TIMER = 0xfff8;
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//constexpr u16 M68HC05_VECTOR_INT = 0xfffa;
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constexpr u16 M68HC05_VECTOR_IRQ = 0xfffa;
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constexpr u16 M68HC05_VECTOR_SWI = 0xfffc;
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//constexpr u16 M68HC05_VECTOR_RESET = 0xfffe;
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constexpr u16 M68HC05_INT_IRQ = u16(1) << 0;
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constexpr u16 M68HC05_INT_TIMER = u16(1) << 1;
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constexpr u16 M68HC05_INT_MASK = M68HC05_INT_IRQ | M68HC05_INT_TIMER;
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} // anonymous namespace
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@ -118,9 +123,13 @@ m68hc05_device::m68hc05_device(
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, m_port_cb_r{ *this, *this, *this, *this }
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, m_port_cb_w{ *this, *this, *this, *this }
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, m_port_bits{ 0xff, 0xff, 0xff, 0xff }
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, m_port_interrupt{ 0x00, 0x00, 0x00, 0x00 }
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, m_port_input{ 0xff, 0xff, 0xff, 0xff }
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, m_port_latch{ 0xff, 0xff, 0xff, 0xff }
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, m_port_ddr{ 0x00, 0x00, 0x00, 0x00 }
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, m_port_irq_state(false)
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, m_irq_line_state(false)
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, m_irq_latch(0)
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, m_tcmp_cb(*this)
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, m_tcap_state(false)
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, m_tcr(0x00)
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@ -139,28 +148,43 @@ m68hc05_device::m68hc05_device(
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}
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void m68hc05_device::set_port_bits(u8 a, u8 b, u8 c, u8 d)
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void m68hc05_device::set_port_bits(std::array<u8, PORT_COUNT> const &bits)
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{
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if (configured() || started())
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throw emu_fatalerror("Attempt to set physical port bits after configuration");
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m_port_bits[0] = a;
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m_port_bits[1] = b;
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m_port_bits[2] = c;
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m_port_bits[3] = d;
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for (unsigned i = 0; PORT_COUNT > i; ++i)
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m_port_bits[i] = bits[i];
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}
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void m68hc05_device::set_port_interrupt(std::array<u8, PORT_COUNT> const &interrupt)
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{
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u8 diff(0x00);
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for (unsigned i = 0; PORT_COUNT > i; ++i)
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{
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diff |= (m_port_interrupt[i] ^ interrupt[i]) & ~m_port_ddr[i];
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m_port_interrupt[i] = interrupt[i];
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if (interrupt[i] && !m_port_cb_r[i].isnull())
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logerror("PORT%c has interrupts enabled with pulled inputs, behaviour may be incorrect\n", 'A' + i);
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}
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if (diff) update_port_irq();
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}
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READ8_MEMBER(m68hc05_device::port_r)
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{
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offset &= PORT_COUNT - 1;
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if (!m_port_cb_r[offset].isnull())
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if (!space.debugger_access() && !m_port_cb_r[offset].isnull())
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{
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u8 const newval(m_port_cb_r[offset](space, 0, ~m_port_ddr[offset] & m_port_bits[offset]) & m_port_bits[offset]);
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if (newval != m_port_input[offset])
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u8 const diff(newval ^ m_port_input[offset]);
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if (diff)
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{
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LOGIOPORT("read PORT%c: new input = %02X & %02X (was %02X)\n",
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char('A' + offset), newval, ~m_port_ddr[offset] & m_port_bits[offset], m_port_input[offset]);
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}
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m_port_input[offset] = newval;
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if (diff & m_port_interrupt[offset] & ~m_port_ddr[offset])
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update_port_irq();
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}
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return port_value(offset);
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}
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@ -189,10 +213,12 @@ WRITE8_MEMBER(m68hc05_device::port_ddr_w)
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{
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offset &= PORT_COUNT - 1;
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data &= m_port_bits[offset];
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if (data != m_port_ddr[offset])
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u8 const diff(data ^ m_port_ddr[offset]);
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if (diff)
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{
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LOGIOPORT("write DDR%c: %02X (was %02X)\n", char('A' + offset), data, m_port_ddr[offset]);
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m_port_ddr[offset] = data;
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if (diff & m_port_interrupt[offset]) update_port_irq();
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m_port_cb_w[offset](space, 0, port_value(offset), m_port_ddr[offset]);
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}
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}
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@ -210,9 +236,9 @@ WRITE8_MEMBER(m68hc05_device::tcr_w)
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BIT(data, 7), BIT(data, 6), BIT(data, 5), BIT(data, 1), BIT(data, 0));
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m_tcr = data;
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if (m_tcr & m_tsr & 0xe0)
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m_pending_interrupts |= u16(1) << M68HC05_TCAP_LINE;
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m_pending_interrupts |= M68HC05_INT_TIMER;
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else
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m_pending_interrupts &= ~(u16(1) << M68HC05_TCAP_LINE);
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m_pending_interrupts &= ~M68HC05_INT_TIMER;
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}
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READ8_MEMBER(m68hc05_device::tsr_r)
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@ -245,7 +271,7 @@ READ8_MEMBER(m68hc05_device::icr_r)
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LOGTIMER("read ICRL, clear ICF\n");
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m_tsr &= 0x7f;
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m_tsr_seen &= 0x7f;
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~(u16(1) << M68HC05_TCAP_LINE);
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~M68HC05_INT_TIMER;
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}
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if (m_inhibit_cap) LOGTIMER("read ICRL, enable capture\n");
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m_inhibit_cap = false;
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@ -269,7 +295,7 @@ READ8_MEMBER(m68hc05_device::ocr_r)
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LOGTIMER("read OCRL, clear OCF\n");
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m_tsr &= 0xbf;
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m_tsr_seen &= 0xbf;
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~(u16(1) << M68HC05_TCAP_LINE);
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~M68HC05_INT_TIMER;
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}
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return u8(m_ocr >> (low ? 0 : 8));
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}
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@ -289,7 +315,7 @@ WRITE8_MEMBER(m68hc05_device::ocr_w)
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LOGTIMER("write OCRL, clear OCF\n");
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m_tsr &= 0xbf;
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m_tsr_seen &= 0xbf;
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~(u16(1) << M68HC05_TCAP_LINE);
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~M68HC05_INT_TIMER;
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}
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if (m_inhibit_cmp) LOGTIMER("write OCRL, enable compare\n");
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m_inhibit_cmp = false;
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@ -323,7 +349,7 @@ READ8_MEMBER(m68hc05_device::timer_r)
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LOGTIMER("read TRL, clear TOF\n");
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m_tsr &= 0xdf;
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m_tsr_seen &= 0xdf;
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~(u16(1) << M68HC05_TCAP_LINE);
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if (!(m_tcr & m_tsr & 0xe0)) m_pending_interrupts &= ~M68HC05_INT_TIMER;
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}
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}
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return m_trl_buf[alt];
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@ -387,9 +413,13 @@ void m68hc05_device::device_start()
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m_tcmp_cb.resolve_safe();
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// save digital I/O
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save_item(NAME(m_port_interrupt));
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save_item(NAME(m_port_input));
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save_item(NAME(m_port_latch));
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save_item(NAME(m_port_ddr));
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save_item(NAME(m_port_irq_state));
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save_item(NAME(m_irq_line_state));
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save_item(NAME(m_irq_latch));
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// save timer/counter
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save_item(NAME(m_tcap_state));
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@ -413,8 +443,10 @@ void m68hc05_device::device_start()
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save_item(NAME(m_ncope));
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// digital I/O state unaffected by reset
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std::fill(std::begin(m_port_interrupt), std::end(m_port_interrupt), 0x00);
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std::fill(std::begin(m_port_input), std::end(m_port_input), 0xff);
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std::fill(std::begin(m_port_latch), std::end(m_port_latch), 0xff);
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m_irq_line_state = false;
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// timer state unaffected by reset
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m_tcap_state = false;
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@ -428,6 +460,9 @@ void m68hc05_device::device_start()
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m_coprst = 0x00;
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m_copcr = 0x00;
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m_ncope = 0;
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// expose most basic state to debugger
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state_add(M68HC05_IRQLATCH, "IRQLATCH", m_irq_latch).mask(0x01);
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}
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void m68hc05_device::device_reset()
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@ -436,6 +471,8 @@ void m68hc05_device::device_reset()
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// digital I/O reset
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std::fill(std::begin(m_port_ddr), std::end(m_port_ddr), 0x00);
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m_irq_latch = 0;
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update_port_irq();
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// timer reset
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m_tcr &= 0x02;
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@ -456,6 +493,18 @@ void m68hc05_device::execute_set_input(int inputnum, int state)
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{
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switch (inputnum)
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{
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case M68HC05_IRQ_LINE:
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if ((CLEAR_LINE != state) && !m_irq_line_state)
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{
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LOGINT("/IRQ edge%s\n", (m_port_irq_state || m_irq_latch) ? "" : ", set IRQ latch");
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if (!m_port_irq_state)
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{
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m_irq_latch = 1;
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m_pending_interrupts |= M68HC05_INT_IRQ;
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}
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}
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m_irq_line_state = ASSERT_LINE == state;
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break;
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case M68HC05_TCAP_LINE:
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if ((bool(state) != m_tcap_state) && (bool(state) == tcr_iedg()))
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{
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@ -464,28 +513,22 @@ void m68hc05_device::execute_set_input(int inputnum, int state)
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{
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m_tsr |= 0x80;
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m_icr = m_counter;
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if (m_tcr & m_tsr & 0xe0) m_pending_interrupts |= u16(1) << M68HC05_TCAP_LINE;
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if (m_tcr & m_tsr & 0xe0) m_pending_interrupts |= M68HC05_INT_TIMER;
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}
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}
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m_tcap_state = bool(state);
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break;
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default:
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if (m_irq_state[inputnum] != state)
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{
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m_irq_state[inputnum] = (state == ASSERT_LINE) ? ASSERT_LINE : CLEAR_LINE;
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if (state != CLEAR_LINE)
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m_pending_interrupts |= u16(1) << inputnum;
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}
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fatalerror("m68hc05[%s]: unknown input line %d", tag(), inputnum);
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}
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}
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uint64_t m68hc05_device::execute_clocks_to_cycles(uint64_t clocks) const
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u64 m68hc05_device::execute_clocks_to_cycles(u64 clocks) const
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{
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return (clocks + 1) / 2;
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}
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uint64_t m68hc05_device::execute_cycles_to_clocks(uint64_t cycles) const
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u64 m68hc05_device::execute_cycles_to_clocks(u64 cycles) const
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{
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return cycles * 2;
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}
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@ -494,9 +537,9 @@ uint64_t m68hc05_device::execute_cycles_to_clocks(uint64_t cycles) const
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offs_t m68hc05_device::disasm_disassemble(
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std::ostream &stream,
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offs_t pc,
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const uint8_t *oprom,
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const uint8_t *opram,
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uint32_t options)
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const u8 *oprom,
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const u8 *opram,
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u32 options)
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{
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return CPU_DISASSEMBLE_NAME(m68hc05)(this, stream, pc, oprom, opram, options);
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}
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@ -504,35 +547,32 @@ offs_t m68hc05_device::disasm_disassemble(
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void m68hc05_device::interrupt()
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{
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if (m_pending_interrupts & M68HC05_INT_MASK)
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if ((m_pending_interrupts & M68HC05_INT_MASK) && !(CC & IFLAG))
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{
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if (!(CC & IFLAG))
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{
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pushword(m_pc);
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pushbyte(m_x);
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pushbyte(m_a);
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pushbyte(m_cc);
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SEI;
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standard_irq_callback(0);
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pushword(m_pc);
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pushbyte(m_x);
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pushbyte(m_a);
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pushbyte(m_cc);
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SEI;
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standard_irq_callback(0);
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/*if (BIT(m_pending_interrupts, M68705_IRQ_LINE))
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{
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LOGINT("servicing /INT interrupt\n");
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m_pending_interrupts &= ~(1 << M68705_IRQ_LINE);
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rm16(M68705_VECTOR_INT, m_pc);
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}
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else*/ if (BIT(m_pending_interrupts, M68HC05_TCAP_LINE))
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{
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LOGINT("servicing timer interrupt\n");
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rm16(M68HC05_VECTOR_TIMER, m_pc);
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}
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else
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{
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throw emu_fatalerror("Unknown pending interrupt");
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}
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m_icount -= 10;
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burn_cycles(10);
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if (m_pending_interrupts & M68HC05_INT_IRQ)
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{
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LOGINT("servicing external interrupt\n");
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m_pending_interrupts &= ~M68HC05_INT_IRQ;
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rm16(M68HC05_VECTOR_IRQ, m_pc);
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}
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else if (m_pending_interrupts & M68HC05_INT_TIMER)
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{
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LOGINT("servicing timer interrupt\n");
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rm16(M68HC05_VECTOR_TIMER, m_pc);
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}
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else
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{
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fatalerror("m68hc05[%s]: unknown pending interrupt(s) %x", tag(), m_pending_interrupts);
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}
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m_icount -= 10;
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burn_cycles(10);
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}
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}
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@ -561,7 +601,7 @@ void m68hc05_device::burn_cycles(unsigned count)
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m_tcmp_cb(tcr_olvl() ? 1 : 0);
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}
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}
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if (m_tcr & m_tsr & 0xe0) m_pending_interrupts |= u16(1) << M68HC05_TCAP_LINE;
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if (m_tcr & m_tsr & 0xe0) m_pending_interrupts |= M68HC05_INT_TIMER;
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// run programmable COP
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u32 const pcop_timeout(u32(1) << ((copcr_cm() << 1) + 15));
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@ -584,6 +624,20 @@ void m68hc05_device::burn_cycles(unsigned count)
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}
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void m68hc05_device::add_port_state(std::array<bool, PORT_COUNT> const &ddr)
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{
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for (unsigned i = 0; PORT_COUNT > i; ++i)
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{
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if (m_port_bits[i])
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state_add(M68HC05_LATCHA + i, util::string_format("LATCH%c", 'A' + i).c_str(), m_port_latch[i]).mask(m_port_bits[i]);
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}
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for (unsigned i = 0; PORT_COUNT > i; ++i)
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{
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if (ddr[i] && m_port_bits[i])
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state_add(M68HC05_DDRA + i, util::string_format("DDR%c", 'A' + i).c_str(), m_port_ddr[i]).mask(m_port_bits[i]);
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}
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}
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void m68hc05_device::add_timer_state()
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{
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state_add(M68HC05_TCR, "TCR", m_tcr).mask(0x7f);
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@ -608,6 +662,31 @@ void m68hc05_device::add_ncop_state()
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}
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u8 m68hc05_device::port_value(unsigned offset) const
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{
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return (m_port_latch[offset] & m_port_ddr[offset]) | (m_port_input[offset] & ~m_port_ddr[offset]);
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}
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void m68hc05_device::update_port_irq()
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{
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u8 state(0x00);
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for (unsigned i = 0; i < PORT_COUNT; ++i)
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state |= m_port_interrupt[i] & ~m_port_ddr[i] & ~m_port_input[i];
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if (bool(state) != m_port_irq_state)
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{
|
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LOGINT("I/O port IRQ state now %u%s\n",
|
||||
state ? 1 : 0, (!m_irq_line_state && state && !m_irq_latch) ? ", set IRQ latch" : "");
|
||||
m_port_irq_state = bool(state);
|
||||
if (!m_irq_line_state && state)
|
||||
{
|
||||
m_irq_latch = 1;
|
||||
m_pending_interrupts |= M68HC05_INT_IRQ;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* M68HC705 base device
|
||||
@ -664,7 +743,7 @@ DEVICE_ADDRESS_MAP_START( c4_map, 8, m68hc05c4_device )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
m68hc05c4_device::m68hc05c4_device(machine_config const &mconfig, char const *tag, device_t *owner, uint32_t clock)
|
||||
m68hc05c4_device::m68hc05c4_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
|
||||
: m68hc05_device(
|
||||
mconfig,
|
||||
tag,
|
||||
@ -676,7 +755,7 @@ m68hc05c4_device::m68hc05c4_device(machine_config const &mconfig, char const *ta
|
||||
"m68hc05c4",
|
||||
__FILE__)
|
||||
{
|
||||
set_port_bits(0xff, 0xff, 0xff, 0xbf);
|
||||
set_port_bits(std::array<u8, PORT_COUNT>{{ 0xff, 0xff, 0xff, 0xbf }});
|
||||
}
|
||||
|
||||
|
||||
@ -685,6 +764,7 @@ void m68hc05c4_device::device_start()
|
||||
{
|
||||
m68hc05_device::device_start();
|
||||
|
||||
add_port_state(std::array<bool, PORT_COUNT>{{ true, true, true, false }});
|
||||
add_timer_state();
|
||||
}
|
||||
|
||||
@ -692,9 +772,9 @@ void m68hc05c4_device::device_start()
|
||||
offs_t m68hc05c4_device::disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options)
|
||||
const u8 *oprom,
|
||||
const u8 *opram,
|
||||
u32 options)
|
||||
{
|
||||
return CPU_DISASSEMBLE_NAME(m68hc05)(this, stream, pc, oprom, opram, options, m68hc05c4_syms);
|
||||
}
|
||||
@ -735,7 +815,7 @@ DEVICE_ADDRESS_MAP_START( c8_map, 8, m68hc05c8_device )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
m68hc05c8_device::m68hc05c8_device(machine_config const &mconfig, char const *tag, device_t *owner, uint32_t clock)
|
||||
m68hc05c8_device::m68hc05c8_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
|
||||
: m68hc05_device(
|
||||
mconfig,
|
||||
tag,
|
||||
@ -747,7 +827,7 @@ m68hc05c8_device::m68hc05c8_device(machine_config const &mconfig, char const *ta
|
||||
"m68hc05c8",
|
||||
__FILE__)
|
||||
{
|
||||
set_port_bits(0xff, 0xff, 0xff, 0xbf);
|
||||
set_port_bits(std::array<u8, PORT_COUNT>{{ 0xff, 0xff, 0xff, 0xbf }});
|
||||
}
|
||||
|
||||
|
||||
@ -755,6 +835,7 @@ void m68hc05c8_device::device_start()
|
||||
{
|
||||
m68hc05_device::device_start();
|
||||
|
||||
add_port_state(std::array<bool, PORT_COUNT>{{ true, true, true, false }});
|
||||
add_timer_state();
|
||||
}
|
||||
|
||||
@ -762,9 +843,9 @@ void m68hc05c8_device::device_start()
|
||||
offs_t m68hc05c8_device::disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options)
|
||||
const u8 *oprom,
|
||||
const u8 *opram,
|
||||
u32 options)
|
||||
{
|
||||
// same I/O registers as MC68HC05C4
|
||||
return CPU_DISASSEMBLE_NAME(m68hc05)(this, stream, pc, oprom, opram, options, m68hc05c4_syms);
|
||||
@ -812,7 +893,7 @@ DEVICE_ADDRESS_MAP_START( c8a_map, 8, m68hc705c8a_device )
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
m68hc705c8a_device::m68hc705c8a_device(machine_config const &mconfig, char const *tag, device_t *owner, uint32_t clock)
|
||||
m68hc705c8a_device::m68hc705c8a_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
|
||||
: m68hc705_device(
|
||||
mconfig,
|
||||
tag,
|
||||
@ -824,7 +905,7 @@ m68hc705c8a_device::m68hc705c8a_device(machine_config const &mconfig, char const
|
||||
"m68hc705c8a",
|
||||
__FILE__)
|
||||
{
|
||||
set_port_bits(0xff, 0xff, 0xff, 0xbf);
|
||||
set_port_bits(std::array<u8, PORT_COUNT>{{ 0xff, 0xff, 0xff, 0xbf }});
|
||||
}
|
||||
|
||||
|
||||
@ -838,6 +919,7 @@ void m68hc705c8a_device::device_start()
|
||||
{
|
||||
m68hc705_device::device_start();
|
||||
|
||||
add_port_state(std::array<bool, PORT_COUNT>{{ true, true, true, false }});
|
||||
add_timer_state();
|
||||
add_pcop_state();
|
||||
add_ncop_state();
|
||||
@ -847,16 +929,18 @@ void m68hc705c8a_device::device_reset()
|
||||
{
|
||||
m68hc705_device::device_reset();
|
||||
|
||||
set_ncope(rdmem(0xfff1));
|
||||
// latch MOR registers on reset
|
||||
set_port_interrupt(std::array<u8, PORT_COUNT>{{ 0x00, u8(rdmem(0xfff0)), 0x00, 0x00 }});
|
||||
set_ncope(BIT(rdmem(0xfff1), 0));
|
||||
}
|
||||
|
||||
|
||||
offs_t m68hc705c8a_device::disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options)
|
||||
const u8 *oprom,
|
||||
const u8 *opram,
|
||||
u32 options)
|
||||
{
|
||||
return CPU_DISASSEMBLE_NAME(m68hc05)(this, stream, pc, oprom, opram, options, m68hc705c8a_syms);
|
||||
}
|
||||
|
||||
@ -7,6 +7,8 @@
|
||||
|
||||
#include "m6805.h"
|
||||
|
||||
#include <array>
|
||||
|
||||
|
||||
//**************************************************************************
|
||||
// GLOBAL VARIABLES
|
||||
@ -73,7 +75,18 @@ protected:
|
||||
M68HC05_CC = M6805_CC,
|
||||
M68HC05_IRQ_STATE = M6805_IRQ_STATE,
|
||||
|
||||
M68HC05_TCR = 0x10,
|
||||
M68HC05_IRQLATCH = 0x10,
|
||||
|
||||
M68HC05_LATCHA,
|
||||
M68HC05_LATCHB,
|
||||
M68HC05_LATCHC,
|
||||
M68HC05_LATCHD,
|
||||
M68HC05_DDRA,
|
||||
M68HC05_DDRB,
|
||||
M68HC05_DDRC,
|
||||
M68HC05_DDRD,
|
||||
|
||||
M68HC05_TCR,
|
||||
M68HC05_TSR,
|
||||
M68HC05_ICR,
|
||||
M68HC05_OCR,
|
||||
@ -100,7 +113,8 @@ protected:
|
||||
char const *shortname,
|
||||
char const *source);
|
||||
|
||||
void set_port_bits(u8 a, u8 b, u8 c, u8 d);
|
||||
void set_port_bits(std::array<u8, PORT_COUNT> const &bits);
|
||||
void set_port_interrupt(std::array<u8, PORT_COUNT> const &interrupt);
|
||||
DECLARE_READ8_MEMBER(port_r);
|
||||
DECLARE_WRITE8_MEMBER(port_latch_w);
|
||||
DECLARE_READ8_MEMBER(port_ddr_r);
|
||||
@ -124,28 +138,27 @@ protected:
|
||||
virtual void device_reset() override;
|
||||
|
||||
virtual void execute_set_input(int inputnum, int state) override;
|
||||
virtual uint64_t execute_clocks_to_cycles(uint64_t clocks) const override;
|
||||
virtual uint64_t execute_cycles_to_clocks(uint64_t cycles) const override;
|
||||
virtual u64 execute_clocks_to_cycles(u64 clocks) const override;
|
||||
virtual u64 execute_cycles_to_clocks(u64 cycles) const override;
|
||||
|
||||
virtual offs_t disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const u8 *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options) override;
|
||||
u32 options) override;
|
||||
|
||||
virtual void interrupt() override;
|
||||
virtual void burn_cycles(unsigned count) override;
|
||||
|
||||
void add_port_state(std::array<bool, PORT_COUNT> const &ddr);
|
||||
void add_timer_state();
|
||||
void add_pcop_state();
|
||||
void add_ncop_state();
|
||||
|
||||
private:
|
||||
u8 port_value(unsigned offset) const
|
||||
{
|
||||
return (m_port_latch[offset] & m_port_ddr[offset]) | (m_port_input[offset] & ~m_port_ddr[offset]);
|
||||
}
|
||||
u8 port_value(unsigned offset) const;
|
||||
void update_port_irq();
|
||||
|
||||
bool tcr_icie() const { return BIT(m_tcr, 7); }
|
||||
bool tcr_ocie() const { return BIT(m_tcr, 6); }
|
||||
@ -166,9 +179,12 @@ private:
|
||||
devcb_read8 m_port_cb_r[PORT_COUNT];
|
||||
devcb_write8 m_port_cb_w[PORT_COUNT];
|
||||
u8 m_port_bits[PORT_COUNT];
|
||||
u8 m_port_interrupt[PORT_COUNT];
|
||||
u8 m_port_input[PORT_COUNT];
|
||||
u8 m_port_latch[PORT_COUNT];
|
||||
u8 m_port_ddr[PORT_COUNT];
|
||||
bool m_port_irq_state, m_irq_line_state;
|
||||
u8 m_irq_latch;
|
||||
|
||||
// timer/counter
|
||||
devcb_write_line m_tcmp_cb;
|
||||
@ -221,9 +237,9 @@ protected:
|
||||
virtual offs_t disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options) override;
|
||||
const u8 *oprom,
|
||||
const u8 *opram,
|
||||
u32 options) override;
|
||||
};
|
||||
|
||||
|
||||
@ -242,9 +258,9 @@ protected:
|
||||
virtual offs_t disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options) override;
|
||||
const u8 *oprom,
|
||||
const u8 *opram,
|
||||
u32 options) override;
|
||||
};
|
||||
|
||||
|
||||
@ -266,9 +282,9 @@ protected:
|
||||
virtual offs_t disasm_disassemble(
|
||||
std::ostream &stream,
|
||||
offs_t pc,
|
||||
const uint8_t *oprom,
|
||||
const uint8_t *opram,
|
||||
uint32_t options) override;
|
||||
const u8 *oprom,
|
||||
const u8 *opram,
|
||||
u32 options) override;
|
||||
};
|
||||
|
||||
|
||||
@ -276,7 +292,6 @@ protected:
|
||||
* 68HC05 section
|
||||
****************************************************************************/
|
||||
|
||||
#define M68HC05_INT_MASK 0x03
|
||||
#define M68HC05_IRQ_LINE (M6805_IRQ_LINE + 0)
|
||||
#define M68HC05_TCAP_LINE (M6805_IRQ_LINE + 1)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user