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https://github.com/holub/mame
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machine/ncr5380.cpp: Add DP8490 type so that its Enhanced Mode can be emulated in the future
This commit is contained in:
AJR
parent
da5ddf83c5
commit
dc2ba0ed83
@ -44,7 +44,7 @@ protected:
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virtual void memc_map(address_map &map) override ATTR_COLD;
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private:
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required_device<ncr5380_device> m_ncr5380;
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required_device<dp8490_device> m_dp8490;
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required_device<eeprom_serial_93cxx_device> m_eeprom;
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required_memory_region m_podule_rom;
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@ -56,10 +56,10 @@ void arc_scsi_cumana_device::ioc_map(address_map &map)
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{
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map(0x0000, 0x1fff).lr8(NAME([this](offs_t offset) { return m_podule_rom->base()[offset | ((m_rom_page << 11) & 0xf800)]; })).umask32(0x000000ff);
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map(0x0000, 0x1fff).lw8(NAME([this](u8 data) { m_rom_page = data; }));
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//map(0x2000, 0x201f).mirror(0x0100).rw(m_ncr5380, FUNC(ncr5380_device::read), FUNC(ncr5380_device::write)).umask32(0x000000ff);
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map(0x2100, 0x211f).m(m_ncr5380, FUNC(ncr5380_device::map)).umask32(0x000000ff);
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//map(0x2100, 0x2100).r(m_ncr5380, FUNC(ncr5380_device::dma_r));
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//map(0x2100, 0x2100).w(m_ncr5380, FUNC(ncr5380_device::dma_w));
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//map(0x2000, 0x201f).mirror(0x0100).rw(m_dp8490, FUNC(dp8490_device::read), FUNC(dp8490_device::write)).umask32(0x000000ff);
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map(0x2100, 0x211f).m(m_dp8490, FUNC(dp8490_device::map)).umask32(0x000000ff);
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//map(0x2100, 0x2100).r(m_dp8490, FUNC(dp8490_device::dma_r));
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//map(0x2100, 0x2100).w(m_dp8490, FUNC(dp8490_device::dma_w));
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}
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void arc_scsi_cumana_device::memc_map(address_map &map)
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@ -96,10 +96,10 @@ void arc_scsi_cumana_device::device_add_mconfig(machine_config &config)
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NSCSI_CONNECTOR(config, "scsi:4", default_scsi_devices, nullptr, false);
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NSCSI_CONNECTOR(config, "scsi:5", default_scsi_devices, nullptr, false);
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NSCSI_CONNECTOR(config, "scsi:6", default_scsi_devices, nullptr, false);
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NSCSI_CONNECTOR(config, "scsi:7").option_set("ncr5380", NCR5380) // DP8490
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NSCSI_CONNECTOR(config, "scsi:7").option_set("dp8490", DP8490) // DP8490N
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.machine_config([this](device_t *device)
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{
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downcast<ncr5380_device &>(*device).irq_handler().set([this](int state) { set_pirq(state); });
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downcast<dp8490_device &>(*device).irq_handler().set([this](int state) { set_pirq(state); });
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});
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EEPROM_93C06_16BIT(config, m_eeprom);
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@ -117,7 +117,7 @@ void arc_scsi_cumana_device::device_add_mconfig(machine_config &config)
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arc_scsi_cumana_device::arc_scsi_cumana_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: device_t(mconfig, ARC_SCSI_CUMANA, tag, owner, clock)
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, device_archimedes_podule_interface(mconfig, *this)
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, m_ncr5380(*this, "scsi:7:ncr5380")
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, m_dp8490(*this, "scsi:7:dp8490")
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, m_eeprom(*this, "eeprom")
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, m_podule_rom(*this, "podule_rom")
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, m_rom_page(0)
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@ -2,14 +2,15 @@
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// copyright-holders:Patrick Mackinlay
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/*
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* NCR 5380 and 53C80, aka Zilog Z5380, AMD Am5380, Sony CXD1180 and others.
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* NCR 5380 and 53C80, aka Zilog Z5380, AMD Am5380, Sony CXD1180, National Semiconductor DP8490, Logic Devices L5380 and others.
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*
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* Sources:
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* - http://bitsavers.org/components/ncr/scsi/SP-1051_NCR_5380-53C80_SCSI_Interface_Chip_Design_Manual_Mar86.pdf
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*
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* TODO:
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* - target mode
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* - cxd1180 enhancements
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* - CXD1180 enhancements
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* - DP8490 enhancements
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*/
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#include "emu.h"
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@ -27,6 +28,7 @@
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DEFINE_DEVICE_TYPE(NCR5380, ncr5380_device, "ncr5380", "NCR 5380 SCSI")
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DEFINE_DEVICE_TYPE(NCR53C80, ncr53c80_device, "ncr53c80", "NCR 53C80 SCSI")
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DEFINE_DEVICE_TYPE(CXD1180, cxd1180_device, "cxd1180", "Sony CXD1180")
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DEFINE_DEVICE_TYPE(DP8490, dp8490_device, "dp8490", "National Semiconductor DP8490 EASI")
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ALLOW_SAVE_TYPE(ncr5380_device::state);
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@ -54,6 +56,11 @@ cxd1180_device::cxd1180_device(machine_config const &mconfig, char const *tag, d
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{
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}
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dp8490_device::dp8490_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: ncr5380_device(mconfig, DP8490, tag, owner, clock, true)
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{
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}
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void ncr5380_device::map(address_map &map)
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{
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map(0x0, 0x0).rw(FUNC(ncr5380_device::csdata_r), FUNC(ncr5380_device::odata_w));
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@ -179,8 +179,15 @@ public:
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cxd1180_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = 0);
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};
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class dp8490_device : public ncr5380_device
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{
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public:
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dp8490_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock = 0);
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};
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DECLARE_DEVICE_TYPE(NCR5380, ncr5380_device)
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DECLARE_DEVICE_TYPE(NCR53C80, ncr53c80_device)
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DECLARE_DEVICE_TYPE(CXD1180, cxd1180_device)
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DECLARE_DEVICE_TYPE(DP8490, dp8490_device)
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#endif // MAME_MACHINE_NCR5380_H
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@ -49,7 +49,7 @@ public:
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, m_fpu(*this, "fpu")
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, m_icu(*this, "icu")
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, m_rtc(*this, "rtc")
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, m_ncr5380(*this, "slot:7:ncr5380")
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, m_dp8490(*this, "slot:7:dp8490")
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, m_aic6250(*this, "scsi:0:aic6250")
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, m_duart(*this, "duart%u", 0U)
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, m_serial(*this, "serial%u", 0U)
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@ -74,7 +74,7 @@ protected:
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required_device<ds1216e_device> m_rtc;
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required_device<ncr5380_device> m_ncr5380;
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required_device<dp8490_device> m_dp8490;
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required_device<aic6250_device> m_aic6250;
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required_device_array<scn2681_device, 4> m_duart;
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@ -154,13 +154,13 @@ void pc532_state::drq_w(int state)
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{
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switch (m_state)
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{
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case RD1: m_dma |= u32(m_ncr5380->dma_r()) << 8; m_state = RD2; break;
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case RD2: m_dma |= u32(m_ncr5380->dma_r()) << 16; m_state = RD3; break;
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case RD3: m_dma |= u32(m_ncr5380->dma_r()) << 24; m_state = RD4; break;
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case RD1: m_dma |= u32(m_dp8490->dma_r()) << 8; m_state = RD2; break;
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case RD2: m_dma |= u32(m_dp8490->dma_r()) << 16; m_state = RD3; break;
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case RD3: m_dma |= u32(m_dp8490->dma_r()) << 24; m_state = RD4; break;
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case WR3: m_ncr5380->dma_w(m_dma >> 8); m_state = WR2; break;
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case WR2: m_ncr5380->dma_w(m_dma >> 16); m_state = WR1; break;
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case WR1: m_ncr5380->dma_w(m_dma >> 24); m_state = IDLE; break;
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case WR3: m_dp8490->dma_w(m_dma >> 8); m_state = WR2; break;
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case WR2: m_dp8490->dma_w(m_dma >> 16); m_state = WR1; break;
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case WR1: m_dp8490->dma_w(m_dma >> 24); m_state = IDLE; break;
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default:
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break;
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@ -212,7 +212,7 @@ u32 pc532_state::dma_r(offs_t offset, u32 mem_mask)
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if (m_drq && !m_irq)
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{
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// buffer empty and SCSI ready to transfer; read SCSI data, enter the read state, and signal the CPU to wait
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m_dma = m_ncr5380->dma_r();
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m_dma = m_dp8490->dma_r();
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m_state = RD1;
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m_cpu->rdy_w(1);
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@ -249,7 +249,7 @@ void pc532_state::dma_w(offs_t offset, u32 data, u32 mem_mask)
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if (m_drq)
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{
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m_dma = data;
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m_ncr5380->dma_w(m_dma >> 0);
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m_dp8490->dma_w(m_dma >> 0);
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m_state = WR3;
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}
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}
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@ -280,7 +280,7 @@ template <unsigned ST> void pc532_state::cpu_map(address_map &map)
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if (ST == ns32000::ST_ODT)
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{
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map(0x3000'0000, 0x3fff'ffff).view(m_select);
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m_select[0](0x3000'0000, 0x3000'0007).m(m_ncr5380, FUNC(ncr5380_device::map));
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m_select[0](0x3000'0000, 0x3000'0007).m(m_dp8490, FUNC(dp8490_device::map));
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m_select[0](0x3800'0000, 0x3fff'ffff).rw(FUNC(pc532_state::dma_r), FUNC(pc532_state::dma_w));
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m_select[1](0x3000'0000, 0x3000'0001).rw(m_aic6250, FUNC(aic6250_device::read), FUNC(aic6250_device::write));
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}
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@ -316,14 +316,14 @@ void pc532_state::pc532(machine_config &config)
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NSCSI_CONNECTOR(config, "slot:1", scsi_devices, nullptr, false);
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NSCSI_CONNECTOR(config, "slot:2", scsi_devices, nullptr, false);
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NSCSI_CONNECTOR(config, "slot:3", scsi_devices, nullptr, false);
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NSCSI_CONNECTOR(config, "slot:7").option_set("ncr5380", NCR5380).machine_config( // DP8490
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NSCSI_CONNECTOR(config, "slot:7").option_set("dp8490", DP8490).machine_config( // DP8490V
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[this](device_t *device)
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{
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ncr5380_device &ncr5380(downcast<ncr5380_device &>(*device));
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dp8490_device &dp8490(downcast<dp8490_device &>(*device));
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ncr5380.drq_handler().set(*this, FUNC(pc532_state::drq_w));
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ncr5380.irq_handler().append(m_icu, FUNC(ns32202_device::ir_w<4>));
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ncr5380.irq_handler().append(*this, FUNC(pc532_state::irq_w));
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dp8490.drq_handler().set(*this, FUNC(pc532_state::drq_w));
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dp8490.irq_handler().append(m_icu, FUNC(ns32202_device::ir_w<4>));
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dp8490.irq_handler().append(*this, FUNC(pc532_state::irq_w));
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});
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NSCSI_BUS(config, "scsi");
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