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machine/74259.cpp : Simplify handlers

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This commit is contained in:
cam900 2019-05-01 15:30:35 +09:00
parent 5501b8c228
commit dc82947cb7
17 changed files with 38 additions and 92 deletions
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16
src/devices/machine/74259.cpp
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@ -232,7 +232,7 @@ void addressable_latch_device::update_bit()
// LSB of data (or CRUOUT on TMS99xx)
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_d0)
void addressable_latch_device::write_d0(offs_t offset, u8 data)
{
if (LOG_MYSTERY_BITS && data != 0x00 && data != 0x01 && data != 0xff)
logerror("Mystery bits written to Q%d:%s%s%s%s%s%s%s\n",
@ -253,7 +253,7 @@ WRITE8_MEMBER(addressable_latch_device::write_d0)
// second-lowest data bit
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_d1)
void addressable_latch_device::write_d1(offs_t offset, u8 data)
{
if (LOG_MYSTERY_BITS && data != 0x00 && data != 0x02 && data != 0xff)
logerror("Mystery bits written to Q%d:%s%s%s%s%s%s%s\n",
@ -274,7 +274,7 @@ WRITE8_MEMBER(addressable_latch_device::write_d1)
// MSB of (8-bit) data
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_d7)
void addressable_latch_device::write_d7(offs_t offset, u8 data)
{
if (LOG_MYSTERY_BITS && data != 0x00 && data != 0x80 && data != 0xff)
logerror("Mystery bits written to Q%d:%s%s%s%s%s%s%s\n",
@ -296,7 +296,7 @@ WRITE8_MEMBER(addressable_latch_device::write_d7)
// ignored)
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_a0)
void addressable_latch_device::write_a0(offs_t offset, u8 data)
{
write_bit(offset >> 1, offset & 1);
}
@ -307,7 +307,7 @@ WRITE8_MEMBER(addressable_latch_device::write_a0)
// fourth lowest as data input
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_a3)
void addressable_latch_device::write_a3(offs_t offset, u8 data)
{
write_bit(offset & 7, (offset & 8) >> 3);
}
@ -318,7 +318,7 @@ WRITE8_MEMBER(addressable_latch_device::write_a3)
// (offset is ignored)
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_nibble_d0)
void addressable_latch_device::write_nibble_d0(u8 data)
{
write_bit((data & 0x0e) >> 1, data & 0x01);
}
@ -329,7 +329,7 @@ WRITE8_MEMBER(addressable_latch_device::write_nibble_d0)
// (offset is ignored)
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::write_nibble_d3)
void addressable_latch_device::write_nibble_d3(u8 data)
{
write_bit(data & 0x07, BIT(data, 3));
}
@ -338,7 +338,7 @@ WRITE8_MEMBER(addressable_latch_device::write_nibble_d3)
// clear - pulse clear line from bus write
//-------------------------------------------------
WRITE8_MEMBER(addressable_latch_device::clear)
void addressable_latch_device::clear(u8 data)
{
clear_outputs(m_enable ? u8(m_data) << m_address : 0);
}

16
src/devices/machine/74259.h
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@ -48,14 +48,14 @@ public:
// data write handlers
void write_bit(offs_t offset, bool d);
void write_abcd(u8 a, bool d);
DECLARE_WRITE8_MEMBER(write_d0);
DECLARE_WRITE8_MEMBER(write_d1);
DECLARE_WRITE8_MEMBER(write_d7);
DECLARE_WRITE8_MEMBER(write_a0);
DECLARE_WRITE8_MEMBER(write_a3);
DECLARE_WRITE8_MEMBER(write_nibble_d0);
DECLARE_WRITE8_MEMBER(write_nibble_d3);
DECLARE_WRITE8_MEMBER(clear);
void write_d0(offs_t offset, u8 data);
void write_d1(offs_t offset, u8 data);
void write_d7(offs_t offset, u8 data);
void write_a0(offs_t offset, u8 data = 0);
void write_a3(offs_t offset, u8 data = 0);
void write_nibble_d0(u8 data);
void write_nibble_d3(u8 data);
void clear(u8 data = 0);
// read handlers (inlined for the sake of optimization)
DECLARE_READ_LINE_MEMBER(q0_r) { return BIT(m_q, 0); }

5
src/mame/drivers/balsente.cpp
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@ -238,10 +238,7 @@ void balsente_state::cpu1_base_map(address_map &map)
map(0x8000, 0x8fff).ram().w(FUNC(balsente_state::paletteram_w)).share("paletteram");
map(0x9000, 0x9007).w(FUNC(balsente_state::adc_select_w));
map(0x9400, 0x9401).r(FUNC(balsente_state::adc_data_r));
map(0x9800, 0x981f).mirror(0x0060).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d7(space, offset >> 2, data, mem_mask);
});
map(0x9800, 0x981f).mirror(0x0060).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d7(offset >> 2, data); });
map(0x9880, 0x989f).w(FUNC(balsente_state::random_reset_w));
map(0x98a0, 0x98bf).w(FUNC(balsente_state::rombank_select_w));
map(0x98c0, 0x98df).w(FUNC(balsente_state::palette_select_w));

5
src/mame/drivers/dynax.cpp
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@ -1243,10 +1243,7 @@ void dynax_state::tenkai_map(address_map &map)
map(0x10050, 0x10050).w(FUNC(dynax_state::tenkai_priority_w)); // layer priority and enable
map(0x10054, 0x10054).w(FUNC(dynax_state::dynax_blit_backpen_w)); // Background Color
map(0x10058, 0x10058).w(FUNC(dynax_state::tenkai_blit_romregion_w)); // Blitter ROM bank
map(0x10060, 0x1007f).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_mainlatch->write_d1(space, offset >> 2, data, mem_mask);
});
map(0x10060, 0x1007f).lw8("mainlatch_w", [this](offs_t offset, u8 data) { m_mainlatch->write_d1(offset >> 2, data); });
map(0x100c0, 0x100c0).w(FUNC(dynax_state::tenkai_ipsel_w));
map(0x100c1, 0x100c1).w(FUNC(dynax_state::tenkai_ip_w));
map(0x100c2, 0x100c3).r(FUNC(dynax_state::tenkai_ip_r));

10
src/mame/drivers/equites.cpp
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@ -650,10 +650,7 @@ void equites_state::equites_map(address_map &map)
map(0x100000, 0x100001).r(FUNC(equites_state::equites_spriteram_kludge_r));
map(0x140000, 0x1407ff).rw(FUNC(equites_state::mcu_ram_r), FUNC(equites_state::mcu_ram_w)).umask16(0x00ff);
map(0x180000, 0x180001).portr("IN1").w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x180000, 0x180000).select(0x03c000).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_mainlatch->write_a3(space, offset >> 14, data, mem_mask);
});
map(0x180000, 0x180000).select(0x03c000).lw8("mainlatch_w", [this](offs_t offset, u8 data) { m_mainlatch->write_a3(offset >> 14); });
map(0x180001, 0x180001).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x1c0000, 0x1c0001).portr("IN0").w(FUNC(equites_state::equites_scrollreg_w));
map(0x380000, 0x380000).w(FUNC(equites_state::equites_bgcolor_w));
@ -676,10 +673,7 @@ void splndrbt_state::splndrbt_map(address_map &map)
map(0x080000, 0x080001).portr("IN0");
map(0x0c0000, 0x0c0001).portr("IN1");
map(0x0c0000, 0x0c0000).select(0x020000).w(FUNC(splndrbt_state::equites_bgcolor_w));
map(0x0c0001, 0x0c0001).select(0x03c000).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_mainlatch->write_a3(space, offset >> 14, data, mem_mask);
});
map(0x0c0001, 0x0c0001).select(0x03c000).lw8("mainlatch_w", [this](offs_t offset, u8 data) { m_mainlatch->write_a3(offset >> 14); });
map(0x100000, 0x100001).w(FUNC(splndrbt_state::splndrbt_bg_scrollx_w));
map(0x140001, 0x140001).w("soundlatch", FUNC(generic_latch_8_device::write));
map(0x1c0000, 0x1c0001).w(FUNC(splndrbt_state::splndrbt_bg_scrolly_w));

2
src/mame/drivers/flyball.cpp
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@ -286,7 +286,7 @@ WRITE8_MEMBER(flyball_state::pitcher_horz_w)
WRITE8_MEMBER(flyball_state::misc_w)
{
// address and data lines passed through inverting buffers
m_outlatch->write_d0(space, ~offset, ~data);
m_outlatch->write_d0(~offset, ~data);
}
WRITE_LINE_MEMBER(flyball_state::lamp_w)

15
src/mame/drivers/gaelco.cpp
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@ -117,10 +117,7 @@ void gaelco_state::bigkarnk_map(address_map &map)
map(0x700004, 0x700005).portr("P1");
map(0x700006, 0x700007).portr("P2");
map(0x700008, 0x700009).portr("SERVICE");
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x70000f, 0x70000f).w(m_soundlatch, FUNC(generic_latch_8_device::write)); /* Triggers a FIRQ on the sound CPU */
map(0xff8000, 0xffffff).ram(); /* Work RAM */
}
@ -166,10 +163,7 @@ void gaelco_state::squash_map(address_map &map)
map(0x700002, 0x700003).portr("DSW1");
map(0x700004, 0x700005).portr("P1");
map(0x700006, 0x700007).portr("P2");
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x70000d, 0x70000d).w(FUNC(gaelco_state::oki_bankswitch_w));
map(0x70000f, 0x70000f).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write)); /* OKI6295 status register */
map(0xff0000, 0xffffff).ram(); /* Work RAM */
@ -188,10 +182,7 @@ void gaelco_state::thoop_map(address_map &map)
map(0x700002, 0x700003).portr("DSW1");
map(0x700004, 0x700005).portr("P1");
map(0x700006, 0x700007).portr("P2");
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x70000d, 0x70000d).w(FUNC(gaelco_state::oki_bankswitch_w));
map(0x70000f, 0x70000f).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write)); /* OKI6295 status register */
map(0xff0000, 0xffffff).ram(); /* Work RAM */

20
src/mame/drivers/gaelco3d.cpp
View File

@ -679,15 +679,9 @@ void gaelco3d_state::main_map(address_map &map)
map(0x510042, 0x510043).r(FUNC(gaelco3d_state::sound_status_r));
map(0x510100, 0x510101).rw(FUNC(gaelco3d_state::eeprom_data_r), FUNC(gaelco3d_state::irq_ack_w));
map(0x510103, 0x510103).r(m_serial, FUNC(gaelco_serial_device::data_r));
map(0x510103, 0x510103).select(0x000038).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_mainlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x510103, 0x510103).select(0x000038).lw8("mainlatch_w", [this](offs_t offset, u8 data) { m_mainlatch->write_d0(offset >> 3, data); });
map(0x510105, 0x510105).w(m_serial, FUNC(gaelco_serial_device::data_w));
map(0x510107, 0x510107).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 4, data, mem_mask);
});
map(0x510107, 0x510107).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 4, data); });
map(0xfe0000, 0xfeffff).ram().share("m68k_ram_base");
map(0xfe7f80, 0xfe7fff).w(FUNC(gaelco3d_state::tms_comm_w)).share("tms_comm_base");
}
@ -705,15 +699,9 @@ void gaelco3d_state::main020_map(address_map &map)
map(0x510042, 0x510043).r(FUNC(gaelco3d_state::sound_status_r));
map(0x510100, 0x510101).rw(FUNC(gaelco3d_state::eeprom_data_r), FUNC(gaelco3d_state::irq_ack_w));
map(0x510103, 0x510103).r(m_serial, FUNC(gaelco_serial_device::data_r));
map(0x510103, 0x510103).select(0x000038).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_mainlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x510103, 0x510103).select(0x000038).lw8("mainlatch_w", [this](offs_t offset, u8 data) { m_mainlatch->write_d0(offset >> 3, data); });
map(0x510105, 0x510105).w(m_serial, FUNC(gaelco_serial_device::data_w));
map(0x510107, 0x510107).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 4, data, mem_mask);
});
map(0x510107, 0x510107).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 4, data); });
map(0xfe0000, 0xfeffff).ram().share("m68k_ram_base");
map(0xfe7f80, 0xfe7fff).w(FUNC(gaelco3d_state::tms_comm_w)).share("tms_comm_base");
}

5
src/mame/drivers/gridlee.cpp
View File

@ -289,10 +289,7 @@ void gridlee_state::cpu1_map(address_map &map)
{
map(0x0000, 0x07ff).ram().share("spriteram");
map(0x0800, 0x7fff).ram().w(FUNC(gridlee_state::gridlee_videoram_w)).share("videoram");
map(0x9000, 0x9000).select(0x0070).lw8("latch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_latch->write_d0(space, offset >> 4, data, mem_mask);
});
map(0x9000, 0x9000).select(0x0070).lw8("latch_w", [this](offs_t offset, u8 data) { m_latch->write_d0(offset >> 4, data); });
map(0x9200, 0x9200).w(FUNC(gridlee_state::gridlee_palette_select_w));
map(0x9380, 0x9380).w("watchdog", FUNC(watchdog_timer_device::reset_w));
map(0x9500, 0x9501).r(FUNC(gridlee_state::analog_port_r));

5
src/mame/drivers/munchmo.cpp
View File

@ -102,10 +102,7 @@ void munchmo_state::mnchmobl_map(address_map &map)
map(0xbaba, 0xbaba).nopw(); /* ? */
map(0xbc00, 0xbc7f).ram().share(m_status_vram);
map(0xbe00, 0xbe00).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0xbe01, 0xbe01).select(0x0070).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask){
m_mainlatch->write_d0(space, offset >> 4, data, mem_mask);
});
map(0xbe01, 0xbe01).select(0x0070).lw8("mainlatch_w", [this](offs_t offset, u8 data){ m_mainlatch->write_d0(offset >> 4, data); });
map(0xbe02, 0xbe02).portr("DSW1");
map(0xbe03, 0xbe03).portr("DSW2");
map(0xbf00, 0xbf00).w(FUNC(munchmo_state::nmi_ack_w)); // CNI 1-8C

10
src/mame/drivers/splash.cpp
View File

@ -81,10 +81,7 @@ void splash_state::splash_map(address_map &map)
map(0x840002, 0x840003).portr("DSW2");
map(0x840004, 0x840005).portr("P1");
map(0x840006, 0x840007).portr("P2");
map(0x84000a, 0x84000a).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x84000a, 0x84000a).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x84000f, 0x84000f).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x880000, 0x8817ff).ram().w(FUNC(splash_state::vram_w)).share("videoram"); /* Video RAM */
map(0x881800, 0x881803).ram().share("vregs"); /* Scroll registers */
@ -164,10 +161,7 @@ void splash_state::roldfrog_map(address_map &map)
map(0x840002, 0x840003).portr("DSW2");
map(0x840004, 0x840005).portr("P1");
map(0x840006, 0x840007).portr("P2");
map(0x84000a, 0x84000a).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x84000a, 0x84000a).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x84000f, 0x84000f).w(m_soundlatch, FUNC(generic_latch_8_device::write));
map(0x880000, 0x8817ff).ram().w(FUNC(splash_state::vram_w)).share("videoram"); /* Video RAM */
map(0x881800, 0x881803).ram().share("vregs"); /* Scroll registers */

5
src/mame/drivers/thoop2.cpp
View File

@ -135,10 +135,7 @@ void thoop2_state::thoop2_map(address_map &map)
map(0x700004, 0x700005).portr("P1");
map(0x700006, 0x700007).portr("P2");
map(0x700008, 0x700009).portr("SYSTEM");
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x70000d, 0x70000d).w(FUNC(thoop2_state::oki_bankswitch_w)); /* OKI6295 bankswitch */
map(0x70000f, 0x70000f).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write)); /* OKI6295 data register */
map(0xfe0000, 0xfe7fff).ram(); /* Work RAM */

5
src/mame/drivers/timeplt.cpp
View File

@ -141,10 +141,7 @@ void timeplt_state::timeplt_main_map(address_map &map)
map(0xc000, 0xc000).mirror(0x0cff).r(FUNC(timeplt_state::scanline_r)).w("timeplt_audio", FUNC(timeplt_audio_device::sound_data_w));
map(0xc200, 0xc200).mirror(0x0cff).portr("DSW1").w("watchdog", FUNC(watchdog_timer_device::reset_w));
map(0xc300, 0xc300).mirror(0x0c9f).portr("IN0");
map(0xc300, 0xc30f).lw8("mainlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_mainlatch->write_d0(space, offset >> 1, data, mem_mask);
});
map(0xc300, 0xc30f).lw8("mainlatch_w", [this](offs_t offset, u8 data) { m_mainlatch->write_d0(offset >> 1, data); });
map(0xc320, 0xc320).mirror(0x0c9f).portr("IN1");
map(0xc340, 0xc340).mirror(0x0c9f).portr("IN2");
map(0xc360, 0xc360).mirror(0x0c9f).portr("DSW0");

2
src/mame/drivers/triplhnt.cpp
View File

@ -71,7 +71,7 @@ READ8_MEMBER(triplhnt_state::input_port_4_r)
READ8_MEMBER(triplhnt_state::misc_r)
{
m_latch->write_a0(space, offset, 0);
m_latch->write_a0(offset);
return ioport("VBLANK")->read() | m_hit_code;
}

5
src/mame/drivers/wrally.cpp
View File

@ -156,10 +156,7 @@ void wrally_state::wrally_map(address_map &map)
map(0x700002, 0x700003).portr("P1_P2");
map(0x700004, 0x700005).portr("WHEEL");
map(0x700008, 0x700009).portr("SYSTEM");
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w",
[this](address_space &space, offs_t offset, u8 data, u8 mem_mask) {
m_outlatch->write_d0(space, offset >> 3, data, mem_mask);
});
map(0x70000b, 0x70000b).select(0x000070).lw8("outlatch_w", [this](offs_t offset, u8 data) { m_outlatch->write_d0(offset >> 3, data); });
map(0x70000d, 0x70000d).w(FUNC(wrally_state::okim6295_bankswitch_w)); /* OKI6295 bankswitch */
map(0x70000f, 0x70000f).rw("oki", FUNC(okim6295_device::read), FUNC(okim6295_device::write)); /* OKI6295 status/data register */
map(0xfec000, 0xfeffff).ram().share("shareram"); /* Work RAM (shared with DS5002FP) */

2
src/mame/machine/bbc.cpp
View File

@ -699,7 +699,7 @@ READ8_MEMBER(bbc_state::via_system_portb_r)
WRITE8_MEMBER(bbc_state::via_system_portb_w)
{
m_latch->write_nibble_d3(space, 0, data);
m_latch->write_nibble_d3(data);
/* Master only */
if (m_rtc)

2
src/mame/video/skydiver.cpp
View File

@ -145,7 +145,7 @@ WRITE_LINE_MEMBER(skydiver_state::lamp_r_w)
WRITE8_MEMBER(skydiver_state::latch3_watchdog_w)
{
m_watchdog->watchdog_reset();
m_latch3->write_a0(space, offset, 0);
m_latch3->write_a0(offset);
}