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https://github.com/holub/mame
synced 2025-07-01 16:19:38 +03:00
swtpc09: Memory banking modernization (nw)
This commit is contained in:
AJR
parent
0a22db8f2b
commit
dcba5a1edc
@ -60,11 +60,97 @@
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/* Address map is dynamically setup when DAT memory is written to */
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/* only ROM from FF00-FFFF and DAT memory at FFF0-FFFF (write only) is guaranteed always*/
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static ADDRESS_MAP_START(swtpc09_mem, AS_PROGRAM, 8, swtpc09_state)
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static ADDRESS_MAP_START(mp09_mem, AS_PROGRAM, 8, swtpc09_state)
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AM_RANGE(0x0000, 0x0fff) AM_DEVICE("bank0", address_map_bank_device, amap8)
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AM_RANGE(0x1000, 0x1fff) AM_DEVICE("bank1", address_map_bank_device, amap8)
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AM_RANGE(0x2000, 0x2fff) AM_DEVICE("bank2", address_map_bank_device, amap8)
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AM_RANGE(0x3000, 0x3fff) AM_DEVICE("bank3", address_map_bank_device, amap8)
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AM_RANGE(0x4000, 0x4fff) AM_DEVICE("bank4", address_map_bank_device, amap8)
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AM_RANGE(0x5000, 0x5fff) AM_DEVICE("bank5", address_map_bank_device, amap8)
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AM_RANGE(0x6000, 0x6fff) AM_DEVICE("bank6", address_map_bank_device, amap8)
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AM_RANGE(0x7000, 0x7fff) AM_DEVICE("bank7", address_map_bank_device, amap8)
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AM_RANGE(0x8000, 0x8fff) AM_DEVICE("bank8", address_map_bank_device, amap8)
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AM_RANGE(0x9000, 0x9fff) AM_DEVICE("bank9", address_map_bank_device, amap8)
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AM_RANGE(0xa000, 0xafff) AM_DEVICE("banka", address_map_bank_device, amap8)
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AM_RANGE(0xb000, 0xbfff) AM_DEVICE("bankb", address_map_bank_device, amap8)
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AM_RANGE(0xc000, 0xcfff) AM_DEVICE("bankc", address_map_bank_device, amap8)
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AM_RANGE(0xd000, 0xdfff) AM_DEVICE("bankd", address_map_bank_device, amap8)
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AM_RANGE(0xe000, 0xefff) AM_DEVICE("banke", address_map_bank_device, amap8)
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AM_RANGE(0xf000, 0xfeff) AM_DEVICE("bankf", address_map_bank_device, amap8)
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AM_RANGE(0xff00, 0xffef) AM_ROM
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AM_RANGE(0xfff0, 0xffff) AM_ROM AM_WRITE(dat_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(flex_dmf2_mem, AS_PROGRAM, 8, swtpc09_state)
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AM_RANGE(0xe000, 0xe003) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe004, 0xe004) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, status_r, control_w)
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AM_RANGE(0xe005, 0xe005) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, data_r, data_w)
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AM_RANGE(0xe080, 0xe083) AM_MIRROR(0xf000c) AM_DEVREADWRITE("pia", pia6821_device, read, write)
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AM_RANGE(0xe090, 0xe097) AM_MIRROR(0xf0008) AM_DEVREADWRITE("ptm", ptm6840_device, read, write)
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AM_RANGE(0xe0a0, 0xefff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf000, 0xf01f) AM_MIRROR(0xf0000) AM_READWRITE(m6844_r, m6844_w)
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AM_RANGE(0xf020, 0xf023) AM_MIRROR(0xf0000) AM_DEVREADWRITE("fdc", fd1793_device, read, write)
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AM_RANGE(0xf024, 0xf03f) AM_MIRROR(0xf0000) AM_READWRITE(dmf2_control_reg_r, dmf2_control_reg_w)
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//AM_RANGE(0xf042, 0xf7ff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf800, 0xffff) AM_MIRROR(0xf0000) AM_ROM AM_REGION("maincpu", 0xf800)
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AM_RANGE(0x00000, 0xfffff) AM_RAM AM_SHARE("mainram") // all the rest is treated as ram, 1MB ram emulated
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(flex_dc4_piaide_mem, AS_PROGRAM, 8, swtpc09_state)
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AM_RANGE(0xe000, 0xe003) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe004, 0xe004) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, status_r, control_w)
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AM_RANGE(0xe005, 0xe005) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, data_r, data_w)
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AM_RANGE(0xe014, 0xe014) AM_MIRROR(0xf0000) AM_WRITE(dc4_control_reg_w)
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AM_RANGE(0xe018, 0xe01b) AM_MIRROR(0xf0000) AM_DEVREADWRITE("fdc", fd1793_device, read, write)
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//AM_RANGE(0xe01c, 0xe05f) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe060, 0xe063) AM_MIRROR(0xf000c) AM_DEVREADWRITE("piaide", pia6821_device, read, write)
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//AM_RANGE(0xe070, 0xe07f) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe080, 0xe083) AM_MIRROR(0xf000c) AM_DEVREADWRITE("pia", pia6821_device, read, write)
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AM_RANGE(0xe090, 0xe097) AM_MIRROR(0xf0008) AM_DEVREADWRITE("ptm", ptm6840_device, read, write)
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//AM_RANGE(0xe0a0, 0xe7ff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe800, 0xefff) AM_MIRROR(0xf0000) AM_ROM AM_REGION("maincpu", 0xe800) //piaide rom
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//AM_RANGE(0xf000, 0xf01f) AM_MIRROR(0xf0000) AM_READWRITE(m6844_r, m6844_w)
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//AM_RANGE(0xf020, 0xf023) AM_MIRROR(0xf0000) AM_DEVREADWRITE("fdc", fd1793_device, read, write)
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//AM_RANGE(0xf024, 0xf03f) AM_MIRROR(0xf0000) AM_READWRITE(dmf2_control_reg_r, dmf2_control_reg_w)
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//AM_RANGE(0xf040, 0xf041) AM_MIRROR(0xf0000) AM_READWRITE(dmf2_dma_address_reg_r, dmf2_dma_address_reg_w)
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AM_RANGE(0xf000, 0xf7ff) AM_MIRROR(0xf0000) AM_RAM AM_SHARE("s09ram") // 2k ram for piaide on s09 board
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AM_RANGE(0xf800, 0xffff) AM_MIRROR(0xf0000) AM_ROM AM_REGION("maincpu", 0xf800)
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AM_RANGE(0x00000, 0xfffff) AM_RAM AM_SHARE("mainram") // all the rest is treated as ram, 1MB ram emulated
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(uniflex_dmf2_mem, AS_PROGRAM, 8, swtpc09_state)
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AM_RANGE(0xe000, 0xe000) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, status_r, control_w)
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AM_RANGE(0xe001, 0xe001) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, data_r, data_w)
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AM_RANGE(0xe002, 0xe07f) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe080, 0xe083) AM_MIRROR(0xf000c) AM_DEVREADWRITE("pia", pia6821_device, read, write)
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AM_RANGE(0xe090, 0xe097) AM_MIRROR(0xf0008) AM_DEVREADWRITE("ptm", ptm6840_device, read, write)
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AM_RANGE(0xe0a0, 0xefff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf000, 0xf01f) AM_MIRROR(0xf0000) AM_READWRITE(m6844_r, m6844_w)
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AM_RANGE(0xf020, 0xf023) AM_MIRROR(0xf0000) AM_DEVREADWRITE("fdc", fd1793_device, read, write)
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AM_RANGE(0xf024, 0xf03f) AM_MIRROR(0xf0000) AM_READWRITE(dmf2_control_reg_r, dmf2_control_reg_w)
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//AM_RANGE(0xf042, 0xf7ff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf800, 0xffff) AM_MIRROR(0xf0000) AM_ROM AM_REGION("maincpu", 0xf800)
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AM_RANGE(0x00000, 0xfffff) AM_RAM AM_SHARE("mainram") // all the rest is treated as ram, 1MB ram emulated
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(uniflex_dmf3_mem, AS_PROGRAM, 8, swtpc09_state)
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AM_RANGE(0xe000, 0xe000) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, status_r, control_w)
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AM_RANGE(0xe001, 0xe001) AM_MIRROR(0xf0000) AM_DEVREADWRITE("acia", acia6850_device, data_r, data_w)
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AM_RANGE(0xe002, 0xe07f) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xe080, 0xe083) AM_MIRROR(0xf000c) AM_DEVREADWRITE("pia", pia6821_device, read, write)
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AM_RANGE(0xe090, 0xe097) AM_MIRROR(0xf0008) AM_DEVREADWRITE("ptm", ptm6840_device, read, write)
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AM_RANGE(0xe0a0, 0xefff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf000, 0xf01f) AM_MIRROR(0xf0000) AM_READWRITE(m6844_r, m6844_w)
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AM_RANGE(0xf020, 0xf023) AM_MIRROR(0xf0000) AM_DEVREADWRITE("fdc", fd1793_device, read, write)
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AM_RANGE(0xf024, 0xf024) AM_MIRROR(0xf0000) AM_READWRITE(dmf3_control_reg_r, dmf3_control_reg_w)
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AM_RANGE(0xf025, 0xf025) AM_MIRROR(0xf0000) AM_READWRITE(dmf3_dma_address_reg_r, dmf3_dma_address_reg_w)
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//AM_RANGE(0xf030, 0xf03f) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf040, 0xf04f) AM_MIRROR(0xf0000) AM_DEVREADWRITE("via", via6522_device, read, write)
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//AM_RANGE(0xf050, 0xf7ff) AM_MIRROR(0xf0000) AM_NOP
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AM_RANGE(0xf800, 0xffff) AM_MIRROR(0xf0000) AM_ROM AM_REGION("maincpu", 0xf800)
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AM_RANGE(0x00000, 0xfffff) AM_RAM AM_SHARE("mainram") // all the rest is treated as ram, 1MB ram emulated
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ADDRESS_MAP_END
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/* Input ports */
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static INPUT_PORTS_START( swtpc09 )
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@ -92,15 +178,112 @@ SLOT_INTERFACE_END
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/* Machine driver */
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/* MPU09, MPID, MPS2 DMF2 */
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static MACHINE_CONFIG_START( swtpc09 )
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static MACHINE_CONFIG_START( swtpc09_base )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", M6809, 1000000)
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MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
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MCFG_CPU_PROGRAM_MAP(mp09_mem)
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/* video hardware */
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MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
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MCFG_DEVICE_ADD("bank0", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank1", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank2", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank3", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank4", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank5", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank6", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank7", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank8", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bank9", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("banka", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bankb", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bankc", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bankd", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("banke", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("bankf", ADDRESS_MAP_BANK, 0)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_BIG)
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MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
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MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(20)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x01000)
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MCFG_DEVICE_PROGRAM_MAP(flex_dmf2_mem)
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MCFG_DEVICE_ADD("pia", PIA6821, 0)
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MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
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MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
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MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
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MCFG_DEVICE_ADD("ptm", PTM6840, 2000000)
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MCFG_PTM6840_EXTERNAL_CLOCKS(50, 0, 50)
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@ -108,10 +291,9 @@ static MACHINE_CONFIG_START( swtpc09 )
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MCFG_PTM6840_OUT2_CB(WRITELINE(swtpc09_state, ptm_o3_callback))
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MCFG_PTM6840_IRQ_CB(WRITELINE(swtpc09_state, ptm_irq))
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MCFG_DEVICE_ADD("pia", PIA6821, 0)
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MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
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MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
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MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
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MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
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MCFG_DEVICE_ADD("acia", ACIA6850, 0)
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MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
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@ -123,52 +305,52 @@ static MACHINE_CONFIG_START( swtpc09 )
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MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("acia", acia6850_device, write_rxc))
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MCFG_FD1793_ADD("fdc", XTAL_1MHz)
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MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(swtpc09_state, fdc_intrq_w))
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MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(swtpc09_state, fdc_drq_w))
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MCFG_FLOPPY_DRIVE_ADD("fdc:0", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
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MCFG_FLOPPY_DRIVE_ADD("fdc:1", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
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MCFG_FLOPPY_DRIVE_ADD("fdc:2", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:3", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( swtpc09, swtpc09_base )
|
||||
MCFG_DEVICE_MODIFY("fdc")
|
||||
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(swtpc09_state, fdc_intrq_w))
|
||||
MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(swtpc09_state, fdc_drq_w))
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* MPU09, MPID, MPS2 DC4 PIAIDE*/
|
||||
static MACHINE_CONFIG_START( swtpc09i )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M6809, 1000000)
|
||||
MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
|
||||
|
||||
MCFG_DEVICE_ADD("ptm", PTM6840, 2000000)
|
||||
MCFG_PTM6840_EXTERNAL_CLOCKS(50, 0, 50)
|
||||
MCFG_PTM6840_OUT0_CB(WRITELINE(swtpc09_state, ptm_o1_callback))
|
||||
MCFG_PTM6840_OUT2_CB(WRITELINE(swtpc09_state, ptm_o3_callback))
|
||||
MCFG_PTM6840_IRQ_CB(WRITELINE(swtpc09_state, ptm_irq))
|
||||
|
||||
MCFG_DEVICE_ADD("pia", PIA6821, 0)
|
||||
MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
|
||||
MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
|
||||
MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
|
||||
|
||||
MCFG_DEVICE_ADD("acia", ACIA6850, 0)
|
||||
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
|
||||
MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
|
||||
MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
|
||||
|
||||
MCFG_DEVICE_ADD("brg", MC14411, XTAL_1_8432MHz)
|
||||
MCFG_MC14411_F1_CB(DEVWRITELINE("acia", acia6850_device, write_txc))
|
||||
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("acia", acia6850_device, write_rxc))
|
||||
|
||||
MCFG_FD1793_ADD("fdc", XTAL_1MHz)
|
||||
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:0", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:1", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:2", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:3", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
static MACHINE_CONFIG_DERIVED( swtpc09i, swtpc09_base )
|
||||
MCFG_DEVICE_MODIFY("bank0")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank1")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank2")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank3")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank4")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank5")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank6")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank7")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank8")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bank9")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("banka")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bankb")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bankc")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bankd")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("banke")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
MCFG_DEVICE_MODIFY("bankf")
|
||||
MCFG_DEVICE_PROGRAM_MAP(flex_dc4_piaide_mem)
|
||||
|
||||
MCFG_DEVICE_ADD("piaide", PIA6821, 0)
|
||||
|
||||
@ -181,45 +363,87 @@ static MACHINE_CONFIG_START( swtpc09i )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( swtpc09u, swtpc09 )
|
||||
MCFG_DEVICE_MODIFY("bank0")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank1")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank2")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank3")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank4")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank5")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank6")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank7")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank8")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bank9")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("banka")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bankb")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bankc")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bankd")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("banke")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MCFG_DEVICE_MODIFY("bankf")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf2_mem)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
/* MPU09, MPID, MPS2 DMF3 */
|
||||
static MACHINE_CONFIG_START( swtpc09d3 )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M6809, 2000000)
|
||||
MCFG_CPU_PROGRAM_MAP(swtpc09_mem)
|
||||
static MACHINE_CONFIG_DERIVED( swtpc09d3, swtpc09_base )
|
||||
MCFG_CPU_MODIFY("maincpu")
|
||||
MCFG_CPU_CLOCK(2000000)
|
||||
|
||||
MCFG_DEVICE_MODIFY("pia")
|
||||
MCFG_DEVICE_CLOCK(2000000)
|
||||
|
||||
MCFG_DEVICE_MODIFY("bank0")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank1")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank2")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank3")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank4")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank5")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank6")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank7")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank8")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bank9")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("banka")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bankb")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bankc")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bankd")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("banke")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
MCFG_DEVICE_MODIFY("bankf")
|
||||
MCFG_DEVICE_PROGRAM_MAP(uniflex_dmf3_mem)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_RS232_PORT_ADD("rs232", default_rs232_devices, "terminal")
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("acia", acia6850_device, write_rxd))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("acia", acia6850_device, write_cts))
|
||||
|
||||
MCFG_DEVICE_ADD("ptm", PTM6840, 2000000)
|
||||
MCFG_PTM6840_EXTERNAL_CLOCKS(50, 0, 50)
|
||||
MCFG_PTM6840_OUT0_CB(WRITELINE(swtpc09_state, ptm_o1_callback))
|
||||
MCFG_PTM6840_OUT2_CB(WRITELINE(swtpc09_state, ptm_o3_callback))
|
||||
MCFG_PTM6840_IRQ_CB(WRITELINE(swtpc09_state, ptm_irq))
|
||||
|
||||
MCFG_DEVICE_ADD("pia", PIA6821, 0)
|
||||
MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_a_r))
|
||||
MCFG_PIA_READPA_HANDLER(READ8(swtpc09_state, pia0_ca1_r))
|
||||
MCFG_PIA_IRQA_HANDLER(WRITELINE(swtpc09_state, pia0_irq_a))
|
||||
|
||||
MCFG_DEVICE_ADD("acia", ACIA6850, 0)
|
||||
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_txd))
|
||||
MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232", rs232_port_device, write_rts))
|
||||
MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(swtpc09_state, acia_interrupt))
|
||||
MCFG_DEVICE_MODIFY("acia")
|
||||
MCFG_ACIA6850_IRQ_HANDLER(INPUTLINE("maincpu", M6809_IRQ_LINE))
|
||||
|
||||
MCFG_DEVICE_ADD("brg", MC14411, XTAL_1_8432MHz)
|
||||
MCFG_MC14411_F1_CB(DEVWRITELINE("acia", acia6850_device, write_txc))
|
||||
MCFG_DEVCB_CHAIN_OUTPUT(DEVWRITELINE("acia", acia6850_device, write_rxc))
|
||||
|
||||
MCFG_FD1793_ADD("fdc", XTAL_1MHz)
|
||||
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:0", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:1", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:2", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
MCFG_FLOPPY_DRIVE_ADD("fdc:3", swtpc09_floppies, "dd", swtpc09_state::floppy_formats)
|
||||
|
||||
MCFG_DEVICE_ADD("via", VIA6522, XTAL_4MHz / 4)
|
||||
MCFG_VIA6522_READPA_HANDLER(READ8(swtpc09_state, dmf3_via_read_porta))
|
||||
MCFG_VIA6522_READPB_HANDLER(READ8(swtpc09_state, dmf3_via_read_portb))
|
||||
@ -256,5 +480,5 @@ ROM_END
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT STATE INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1980, swtpc09, 0, 0, swtpc09, swtpc09, swtpc09_state, swtpc09, "SWTPC", "swtpc S/09 Sbug", MACHINE_NO_SOUND_HW )
|
||||
COMP( 1980, swtpc09i, swtpc09, 0, swtpc09i, swtpc09, swtpc09_state, swtpc09i, "SWTPC", "swtpc S/09 Sbug + piaide", MACHINE_NOT_WORKING | MACHINE_NO_SOUND_HW )
|
||||
COMP( 1980, swtpc09u, swtpc09, 0, swtpc09, swtpc09, swtpc09_state, swtpc09u, "SWTPC", "swtpc S/09 UNIBug + DMF2", MACHINE_NO_SOUND_HW )
|
||||
COMP( 1980, swtpc09u, swtpc09, 0, swtpc09u, swtpc09, swtpc09_state, swtpc09u, "SWTPC", "swtpc S/09 UNIBug + DMF2", MACHINE_NO_SOUND_HW )
|
||||
COMP( 1980, swtpc09d3, swtpc09, 0, swtpc09d3, swtpc09, swtpc09_state, swtpc09d3, "SWTPC", "swtpc S/09 UNIBug + DMF3", MACHINE_NO_SOUND_HW )
|
||||
|
||||
@ -22,6 +22,7 @@
|
||||
#include "machine/terminal.h"
|
||||
#include "imagedev/harddriv.h"
|
||||
#include "machine/idectrl.h"
|
||||
#include "machine/bankdev.h"
|
||||
#include "machine/mc14411.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
|
||||
@ -33,6 +34,7 @@ public:
|
||||
swtpc09_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_bank(*this, "bank%x", 0)
|
||||
, m_brg(*this, "brg")
|
||||
, m_pia(*this, "pia")
|
||||
, m_ptm(*this, "ptm")
|
||||
@ -102,6 +104,7 @@ protected:
|
||||
void swtpc09_irq_handler(uint8_t peripheral, uint8_t state);
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device_array<address_map_bank_device, 16> m_bank;
|
||||
required_device<mc14411_device> m_brg;
|
||||
required_device<pia6821_device> m_pia;
|
||||
required_device<ptm6840_device> m_ptm;
|
||||
|
||||
@ -150,9 +150,8 @@ WRITE8_MEMBER ( swtpc09_state::dmf2_control_reg_w )
|
||||
/* FDC controller dma transfer */
|
||||
void swtpc09_state::swtpc09_fdc_dma_transfer()
|
||||
{
|
||||
uint8_t *RAM = memregion("maincpu")->base();
|
||||
uint32_t offset;
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
address_space &space = m_bank[0]->space(AS_PROGRAM);
|
||||
|
||||
offset = (m_fdc_dma_address_reg & 0x0f)<<16;
|
||||
|
||||
@ -163,11 +162,11 @@ void swtpc09_state::swtpc09_fdc_dma_transfer()
|
||||
uint8_t data = m_fdc->data_r(space, 0);
|
||||
|
||||
LOG(("swtpc09_dma_write_mem %05X %02X\n", m_m6844_channel[0].address + offset, data));
|
||||
RAM[m_m6844_channel[0].address + offset] = data;
|
||||
space.write_byte(m_m6844_channel[0].address + offset, data);
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t data = RAM[m_m6844_channel[0].address + offset];
|
||||
uint8_t data = space.read_byte(m_m6844_channel[0].address + offset);
|
||||
|
||||
m_fdc->data_w(space, 0, data);
|
||||
//LOG(("swtpc09_dma_read_mem %04X %02X\n", m_m6844_channel[0].address, data));
|
||||
@ -456,125 +455,15 @@ WRITE8_MEMBER( swtpc09_state::piaide_b_w )
|
||||
WRITE8_MEMBER(swtpc09_state::dat_w)
|
||||
{
|
||||
uint8_t a16_to_a19, a12_to_a15;
|
||||
uint8_t *RAM = memregion("maincpu")->base();
|
||||
uint32_t physical_address, logical_address;
|
||||
|
||||
address_space &mem = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
fd1793_device *fdc = machine().device<fd1793_device>("fdc");
|
||||
pia6821_device *pia = machine().device<pia6821_device>("pia");
|
||||
ptm6840_device *ptm = machine().device<ptm6840_device>("ptm");
|
||||
acia6850_device *acia = machine().device<acia6850_device>("acia");
|
||||
via6522_device *via = machine().device<via6522_device>("via");
|
||||
pia6821_device *piaide = machine().device<pia6821_device>("piaide");
|
||||
|
||||
a16_to_a19 = data & 0xf0;
|
||||
a12_to_a15 = ~data & 0x0f; //lower 4 bits are inverted
|
||||
physical_address = ((a16_to_a19 + a12_to_a15) << 12);
|
||||
logical_address = offset << 12;
|
||||
LOG(("swtpc09_dat_bank_unmap Logical address:%04X\n", offset << 12 ));
|
||||
LOG(("swtpc09_dat_bank_set dat:%02X Logical address:%04X Physical address:%05X\n", data, offset << 12, physical_address ));
|
||||
|
||||
|
||||
// unmap page to be changed
|
||||
mem.unmap_readwrite(offset << 12, (offset << 12)+0x0fff);
|
||||
|
||||
// map in new page
|
||||
if (a12_to_a15 == 0x0e) // 0xE000 address range to be mapped in at this page
|
||||
{
|
||||
if (m_system_type == FLEX_DMF2) // if flex/sbug, map in acia at 0xE004
|
||||
{
|
||||
mem.nop_readwrite(logical_address+0x000, logical_address+0x003);
|
||||
mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
|
||||
mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
|
||||
mem.nop_readwrite(logical_address+0x006, logical_address+0x07f);
|
||||
mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
|
||||
mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
|
||||
mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
|
||||
}
|
||||
else if (m_system_type == FLEX_DC4_PIAIDE) // if flex/sbug and dc4 and piaide
|
||||
{
|
||||
mem.nop_readwrite(logical_address+0x000, logical_address+0x003);
|
||||
mem.install_readwrite_handler(logical_address+0x004, logical_address+0x004, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w),acia));
|
||||
mem.install_readwrite_handler(logical_address+0x005, logical_address+0x005, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w),acia));
|
||||
mem.install_write_handler(logical_address+0x014, logical_address+0x014, write8_delegate(FUNC(swtpc09_state::dc4_control_reg_w),this));
|
||||
mem.install_readwrite_handler(logical_address+0x018, logical_address+0x01b, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
|
||||
//mem.nop_readwrite(logical_address+0x01c, logical_address+0x05f);
|
||||
mem.install_readwrite_handler(logical_address+0x060, logical_address+0x06f, read8_delegate(FUNC(pia6821_device::read), piaide), write8_delegate(FUNC(pia6821_device::write), piaide));
|
||||
//mem.nop_readwrite(logical_address+0x070, logical_address+0x07f);
|
||||
mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
|
||||
mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
|
||||
//mem.nop_readwrite(logical_address+0x0a0, logical_address+0x7ff);
|
||||
mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xe800]); //piaide rom
|
||||
}
|
||||
else // assume unibug, map in acia at 0xE000
|
||||
{
|
||||
mem.install_readwrite_handler(logical_address+0x000, logical_address+0x000, read8_delegate(FUNC(acia6850_device::status_r), acia), write8_delegate(FUNC(acia6850_device::control_w), acia));
|
||||
mem.install_readwrite_handler(logical_address+0x001, logical_address+0x001, read8_delegate(FUNC(acia6850_device::data_r), acia), write8_delegate(FUNC(acia6850_device::data_w), acia));
|
||||
mem.nop_readwrite(logical_address+0x002, logical_address+0x07f);
|
||||
mem.install_readwrite_handler(logical_address+0x080, logical_address+0x08f, read8_delegate(FUNC(pia6821_device::read), pia), write8_delegate(FUNC(pia6821_device::write), pia));
|
||||
mem.install_readwrite_handler(logical_address+0x090, logical_address+0x09f, read8_delegate(FUNC(ptm6840_device::read), ptm), write8_delegate(FUNC(ptm6840_device::write), ptm));
|
||||
mem.nop_readwrite(logical_address+0x0a0, logical_address+0xfff);
|
||||
}
|
||||
}
|
||||
else if (a12_to_a15 == 0x0f) // 0xF000 address range to be mapped in at this page
|
||||
{
|
||||
if (m_system_type == UNIFLEX_DMF2 || m_system_type == FLEX_DMF2) // if DMF2 conroller this is the map
|
||||
{
|
||||
mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
|
||||
mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
|
||||
mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
|
||||
mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
|
||||
//mem.nop_readwrite(logical_address+0x042, logical_address+0x7ff);
|
||||
mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
|
||||
mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
|
||||
}
|
||||
else if (m_system_type == FLEX_DC4_PIAIDE) // 2k ram for piaide on s09 board
|
||||
{
|
||||
//mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
|
||||
//mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
|
||||
//mem.install_readwrite_handler(logical_address+0x024, logical_address+0x03f, read8_delegate(FUNC(swtpc09_state::dmf2_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_control_reg_w),this));
|
||||
//mem.install_readwrite_handler(logical_address+0x040, logical_address+0x041, read8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf2_dma_address_reg_w),this));
|
||||
mem.install_ram(logical_address+0x000, logical_address+0x7ff, &RAM[0xf000]);
|
||||
mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
|
||||
mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
|
||||
}
|
||||
else // assume DMF3 controller
|
||||
{
|
||||
mem.install_readwrite_handler(logical_address+0x000, logical_address+0x01f, read8_delegate(FUNC(swtpc09_state::m6844_r),this), write8_delegate(FUNC(swtpc09_state::m6844_w),this));
|
||||
mem.install_readwrite_handler(logical_address+0x020, logical_address+0x023, read8_delegate(FUNC(fd1793_device::read), fdc), write8_delegate(FUNC(fd1793_device::write),fdc));
|
||||
mem.install_readwrite_handler(logical_address+0x024, logical_address+0x024, read8_delegate(FUNC(swtpc09_state::dmf3_control_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_control_reg_w),this));
|
||||
mem.install_readwrite_handler(logical_address+0x025, logical_address+0x025, read8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_r),this), write8_delegate(FUNC(swtpc09_state::dmf3_dma_address_reg_w),this));
|
||||
//mem.nop_readwrite(logical_address+0x030, logical_address+0x03f);
|
||||
mem.install_readwrite_handler(logical_address+0x040, logical_address+0x04f, read8_delegate(FUNC(via6522_device::read), via), write8_delegate(FUNC(via6522_device::write), via));
|
||||
//mem.nop_readwrite(logical_address+0x050, logical_address+0x7ff);
|
||||
mem.install_rom(logical_address+0x800, logical_address+0xfff, &RAM[0xf800]);
|
||||
mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
|
||||
}
|
||||
}
|
||||
else if (offset==0x0f) // then we need to leave in top part of ram and dat write
|
||||
{
|
||||
mem.install_ram(logical_address, logical_address+0x0eff, &RAM[physical_address]);
|
||||
mem.install_rom(logical_address+0xf00, logical_address+0xfff, &RAM[0xff00]);
|
||||
mem.install_write_handler(logical_address+0xff0, logical_address+0xfff, write8_delegate(FUNC(swtpc09_state::dat_w),this));
|
||||
|
||||
}
|
||||
else // all the rest is treated as ram, 1MB ram emulated
|
||||
{
|
||||
mem.install_ram(logical_address, logical_address+0x0fff, &RAM[physical_address]);
|
||||
}
|
||||
|
||||
// unused code to limit to 256k ram
|
||||
// else if (!(a12_to_a15 & 0x0c) ) // limit ram to 256k || a12_to_a15 == 0x02
|
||||
// {
|
||||
// memory_install_ram(space, logical_address, logical_address+0x0fff, 0, 0, &RAM[physical_address]);
|
||||
// }
|
||||
//
|
||||
// else // all the rest is treated as unallocated
|
||||
// {
|
||||
// memory_nop_readwrite(space, logical_address, logical_address+0x0fff, 0, 0);
|
||||
// }
|
||||
|
||||
m_bank[logical_address >> 12]->set_bank(physical_address >> 12);
|
||||
}
|
||||
|
||||
/* MC6844 DMA controller I/O */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user