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Converted intelfsh to a device, updated all users.

Browse Source 
Note CPS3 and G-NET testing is very limited due to lack of
CHDs. The other drivers have been verified to varying extents.
This commit is contained in:
Aaron Giles 2010-09-11 18:58:29 +00:00
parent 8182f611b0
commit dcedf21a43
9 changed files with 943 additions and 939 deletions
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567
src/emu/machine/intelfsh.c
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@ -14,6 +14,11 @@
#include "emu.h"
#include "intelfsh.h"
//**************************************************************************
// CONSTANTS
//**************************************************************************
enum
{
FM_NORMAL, // normal read/write
@ -32,185 +37,280 @@ enum
FM_BYTEPROGRAM,
};
struct flash_chip
//**************************************************************************
// DEVICE DEFINITIONS
//**************************************************************************
// 8-bit variants
DEFINE_TRIVIAL_DERIVED_DEVICE(intel_28f016s5_device_config, intelfsh8_device_config, intel_28f016s5_device, intelfsh8_device, "Sharp LH28F400 Flash", intelfsh_device_config::FLASH_SHARP_LH28F400)
DEFINE_TRIVIAL_DERIVED_DEVICE(fujitsu_29f016a_device_config, intelfsh8_device_config, fujitsu_29f016a_device, intelfsh8_device, "Fujitsu 29F016A Flash", intelfsh_device_config::FLASH_FUJITSU_29F016A)
DEFINE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f016s_device_config, intelfsh8_device_config, sharp_lh28f016s_device, intelfsh8_device, "Sharp LH28F016S Flash", intelfsh_device_config::FLASH_SHARP_LH28F016S)
DEFINE_TRIVIAL_DERIVED_DEVICE(intel_e28f008sa_device_config, intelfsh8_device_config, intel_e28f008sa_device, intelfsh8_device, "Intel E28F008SA Flash", intelfsh_device_config::FLASH_INTEL_E28F008SA)
DEFINE_TRIVIAL_DERIVED_DEVICE(macronix_29l001mc_device_config, intelfsh8_device_config, macronix_29l001mc_device, intelfsh8_device, "Macronix 29L001MC Flash", intelfsh_device_config::FLASH_MACRONIX_29L001MC)
DEFINE_TRIVIAL_DERIVED_DEVICE(panasonic_mn63f805mnp_device_config, intelfsh8_device_config, panasonic_mn63f805mnp_device, intelfsh8_device, "Panasonic MN63F805MNP Flash", intelfsh_device_config::FLASH_PANASONIC_MN63F805MNP)
DEFINE_TRIVIAL_DERIVED_DEVICE(sanyo_le26fv10n1ts_device_config, intelfsh8_device_config, sanyo_le26fv10n1ts_device, intelfsh8_device, "Sanyo LE26FV10N1TS Flash", intelfsh_device_config::FLASH_SANYO_LE26FV10N1TS)
const device_type INTEL_28F016S5 = intel_28f016s5_device_config::static_alloc_device_config;
const device_type SHARP_LH28F016S = sharp_lh28f016s_device_config::static_alloc_device_config;
const device_type FUJITSU_29F016A = fujitsu_29f016a_device_config::static_alloc_device_config;
const device_type INTEL_E28F008SA = intel_e28f008sa_device_config::static_alloc_device_config;
const device_type MACRONIX_29L001MC = macronix_29l001mc_device_config::static_alloc_device_config;
const device_type PANASONIC_MN63F805MNP = panasonic_mn63f805mnp_device_config::static_alloc_device_config;
const device_type SANYO_LE26FV10N1TS = sanyo_le26fv10n1ts_device_config::static_alloc_device_config;
// 16-bit variants
DEFINE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f400_device_config, intelfsh16_device_config, sharp_lh28f400_device, intelfsh16_device, "Sharp LH28F400 Flash", intelfsh_device_config::FLASH_SHARP_LH28F400)
DEFINE_TRIVIAL_DERIVED_DEVICE(intel_te28f160_device_config, intelfsh16_device_config, intel_te28f160_device, intelfsh16_device, "Intel TE28F160 Flash", intelfsh_device_config::FLASH_INTEL_TE28F160)
DEFINE_TRIVIAL_DERIVED_DEVICE(intel_e28f400_device_config, intelfsh16_device_config, intel_e28f400_device, intelfsh16_device, "Intel E28F400 Flash", intelfsh_device_config::FLASH_INTEL_E28F400)
DEFINE_TRIVIAL_DERIVED_DEVICE(sharp_unk128mbit_device_config, intelfsh16_device_config, sharp_unk128mbit_device, intelfsh16_device, "Sharp Unknown 128Mb Flash", intelfsh_device_config::FLASH_SHARP_UNK128MBIT)
const device_type SHARP_LH28F400 = sharp_lh28f400_device_config::static_alloc_device_config;
const device_type INTEL_TE28F160 = intel_te28f160_device_config::static_alloc_device_config;
const device_type INTEL_E28F400 = intel_e28f400_device_config::static_alloc_device_config;
const device_type SHARP_UNK128MBIT = sharp_unk128mbit_device_config::static_alloc_device_config;
//**************************************************************************
// DEVICE CONFIGURATION
//**************************************************************************
//-------------------------------------------------
// intelfsh_device_config - constructor
//-------------------------------------------------
intelfsh_device_config::intelfsh_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant)
: device_config(mconfig, type, name, tag, owner, clock),
device_config_nvram_interface(mconfig, *this),
m_type(variant)
{
int type;
int size;
int bits;
int status;
int erase_sector;
int sector_is_4k;
INT32 flash_mode;
INT32 flash_master_lock;
int device_id;
int maker_id;
emu_timer *timer;
void *flash_memory;
};
}
static struct flash_chip chips[FLASH_CHIPS_MAX];
static TIMER_CALLBACK( erase_finished )
intelfsh8_device_config::intelfsh8_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant)
: intelfsh_device_config(mconfig, type, name, tag, owner, clock, variant)
{
struct flash_chip *c = (struct flash_chip *)ptr;
}
switch( c->flash_mode )
intelfsh16_device_config::intelfsh16_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant)
: intelfsh_device_config(mconfig, type, name, tag, owner, clock, variant)
{
}
//**************************************************************************
// LIVE DEVICE
//**************************************************************************
//-------------------------------------------------
// intelfsh_device - constructor
//-------------------------------------------------
intelfsh_device::intelfsh_device(running_machine &_machine, const intelfsh_device_config &config)
: device_t(_machine, config),
device_nvram_interface(_machine, config, *this),
m_config(config),
m_size(0),
m_bits(config.m_type >> 8),
m_status(0x80),
m_erase_sector(0),
m_sector_is_4k(false),
m_flash_mode(FM_NORMAL),
m_flash_master_lock(false),
m_device_id(0),
m_maker_id(0),
m_timer(NULL),
m_flash_memory(NULL)
{
switch( config.m_type )
{
case intelfsh_device_config::FLASH_INTEL_28F016S5:
case intelfsh_device_config::FLASH_SHARP_LH28F016S:
m_bits = 8;
m_size = 0x200000;
m_maker_id = 0x89;
m_device_id = 0xaa;
break;
case intelfsh_device_config::FLASH_SHARP_LH28F400:
case intelfsh_device_config::FLASH_INTEL_E28F400:
m_bits = 16;
m_size = 0x80000;
m_maker_id = 0xb0;
m_device_id = 0xed;
break;
case intelfsh_device_config::FLASH_FUJITSU_29F016A:
m_bits = 8;
m_size = 0x200000;
m_maker_id = 0x04;
m_device_id = 0xad;
break;
case intelfsh_device_config::FLASH_INTEL_E28F008SA:
m_bits = 8;
m_size = 0x100000;
m_maker_id = 0x89;
m_device_id = 0xa2;
break;
case intelfsh_device_config::FLASH_INTEL_TE28F160:
m_bits = 16;
m_size = 0x200000;
m_maker_id = 0xb0;
m_device_id = 0xd0;
break;
case intelfsh_device_config::FLASH_SHARP_UNK128MBIT:
m_bits = 16;
m_size = 0x800000;
m_maker_id = 0xb0;
m_device_id = 0xb0;
break;
case intelfsh_device_config::FLASH_MACRONIX_29L001MC:
m_bits = 8;
m_size = 0x20000;
m_maker_id = 0xc2;
m_device_id = 0x51;
break;
case intelfsh_device_config::FLASH_PANASONIC_MN63F805MNP:
m_bits = 8;
m_size = 0x10000;
m_maker_id = 0x32;
m_device_id = 0x1b;
m_sector_is_4k = true;
break;
case intelfsh_device_config::FLASH_SANYO_LE26FV10N1TS:
m_bits = 8;
m_size = 0x20000;
m_maker_id = 0x62;
m_device_id = 0x13;
m_sector_is_4k = true;
break;
}
m_flash_memory = auto_alloc_array( &m_machine, UINT8, m_size );
}
intelfsh8_device::intelfsh8_device(running_machine &_machine, const intelfsh_device_config &config)
: intelfsh_device(_machine, config) { }
intelfsh16_device::intelfsh16_device(running_machine &_machine, const intelfsh_device_config &config)
: intelfsh_device(_machine, config) { }
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void intelfsh_device::device_start()
{
m_timer = device_timer_alloc(*this);
state_save_register_device_item( this, 0, m_status );
state_save_register_device_item( this, 0, m_flash_mode );
state_save_register_device_item( this, 0, m_flash_master_lock );
state_save_register_memory( machine, name(), tag(), 0, "m_flash_memory", m_flash_memory, m_bits/8, m_size / (m_bits/8), __FILE__, __LINE__ );
}
//-------------------------------------------------
// device_timer - handler timer events
//-------------------------------------------------
void intelfsh_device::device_timer(emu_timer &timer, int param, void *ptr)
{
switch( m_flash_mode )
{
case FM_READSTATUS:
c->status = 0x80;
m_status = 0x80;
break;
case FM_ERASEAMD4:
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
break;
}
}
void* intelflash_getmemptr(int chip)
{
struct flash_chip *c;
if( chip >= FLASH_CHIPS_MAX )
{
logerror( "intelflash_init: invalid chip %d\n", chip );
return 0;
}
c = &chips[ chip ];
return c->flash_memory;
}
//-------------------------------------------------
// nvram_default - called to initialize NVRAM to
// its default state
//-------------------------------------------------
void intelflash_init(running_machine *machine, int chip, int type, void *data)
void intelfsh_device::nvram_default()
{
struct flash_chip *c;
if( chip >= FLASH_CHIPS_MAX )
// region always wins
if (m_region != NULL)
{
logerror( "intelflash_init: invalid chip %d\n", chip );
UINT32 bytes = m_region->bytes();
if (bytes > m_size)
bytes = m_size;
memcpy(m_flash_memory, *m_region, bytes);
return;
}
c = &chips[ chip ];
c->type = type;
c->sector_is_4k = 0;
switch( c->type )
{
case FLASH_INTEL_28F016S5:
case FLASH_SHARP_LH28F016S:
c->bits = 8;
c->size = 0x200000;
c->maker_id = 0x89;
c->device_id = 0xaa;
break;
case FLASH_SHARP_LH28F400:
case FLASH_INTEL_E28F400:
c->bits = 16;
c->size = 0x80000;
c->maker_id = 0xb0;
c->device_id = 0xed;
break;
case FLASH_FUJITSU_29F016A:
c->bits = 8;
c->size = 0x200000;
c->maker_id = 0x04;
c->device_id = 0xad;
break;
case FLASH_INTEL_E28F008SA:
c->bits = 8;
c->size = 0x100000;
c->maker_id = 0x89;
c->device_id = 0xa2;
break;
case FLASH_INTEL_TE28F160:
c->bits = 16;
c->size = 0x200000;
c->maker_id = 0xb0;
c->device_id = 0xd0;
break;
case FLASH_SHARP_UNK128MBIT:
c->bits = 16;
c->size = 0x800000;
c->maker_id = 0xb0;
c->device_id = 0xb0;
break;
case FLASH_MACRONIX_29L001MC:
c->bits = 8;
c->size = 0x20000;
c->maker_id = 0xc2;
c->device_id = 0x51;
break;
case FLASH_PANASONIC_MN63F805MNP:
c->bits = 8;
c->size = 0x10000;
c->maker_id = 0x32;
c->device_id = 0x1b;
c->sector_is_4k = 1;
break;
case FLASH_SANYO_LE26FV10N1TS:
c->bits = 8;
c->size = 0x20000;
c->maker_id = 0x62;
c->device_id = 0x13;
c->sector_is_4k = 1;
break;
}
if( data == NULL )
{
data = auto_alloc_array( machine, UINT8, c->size );
memset( data, 0xff, c->size );
}
c->status = 0x80;
c->flash_mode = FM_NORMAL;
c->flash_master_lock = 0;
c->timer = timer_alloc(machine, erase_finished, c);
c->flash_memory = data;
state_save_register_item( machine, "intelfsh", NULL, chip, c->status );
state_save_register_item( machine, "intelfsh", NULL, chip, c->flash_mode );
state_save_register_item( machine, "intelfsh", NULL, chip, c->flash_master_lock );
state_save_register_memory( machine, "intelfsh", NULL, chip, "flash_memory", c->flash_memory, c->bits/8, c->size / (c->bits/8), __FILE__, __LINE__ );
memset( m_flash_memory, 0xff, m_size );
}
UINT32 intelflash_read(int chip, UINT32 address)
//-------------------------------------------------
// nvram_read - called to read NVRAM from the
// .nv file
//-------------------------------------------------
void intelfsh_device::nvram_read(mame_file &file)
{
mame_fread(&file, m_flash_memory, m_size);
}
//-------------------------------------------------
// nvram_write - called to write NVRAM to the
// .nv file
//-------------------------------------------------
void intelfsh_device::nvram_write(mame_file &file)
{
mame_fwrite(&file, m_flash_memory, m_size);
}
//-------------------------------------------------
// read_full - generic read, called by the
// bit-width-specific readers
//-------------------------------------------------
UINT32 intelfsh_device::read_full(UINT32 address)
{
UINT32 data = 0;
struct flash_chip *c;
if( chip >= FLASH_CHIPS_MAX )
{
logerror( "intelflash_read: invalid chip %d\n", chip );
return 0;
}
c = &chips[ chip ];
switch( c->flash_mode )
switch( m_flash_mode )
{
default:
case FM_NORMAL:
switch( c->bits )
switch( m_bits )
{
case 8:
{
UINT8 *flash_memory = (UINT8 *)c->flash_memory;
UINT8 *flash_memory = (UINT8 *)m_flash_memory;
data = flash_memory[ address ];
}
break;
case 16:
{
UINT16 *flash_memory = (UINT16 *)c->flash_memory;
UINT16 *flash_memory = (UINT16 *)m_flash_memory;
data = flash_memory[ address ];
}
break;
}
break;
case FM_READSTATUS:
data = c->status;
data = m_status;
break;
case FM_READAMDID3:
switch (address)
{
case 0: data = c->maker_id; break;
case 1: data = c->device_id; break;
case 0: data = m_maker_id; break;
case 1: data = m_device_id; break;
case 2: data = 0; break;
}
break;
@ -218,16 +318,16 @@ UINT32 intelflash_read(int chip, UINT32 address)
switch (address)
{
case 0: // maker ID
data = c->maker_id;
data = m_maker_id;
break;
case 1: // chip ID
data = c->device_id;
data = m_device_id;
break;
case 2: // block lock config
data = 0; // we don't support this yet
break;
case 3: // master lock config
if (c->flash_master_lock)
if (m_flash_master_lock)
{
data = 1;
}
@ -240,19 +340,19 @@ UINT32 intelflash_read(int chip, UINT32 address)
break;
case FM_ERASEAMD4:
// reads outside of the erasing sector return normal data
if ((address < c->erase_sector) || (address >= c->erase_sector+(64*1024)))
if ((address < m_erase_sector) || (address >= m_erase_sector+(64*1024)))
{
switch( c->bits )
switch( m_bits )
{
case 8:
{
UINT8 *flash_memory = (UINT8 *)c->flash_memory;
UINT8 *flash_memory = (UINT8 *)m_flash_memory;
data = flash_memory[ address ];
}
break;
case 16:
{
UINT16 *flash_memory = (UINT16 *)c->flash_memory;
UINT16 *flash_memory = (UINT16 *)m_flash_memory;
data = flash_memory[ address ];
}
break;
@ -260,8 +360,8 @@ UINT32 intelflash_read(int chip, UINT32 address)
}
else
{
c->status ^= ( 1 << 6 ) | ( 1 << 2 );
data = c->status;
m_status ^= ( 1 << 6 ) | ( 1 << 2 );
data = m_status;
}
break;
}
@ -271,19 +371,17 @@ UINT32 intelflash_read(int chip, UINT32 address)
return data;
}
void intelflash_write(int chip, UINT32 address, UINT32 data)
{
struct flash_chip *c;
if( chip >= FLASH_CHIPS_MAX )
{
logerror( "intelflash_write: invalid chip %d\n", chip );
return;
}
c = &chips[ chip ];
//-------------------------------------------------
// write_full - generic write, called by the
// bit-width-specific writers
//-------------------------------------------------
void intelfsh_device::write_full(UINT32 address, UINT32 data)
{
// logerror( "intelflash_write( %d, %08x, %08x )\n", chip, address, data );
switch( c->flash_mode )
switch( m_flash_mode )
{
case FM_NORMAL:
case FM_READSTATUS:
@ -293,32 +391,32 @@ void intelflash_write(int chip, UINT32 address, UINT32 data)
{
case 0xf0:
case 0xff: // reset chip mode
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
break;
case 0x90: // read ID
c->flash_mode = FM_READID;
m_flash_mode = FM_READID;
break;
case 0x40:
case 0x10: // program
c->flash_mode = FM_WRITEPART1;
m_flash_mode = FM_WRITEPART1;
break;
case 0x50: // clear status reg
c->status = 0x80;
c->flash_mode = FM_READSTATUS;
m_status = 0x80;
m_flash_mode = FM_READSTATUS;
break;
case 0x20: // block erase
c->flash_mode = FM_CLEARPART1;
m_flash_mode = FM_CLEARPART1;
break;
case 0x60: // set master lock
c->flash_mode = FM_SETMASTER;
m_flash_mode = FM_SETMASTER;
break;
case 0x70: // read status
c->flash_mode = FM_READSTATUS;
m_flash_mode = FM_READSTATUS;
break;
case 0xaa: // AMD ID select part 1
if( ( address & 0xfff ) == 0x555 )
{
c->flash_mode = FM_READAMDID1;
m_flash_mode = FM_READAMDID1;
}
break;
default:
@ -329,61 +427,61 @@ void intelflash_write(int chip, UINT32 address, UINT32 data)
case FM_READAMDID1:
if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 )
{
c->flash_mode = FM_READAMDID2;
m_flash_mode = FM_READAMDID2;
}
else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 )
{
c->flash_mode = FM_READAMDID2;
m_flash_mode = FM_READAMDID2;
}
else
{
logerror( "unexpected %08x=%02x in FM_READAMDID1\n", address, data & 0xff );
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
}
break;
case FM_READAMDID2:
if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x90 )
{
c->flash_mode = FM_READAMDID3;
m_flash_mode = FM_READAMDID3;
}
else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x90 )
{
c->flash_mode = FM_READAMDID3;
m_flash_mode = FM_READAMDID3;
}
else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0x80 )
{
c->flash_mode = FM_ERASEAMD1;
m_flash_mode = FM_ERASEAMD1;
}
else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0x80 )
{
c->flash_mode = FM_ERASEAMD1;
m_flash_mode = FM_ERASEAMD1;
}
else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xa0 )
{
c->flash_mode = FM_BYTEPROGRAM;
m_flash_mode = FM_BYTEPROGRAM;
}
else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xa0 )
{
c->flash_mode = FM_BYTEPROGRAM;
m_flash_mode = FM_BYTEPROGRAM;
}
else if( ( address & 0xffff ) == 0x555 && ( data & 0xff ) == 0xf0 )
{
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
}
else if( ( address & 0xffff ) == 0x5555 && ( data & 0xff ) == 0xf0 )
{
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
}
else
{
logerror( "unexpected %08x=%02x in FM_READAMDID2\n", address, data & 0xff );
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
}
break;
case FM_ERASEAMD1:
if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0xaa )
{
c->flash_mode = FM_ERASEAMD2;
m_flash_mode = FM_ERASEAMD2;
}
else
{
@ -393,11 +491,11 @@ void intelflash_write(int chip, UINT32 address, UINT32 data)
case FM_ERASEAMD2:
if( ( address & 0xffff ) == 0x2aa && ( data & 0xff ) == 0x55 )
{
c->flash_mode = FM_ERASEAMD3;
m_flash_mode = FM_ERASEAMD3;
}
else if( ( address & 0xffff ) == 0x2aaa && ( data & 0xff ) == 0x55 )
{
c->flash_mode = FM_ERASEAMD3;
m_flash_mode = FM_ERASEAMD3;
}
else
{
@ -408,57 +506,57 @@ void intelflash_write(int chip, UINT32 address, UINT32 data)
if( ( address & 0xfff ) == 0x555 && ( data & 0xff ) == 0x10 )
{
// chip erase
memset( c->flash_memory, 0xff, c->size);
memset( m_flash_memory, 0xff, m_size);
c->status = 1 << 3;
c->flash_mode = FM_ERASEAMD4;
m_status = 1 << 3;
m_flash_mode = FM_ERASEAMD4;
timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 17 ), 0 );
timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 17 ), 0 );
}
else if( ( data & 0xff ) == 0x30 )
{
// sector erase
// clear the 4k/64k block containing the current address to all 0xffs
switch( c->bits )
switch( m_bits )
{
case 8:
{
UINT8 *flash_memory = (UINT8 *)c->flash_memory;
if (c->sector_is_4k)
UINT8 *flash_memory = (UINT8 *)m_flash_memory;
if (m_sector_is_4k)
{
memset( &flash_memory[ address & ~0xfff ], 0xff, 4 * 1024 );
c->erase_sector = address & ~0xfff;
timer_adjust_oneshot( c->timer, ATTOTIME_IN_MSEC( 125 ), 0 );
m_erase_sector = address & ~0xfff;
timer_adjust_oneshot( m_timer, ATTOTIME_IN_MSEC( 125 ), 0 );
}
else
{
memset( &flash_memory[ address & ~0xffff ], 0xff, 64 * 1024 );
c->erase_sector = address & ~0xffff;
timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 );
m_erase_sector = address & ~0xffff;
timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 );
}
}
break;
case 16:
{
UINT16 *flash_memory = (UINT16 *)c->flash_memory;
if (c->sector_is_4k)
UINT16 *flash_memory = (UINT16 *)m_flash_memory;
if (m_sector_is_4k)
{
memset( &flash_memory[ address & ~0x7ff ], 0xff, 4 * 1024 );
c->erase_sector = address & ~0x7ff;
timer_adjust_oneshot( c->timer, ATTOTIME_IN_MSEC( 125 ), 0 );
m_erase_sector = address & ~0x7ff;
timer_adjust_oneshot( m_timer, ATTOTIME_IN_MSEC( 125 ), 0 );
}
else
{
memset( &flash_memory[ address & ~0x7fff ], 0xff, 64 * 1024 );
c->erase_sector = address & ~0x7fff;
timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 );
m_erase_sector = address & ~0x7fff;
timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 );
}
}
break;
}
c->status = 1 << 3;
c->flash_mode = FM_ERASEAMD4;
m_status = 1 << 3;
m_flash_mode = FM_ERASEAMD4;
}
else
{
@ -466,68 +564,68 @@ void intelflash_write(int chip, UINT32 address, UINT32 data)
}
break;
case FM_BYTEPROGRAM:
switch( c->bits )
switch( m_bits )
{
case 8:
{
UINT8 *flash_memory = (UINT8 *)c->flash_memory;
UINT8 *flash_memory = (UINT8 *)m_flash_memory;
flash_memory[ address ] = data;
}
break;
default:
logerror( "FM_BYTEPROGRAM not supported when c->bits == %d\n", c->bits );
logerror( "FM_BYTEPROGRAM not supported when m_bits == %d\n", m_bits );
break;
}
c->flash_mode = FM_NORMAL;
m_flash_mode = FM_NORMAL;
break;
case FM_WRITEPART1:
switch( c->bits )
switch( m_bits )
{
case 8:
{
UINT8 *flash_memory = (UINT8 *)c->flash_memory;
UINT8 *flash_memory = (UINT8 *)m_flash_memory;
flash_memory[ address ] = data;
}
break;
case 16:
{
UINT16 *flash_memory = (UINT16 *)c->flash_memory;
UINT16 *flash_memory = (UINT16 *)m_flash_memory;
flash_memory[ address ] = data;
}
break;
default:
logerror( "FM_WRITEPART1 not supported when c->bits == %d\n", c->bits );
logerror( "FM_WRITEPART1 not supported when m_bits == %d\n", m_bits );
break;
}
c->status = 0x80;
c->flash_mode = FM_READSTATUS;
m_status = 0x80;
m_flash_mode = FM_READSTATUS;
break;
case FM_CLEARPART1:
if( ( data & 0xff ) == 0xd0 )
{
// clear the 64k block containing the current address to all 0xffs
switch( c->bits )
switch( m_bits )
{
case 8:
{
UINT8 *flash_memory = (UINT8 *)c->flash_memory;
UINT8 *flash_memory = (UINT8 *)m_flash_memory;
memset( &flash_memory[ address & ~0xffff ], 0xff, 64 * 1024 );
}
break;
case 16:
{
UINT16 *flash_memory = (UINT16 *)c->flash_memory;
UINT16 *flash_memory = (UINT16 *)m_flash_memory;
memset( &flash_memory[ address & ~0x7fff ], 0xff, 64 * 1024 );
}
break;
default:
logerror( "FM_CLEARPART1 not supported when c->bits == %d\n", c->bits );
logerror( "FM_CLEARPART1 not supported when m_bits == %d\n", m_bits );
break;
}
c->status = 0x00;
c->flash_mode = FM_READSTATUS;
m_status = 0x00;
m_flash_mode = FM_READSTATUS;
timer_adjust_oneshot( c->timer, ATTOTIME_IN_SEC( 1 ), 0 );
timer_adjust_oneshot( m_timer, ATTOTIME_IN_SEC( 1 ), 0 );
break;
}
else
@ -539,53 +637,16 @@ void intelflash_write(int chip, UINT32 address, UINT32 data)
switch( data & 0xff )
{
case 0xf1:
c->flash_master_lock = 1;
m_flash_master_lock = true;
break;
case 0xd0:
c->flash_master_lock = 0;
m_flash_master_lock = false;
break;
default:
logerror( "unexpected %08x=%02x in FM_SETMASTER:\n", address, data & 0xff );
break;
}
c->flash_mode = FM_NORMAL;
break;
}
}
void nvram_handler_intelflash(running_machine *machine, int chip,mame_file *file,int read_or_write)
{
struct flash_chip *c;
if( chip >= FLASH_CHIPS_MAX )
{
logerror( "intelflash_nvram: invalid chip %d\n", chip );
return;
}
c = &chips[ chip ];
switch( c->bits )
{
case 8:
if (read_or_write)
{
mame_fwrite( file, c->flash_memory, c->size );
}
else if (file)
{
mame_fread( file, c->flash_memory, c->size );
}
break;
case 16:
if (read_or_write)
{
/// TODO: endian conversion
mame_fwrite( file, c->flash_memory, c->size );
}
else if (file)
{
mame_fread( file, c->flash_memory, c->size );
/// TODO: endian conversion
}
m_flash_mode = FM_NORMAL;
break;
}
}

246
src/emu/machine/intelfsh.h
View File

@ -5,24 +5,236 @@
#ifndef _INTELFLASH_H_
#define _INTELFLASH_H_
#define FLASH_CHIPS_MAX ( 56 )
#define FLASH_INTEL_28F016S5 ( 0 )
#define FLASH_SHARP_LH28F400 ( 1 )
#define FLASH_FUJITSU_29F016A ( 2 )
#define FLASH_INTEL_E28F008SA ( 3 )
#define FLASH_INTEL_TE28F160 ( 4 )
#define FLASH_SHARP_LH28F016S ( 5 )
#define FLASH_INTEL_E28F400 ( 6 )
#define FLASH_SHARP_UNK128MBIT ( 7 )
#define FLASH_MACRONIX_29L001MC ( 8 )
#define FLASH_PANASONIC_MN63F805MNP ( 9 )
#define FLASH_SANYO_LE26FV10N1TS ( 10 )
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
//**************************************************************************
#define MDRV_INTEL_28F016S5_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, INTEL_28F016S5, 0)
#define MDRV_SHARP_LH28F016S_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, SHARP_LH28F016S, 0)
#define MDRV_FUJITSU_29F016A_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, FUJITSU_29F016A, 0)
#define MDRV_INTEL_E28F400_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, INTEL_E28F400, 0)
#define MDRV_MACRONIX_29L001MC_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, MACRONIX_29L001MC, 0)
#define MDRV_PANASONIC_MN63F805MNP_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, PANASONIC_MN63F805MNP, 0)
#define MDRV_SANYO_LE26FV10N1TS_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, SANYO_LE26FV10N1TS, 0)
#define MDRV_SHARP_LH28F400_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, SHARP_LH28F400, 0)
#define MDRV_INTEL_E28F008SA_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, INTEL_E28F008SA, 0)
#define MDRV_INTEL_TE28F160_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, INTEL_TE28F160, 0)
#define MDRV_SHARP_UNK128MBIT_ADD(_tag) \
MDRV_DEVICE_ADD(_tag, SHARP_UNK128MBIT, 0)
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
class intelfsh_device;
// ======================> intelfsh_device_config
class intelfsh_device_config : public device_config,
public device_config_nvram_interface
{
friend class intelfsh_device;
protected:
// constants
enum
{
// 8-bit variants
FLASH_INTEL_28F016S5 = 0x0800,
FLASH_FUJITSU_29F016A,
FLASH_SHARP_LH28F016S,
FLASH_INTEL_E28F400,
FLASH_MACRONIX_29L001MC,
FLASH_PANASONIC_MN63F805MNP,
FLASH_SANYO_LE26FV10N1TS,
// 16-bit variants
FLASH_SHARP_LH28F400 = 0x1000,
FLASH_INTEL_E28F008SA,
FLASH_INTEL_TE28F160,
FLASH_SHARP_UNK128MBIT
};
// construction/destruction
intelfsh_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant);
// internal state
UINT32 m_type;
};
// ======================> intelfsh_device
class intelfsh_device : public device_t,
public device_nvram_interface
{
friend class intelfsh_device_config;
protected:
// construction/destruction
intelfsh_device(running_machine &_machine, const intelfsh_device_config &config);
public:
// helpers
void *memory() const { return m_flash_memory; }
protected:
// device-level overrides
virtual void device_start();
virtual void device_timer(emu_timer &timer, int param, void *ptr);
// device_intelfsh_interface overrides
virtual void nvram_default();
virtual void nvram_read(mame_file &file);
virtual void nvram_write(mame_file &file);
// derived helpers
UINT32 read_full(UINT32 offset);
void write_full(UINT32 offset, UINT32 data);
// internal state
const intelfsh_device_config & m_config;
INT32 m_size;
UINT8 m_bits;
UINT8 m_status;
INT32 m_erase_sector;
bool m_sector_is_4k;
INT32 m_flash_mode;
bool m_flash_master_lock;
UINT8 m_device_id;
UINT8 m_maker_id;
emu_timer * m_timer;
void * m_flash_memory;
};
// ======================> intelfsh8_device_config
class intelfsh8_device_config : public intelfsh_device_config
{
friend class intelfsh8_device;
protected:
// construction/destruction
intelfsh8_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant);
};
// ======================> intelfsh8_device
class intelfsh8_device : public intelfsh_device
{
friend class intelfsh8_device_config;
friend class intel_28f016s5_device_config;
friend class fujitsu_29f016a_device_config;
friend class sharp_lh28f016s_device_config;
friend class intel_e28f008sa_device_config;
friend class macronix_29l001mc_device_config;
friend class panasonic_mn63f805mnp_device_config;
friend class sanyo_le26fv10n1ts_device_config;
protected:
// construction/destruction
intelfsh8_device(running_machine &_machine, const intelfsh_device_config &config);
public:
// public interface
UINT8 read(offs_t offset) { return read_full(offset); }
void write(offs_t offset, UINT8 data) { write_full(offset, data); }
};
// ======================> intelfsh16_device_config
class intelfsh16_device_config : public intelfsh_device_config
{
friend class intelfsh16_device;
protected:
// construction/destruction
intelfsh16_device_config(const machine_config &mconfig, device_type type, const char *name, const char *tag, const device_config *owner, UINT32 clock, UINT32 variant);
};
// ======================> intelfsh16_device
class intelfsh16_device : public intelfsh_device
{
friend class intelfsh16_device_config;
friend class sharp_lh28f400_device_config;
friend class intel_te28f160_device_config;
friend class intel_e28f400_device_config;
friend class sharp_unk128mbit_device_config;
protected:
// construction/destruction
intelfsh16_device(running_machine &_machine, const intelfsh_device_config &config);
public:
// public interface
UINT16 read(offs_t offset) { return read_full(offset); }
void write(offs_t offset, UINT16 data) { write_full(offset, data); }
};
// ======================> trivial variants
// 8-bit variants
DECLARE_TRIVIAL_DERIVED_DEVICE(intel_28f016s5_device_config, intelfsh8_device_config, intel_28f016s5_device, intelfsh8_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(fujitsu_29f016a_device_config, intelfsh8_device_config, fujitsu_29f016a_device, intelfsh8_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f016s_device_config, intelfsh8_device_config, sharp_lh28f016s_device, intelfsh8_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(intel_e28f008sa_device_config, intelfsh8_device_config, intel_e28f008sa_device, intelfsh8_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(macronix_29l001mc_device_config, intelfsh8_device_config, macronix_29l001mc_device, intelfsh8_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(panasonic_mn63f805mnp_device_config, intelfsh8_device_config, panasonic_mn63f805mnp_device, intelfsh8_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(sanyo_le26fv10n1ts_device_config, intelfsh8_device_config, sanyo_le26fv10n1ts_device, intelfsh8_device)
// 16-bit variants
DECLARE_TRIVIAL_DERIVED_DEVICE(sharp_lh28f400_device_config, intelfsh16_device_config, sharp_lh28f400_device, intelfsh16_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(intel_te28f160_device_config, intelfsh16_device_config, intel_te28f160_device, intelfsh16_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(intel_e28f400_device_config, intelfsh16_device_config, intel_e28f400_device, intelfsh16_device)
DECLARE_TRIVIAL_DERIVED_DEVICE(sharp_unk128mbit_device_config, intelfsh16_device_config, sharp_unk128mbit_device, intelfsh16_device)
// device type definition
extern const device_type INTEL_28F016S5;
extern const device_type SHARP_LH28F016S;
extern const device_type FUJITSU_29F016A;
extern const device_type INTEL_E28F400;
extern const device_type MACRONIX_29L001MC;
extern const device_type PANASONIC_MN63F805MNP;
extern const device_type SANYO_LE26FV10N1TS;
extern const device_type SHARP_LH28F400;
extern const device_type INTEL_E28F008SA;
extern const device_type INTEL_TE28F160;
extern const device_type SHARP_UNK128MBIT;
extern void intelflash_init( running_machine *machine, int chip, int type, void *data );
extern UINT32 intelflash_read( int chip, UINT32 address );
extern void intelflash_write( int chip, UINT32 address, UINT32 value );
extern void nvram_handler_intelflash( running_machine *machine, int chip, mame_file *file, int read_or_write );
extern void* intelflash_getmemptr(int chip);
#endif

150
src/mame/drivers/cps3.c
View File

@ -337,6 +337,8 @@ Notes:
#define DMA_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(1,2))
static fujitsu_29f016a_device *flashrom[48];
static UINT32* decrypted_bios;
static UINT32* decrypted_gamerom;
@ -684,8 +686,6 @@ static void cps3_decrypt_bios(running_machine *machine)
static DRIVER_INIT( cps3 )
{
int i;
// cache pointers to regions
cps3_user4region = memory_region(machine,"user4");
cps3_user5region = memory_region(machine,"user5");
@ -711,9 +711,9 @@ static DRIVER_INIT( cps3 )
main->set_direct_update_handler(direct_update_delegate_create_static(cps3_direct_handler, *machine));
// flash roms
for (i=0;i<48;i++)
intelflash_init( machine, i, FLASH_FUJITSU_29F016A, NULL );
astring tempstr;
for (int index = 0; index < 48; index++)
flashrom[index] = machine->device<fujitsu_29f016a_device>(tempstr.format("flash%d", index));
cps3_eeprom = auto_alloc_array(machine, UINT32, 0x400/4);
}
@ -1363,22 +1363,22 @@ static READ32_HANDLER( cps3_gfxflash_r )
if (ACCESSING_BITS_24_31) // GFX Flash 1
{
logerror("read GFX flash chip %d addr %02x\n", flash1-8, (offset<<1));
result |= intelflash_read(flash1, (offset<<1) ) << 24;
result |= flashrom[flash1]->read( (offset<<1) ) << 24;
}
if (ACCESSING_BITS_16_23) // GFX Flash 2
{
logerror("read GFX flash chip %d addr %02x\n", flash2-8, (offset<<1));
result |= intelflash_read(flash2, (offset<<1) ) << 16;
result |= flashrom[flash2]->read( (offset<<1) ) << 16;
}
if (ACCESSING_BITS_8_15) // GFX Flash 1
{
logerror("read GFX flash chip %d addr %02x\n", flash1-8, (offset<<1)+1);
result |= intelflash_read(flash1, (offset<<1)+0x1 ) << 8;
result |= flashrom[flash1]->read( (offset<<1)+0x1 ) << 8;
}
if (ACCESSING_BITS_0_7) // GFX Flash 2
{
logerror("read GFX flash chip %d addr %02x\n", flash2-8, (offset<<1)+1);
result |= intelflash_read(flash2, (offset<<1)+0x1 ) << 0;
result |= flashrom[flash2]->read( (offset<<1)+0x1 ) << 0;
}
//printf("read GFX flash chips addr %02x returning %08x mem_mask %08x crambank %08x gfxbank %08x\n", offset*2, result,mem_mask, cram_bank, cram_gfxflash_bank );
@ -1404,25 +1404,25 @@ static WRITE32_HANDLER( cps3_gfxflash_w )
{
command = (data >> 24) & 0xff;
logerror("write to GFX flash chip %d addr %02x cmd %02x\n", flash1-8, (offset<<1), command);
intelflash_write(flash1, (offset<<1), command);
flashrom[flash1]->write( (offset<<1), command);
}
if (ACCESSING_BITS_16_23) // GFX Flash 2
{
command = (data >> 16) & 0xff;
logerror("write to GFX flash chip %d addr %02x cmd %02x\n", flash2-8, (offset<<1), command);
intelflash_write(flash2, (offset<<1), command);
flashrom[flash2]->write( (offset<<1), command);
}
if (ACCESSING_BITS_8_15) // GFX Flash 1
{
command = (data >> 8) & 0xff;
logerror("write to GFX flash chip %d addr %02x cmd %02x\n", flash1-8, (offset<<1)+1, command);
intelflash_write(flash1, (offset<<1)+0x1, command);
flashrom[flash1]->write( (offset<<1)+0x1, command);
}
if (ACCESSING_BITS_0_7) // GFX Flash 2
{
command = (data >> 0) & 0xff;
//if ( ((offset<<1)+1) != 0x555) printf("write to GFX flash chip %d addr %02x cmd %02x\n", flash1-8, (offset<<1)+1, command);
intelflash_write(flash2, (offset<<1)+0x1, command);
flashrom[flash2]->write( (offset<<1)+0x1, command);
}
/* make a copy in the linear memory region we actually use for drawing etc. having it stored in interleaved flash roms isnt' very useful */
@ -1430,8 +1430,8 @@ static WRITE32_HANDLER( cps3_gfxflash_w )
UINT32* romdata = (UINT32*)cps3_user5region;
int real_offset = 0;
UINT32 newdata;
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(flash1);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(flash2);
UINT8* ptr1 = (UINT8*)flashrom[flash1]->memory();
UINT8* ptr2 = (UINT8*)flashrom[flash2]->memory();
real_offset = ((cram_gfxflash_bank&0x3e) * 0x200000) + offset*4;
@ -1454,22 +1454,22 @@ static UINT32 cps3_flashmain_r(int base, UINT32 offset, UINT32 mem_mask)
if (ACCESSING_BITS_24_31) // Flash 1
{
// logerror("read flash chip %d addr %02x\n", base+0, offset*4 );
result |= (intelflash_read(base+0, offset)<<24);
result |= (flashrom[base+0]->read(offset)<<24);
}
if (ACCESSING_BITS_16_23) // Flash 1
{
// logerror("read flash chip %d addr %02x\n", base+1, offset*4 );
result |= (intelflash_read(base+1, offset)<<16);
result |= (flashrom[base+1]->read(offset)<<16);
}
if (ACCESSING_BITS_8_15) // Flash 1
{
// logerror("read flash chip %d addr %02x\n", base+2, offset*4 );
result |= (intelflash_read(base+2, offset)<<8);
result |= (flashrom[base+2]->read(offset)<<8);
}
if (ACCESSING_BITS_0_7) // Flash 1
{
// logerror("read flash chip %d addr %02x\n", base+3, offset*4 );
result |= (intelflash_read(base+3, offset)<<0);
result |= (flashrom[base+3]->read(offset)<<0);
}
// if (base==4) logerror("read flash chips addr %02x returning %08x\n", offset*4, result );
@ -1506,25 +1506,25 @@ static void cps3_flashmain_w(running_machine *machine, int base, UINT32 offset,
{
command = (data >> 24) & 0xff;
logerror("write to flash chip %d addr %02x cmd %02x\n", base+0, offset, command);
intelflash_write(base+0, offset, command);
flashrom[base+0]->write(offset, command);
}
if (ACCESSING_BITS_16_23) // Flash 2
{
command = (data >> 16) & 0xff;
logerror("write to flash chip %d addr %02x cmd %02x\n", base+1, offset, command);
intelflash_write(base+1, offset, command);
flashrom[base+1]->write(offset, command);
}
if (ACCESSING_BITS_8_15) // Flash 2
{
command = (data >> 8) & 0xff;
logerror("write to flash chip %d addr %02x cmd %02x\n", base+2, offset, command);
intelflash_write(base+2, offset, command);
flashrom[base+2]->write(offset, command);
}
if (ACCESSING_BITS_0_7) // Flash 2
{
command = (data >> 0) & 0xff;
logerror("write to flash chip %d addr %02x cmd %02x\n", base+3, offset, command);
intelflash_write(base+3, offset, command);
flashrom[base+3]->write(offset, command);
}
/* copy data into regions to execute from */
@ -1533,10 +1533,10 @@ static void cps3_flashmain_w(running_machine *machine, int base, UINT32 offset,
UINT32* romdata2 = (UINT32*)decrypted_gamerom;
int real_offset = 0;
UINT32 newdata;
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(base+0);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(base+1);
UINT8* ptr3 = (UINT8*)intelflash_getmemptr(base+2);
UINT8* ptr4 = (UINT8*)intelflash_getmemptr(base+3);
UINT8* ptr1 = (UINT8*)flashrom[base+0]->memory();
UINT8* ptr2 = (UINT8*)flashrom[base+1]->memory();
UINT8* ptr3 = (UINT8*)flashrom[base+2]->memory();
UINT8* ptr4 = (UINT8*)flashrom[base+3]->memory();
real_offset = offset * 4;
@ -2298,10 +2298,10 @@ static void precopy_to_flash(running_machine *machine)
for (i=0;i<0x800000;i+=4)
{
UINT32 data;
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(0);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(1);
UINT8* ptr3 = (UINT8*)intelflash_getmemptr(2);
UINT8* ptr4 = (UINT8*)intelflash_getmemptr(3);
UINT8* ptr1 = (UINT8*)flashrom[0]->memory();
UINT8* ptr2 = (UINT8*)flashrom[1]->memory();
UINT8* ptr3 = (UINT8*)flashrom[2]->memory();
UINT8* ptr4 = (UINT8*)flashrom[3]->memory();
data = romdata[i/4];
@ -2314,10 +2314,10 @@ static void precopy_to_flash(running_machine *machine)
for (i=0;i<0x800000;i+=4)
{
UINT32 data;
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(4);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(5);
UINT8* ptr3 = (UINT8*)intelflash_getmemptr(6);
UINT8* ptr4 = (UINT8*)intelflash_getmemptr(7);
UINT8* ptr1 = (UINT8*)flashrom[4]->memory();
UINT8* ptr2 = (UINT8*)flashrom[5]->memory();
UINT8* ptr3 = (UINT8*)flashrom[6]->memory();
UINT8* ptr4 = (UINT8*)flashrom[7]->memory();
data = romdata[(0x800000+i)/4];
@ -2339,8 +2339,8 @@ static void precopy_to_flash(running_machine *machine)
for (i=0;i<0x200000;i+=2)
{
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(flashnum);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(flashnum+1);
UINT8* ptr1 = (UINT8*)flashrom[flashnum]->memory();
UINT8* ptr2 = (UINT8*)flashrom[flashnum+1]->memory();
UINT32 dat = romdata[(thebase+i)/2];
ptr1[BYTE_XOR_LE(i+1)] = (dat&0xff000000)>>24;
@ -2365,10 +2365,10 @@ static void copy_from_nvram(running_machine *machine)
for (i=0;i<0x800000;i+=4)
{
UINT32 data;
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(0);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(1);
UINT8* ptr3 = (UINT8*)intelflash_getmemptr(2);
UINT8* ptr4 = (UINT8*)intelflash_getmemptr(3);
UINT8* ptr1 = (UINT8*)flashrom[0]->memory();
UINT8* ptr2 = (UINT8*)flashrom[1]->memory();
UINT8* ptr3 = (UINT8*)flashrom[2]->memory();
UINT8* ptr4 = (UINT8*)flashrom[3]->memory();
data = ((ptr1[i/4]<<24) | (ptr2[i/4]<<16) | (ptr3[i/4]<<8) | (ptr4[i/4]<<0));
@ -2384,10 +2384,10 @@ static void copy_from_nvram(running_machine *machine)
for (i=0;i<0x800000;i+=4)
{
UINT32 data;
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(4);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(5);
UINT8* ptr3 = (UINT8*)intelflash_getmemptr(6);
UINT8* ptr4 = (UINT8*)intelflash_getmemptr(7);
UINT8* ptr1 = (UINT8*)flashrom[4]->memory();
UINT8* ptr2 = (UINT8*)flashrom[5]->memory();
UINT8* ptr3 = (UINT8*)flashrom[6]->memory();
UINT8* ptr4 = (UINT8*)flashrom[7]->memory();
data = ((ptr1[i/4]<<24) | (ptr2[i/4]<<16) | (ptr3[i/4]<<8) | (ptr4[i/4]<<0));
@ -2409,8 +2409,8 @@ static void copy_from_nvram(running_machine *machine)
for (i=0;i<0x200000;i+=2)
{
UINT8* ptr1 = (UINT8*)intelflash_getmemptr(flashnum);
UINT8* ptr2 = (UINT8*)intelflash_getmemptr(flashnum+1);
UINT8* ptr1 = (UINT8*)flashrom[flashnum]->memory();
UINT8* ptr2 = (UINT8*)flashrom[flashnum+1]->memory();
UINT32 dat = (ptr1[i+0]<<8) |
(ptr1[i+1]<<24) |
(ptr2[i+0]<<0) |
@ -2446,21 +2446,15 @@ static void copy_from_nvram(running_machine *machine)
static NVRAM_HANDLER( cps3 )
{
int i;
if (read_or_write)
{
//printf("read_write\n");
mame_fwrite(file, cps3_eeprom, 0x400);
for (i=0;i<48;i++)
nvram_handler_intelflash( machine, i, file, read_or_write );
}
else if (file)
{
//printf("file\n");
mame_fread(file, cps3_eeprom, 0x400);
for (i=0;i<48;i++)
nvram_handler_intelflash( machine, i, file, read_or_write );
copy_from_nvram(machine); // copy data from flashroms back into user regions + decrypt into regions we execute/draw from.
}
@ -2562,6 +2556,56 @@ static MACHINE_CONFIG_START( cps3, driver_device )
42.9545MHz / 15.4445kHz = 2781.217 / 6 = 463.536 -> unlikely
*/
// 48 flash chips
MDRV_FUJITSU_29F016A_ADD("flash0")
MDRV_FUJITSU_29F016A_ADD("flash1")
MDRV_FUJITSU_29F016A_ADD("flash2")
MDRV_FUJITSU_29F016A_ADD("flash3")
MDRV_FUJITSU_29F016A_ADD("flash4")
MDRV_FUJITSU_29F016A_ADD("flash5")
MDRV_FUJITSU_29F016A_ADD("flash6")
MDRV_FUJITSU_29F016A_ADD("flash7")
MDRV_FUJITSU_29F016A_ADD("flash8")
MDRV_FUJITSU_29F016A_ADD("flash9")
MDRV_FUJITSU_29F016A_ADD("flash10")
MDRV_FUJITSU_29F016A_ADD("flash11")
MDRV_FUJITSU_29F016A_ADD("flash12")
MDRV_FUJITSU_29F016A_ADD("flash13")
MDRV_FUJITSU_29F016A_ADD("flash14")
MDRV_FUJITSU_29F016A_ADD("flash15")
MDRV_FUJITSU_29F016A_ADD("flash16")
MDRV_FUJITSU_29F016A_ADD("flash17")
MDRV_FUJITSU_29F016A_ADD("flash18")
MDRV_FUJITSU_29F016A_ADD("flash19")
MDRV_FUJITSU_29F016A_ADD("flash20")
MDRV_FUJITSU_29F016A_ADD("flash21")
MDRV_FUJITSU_29F016A_ADD("flash22")
MDRV_FUJITSU_29F016A_ADD("flash23")
MDRV_FUJITSU_29F016A_ADD("flash24")
MDRV_FUJITSU_29F016A_ADD("flash25")
MDRV_FUJITSU_29F016A_ADD("flash26")
MDRV_FUJITSU_29F016A_ADD("flash27")
MDRV_FUJITSU_29F016A_ADD("flash28")
MDRV_FUJITSU_29F016A_ADD("flash29")
MDRV_FUJITSU_29F016A_ADD("flash30")
MDRV_FUJITSU_29F016A_ADD("flash31")
MDRV_FUJITSU_29F016A_ADD("flash32")
MDRV_FUJITSU_29F016A_ADD("flash33")
MDRV_FUJITSU_29F016A_ADD("flash34")
MDRV_FUJITSU_29F016A_ADD("flash35")
MDRV_FUJITSU_29F016A_ADD("flash36")
MDRV_FUJITSU_29F016A_ADD("flash37")
MDRV_FUJITSU_29F016A_ADD("flash38")
MDRV_FUJITSU_29F016A_ADD("flash39")
MDRV_FUJITSU_29F016A_ADD("flash40")
MDRV_FUJITSU_29F016A_ADD("flash41")
MDRV_FUJITSU_29F016A_ADD("flash42")
MDRV_FUJITSU_29F016A_ADD("flash43")
MDRV_FUJITSU_29F016A_ADD("flash44")
MDRV_FUJITSU_29F016A_ADD("flash45")
MDRV_FUJITSU_29F016A_ADD("flash46")
MDRV_FUJITSU_29F016A_ADD("flash47")
MDRV_MACHINE_START(cps3)
MDRV_MACHINE_RESET(cps3)
MDRV_NVRAM_HANDLER( cps3 )

79
src/mame/drivers/firebeat.c
View File

@ -135,6 +135,8 @@ static UINT8 extend_board_irq_active;
static emu_timer *keyboard_timer;
static fujitsu_29f016a_device *flash[3];
static GCU_REGS gcu[2];
static VIDEO_START(firebeat)
@ -709,19 +711,19 @@ static READ32_HANDLER(flashram_r)
UINT32 r = 0;
if (ACCESSING_BITS_24_31)
{
r |= (intelflash_read(0, (offset*4)+0) & 0xff) << 24;
r |= (flash[0]->read((offset*4)+0) & 0xff) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= (intelflash_read(0, (offset*4)+1) & 0xff) << 16;
r |= (flash[0]->read((offset*4)+1) & 0xff) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= (intelflash_read(0, (offset*4)+2) & 0xff) << 8;
r |= (flash[0]->read((offset*4)+2) & 0xff) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= (intelflash_read(0, (offset*4)+3) & 0xff) << 0;
r |= (flash[0]->read((offset*4)+3) & 0xff) << 0;
}
return r;
}
@ -730,85 +732,85 @@ static WRITE32_HANDLER(flashram_w)
{
if (ACCESSING_BITS_24_31)
{
intelflash_write(0, (offset*4)+0, (data >> 24) & 0xff);
flash[0]->write((offset*4)+0, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
intelflash_write(0, (offset*4)+1, (data >> 16) & 0xff);
flash[0]->write((offset*4)+1, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
intelflash_write(0, (offset*4)+2, (data >> 8) & 0xff);
flash[0]->write((offset*4)+2, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
intelflash_write(0, (offset*4)+3, (data >> 0) & 0xff);
flash[0]->write((offset*4)+3, (data >> 0) & 0xff);
}
}
static READ32_HANDLER(soundflash_r)
{
UINT32 r = 0;
int chip;
fujitsu_29f016a_device *chip;
if (offset >= 0 && offset < 0x200000/4)
{
chip = 1;
chip = flash[1];
}
else
{
chip = 2;
chip = flash[2];
}
offset &= 0x7ffff;
if (ACCESSING_BITS_24_31)
{
r |= (intelflash_read(chip, (offset*4)+0) & 0xff) << 24;
r |= (chip->read((offset*4)+0) & 0xff) << 24;
}
if (ACCESSING_BITS_16_23)
{
r |= (intelflash_read(chip, (offset*4)+1) & 0xff) << 16;
r |= (chip->read((offset*4)+1) & 0xff) << 16;
}
if (ACCESSING_BITS_8_15)
{
r |= (intelflash_read(chip, (offset*4)+2) & 0xff) << 8;
r |= (chip->read((offset*4)+2) & 0xff) << 8;
}
if (ACCESSING_BITS_0_7)
{
r |= (intelflash_read(chip, (offset*4)+3) & 0xff) << 0;
r |= (chip->read((offset*4)+3) & 0xff) << 0;
}
return r;
}
static WRITE32_HANDLER(soundflash_w)
{
int chip;
fujitsu_29f016a_device *chip;
if (offset >= 0 && offset < 0x200000/4)
{
chip = 1;
chip = flash[1];
}
else
{
chip = 2;
chip = flash[2];
}
offset &= 0x7ffff;
if (ACCESSING_BITS_24_31)
{
intelflash_write(chip, (offset*4)+0, (data >> 24) & 0xff);
chip->write((offset*4)+0, (data >> 24) & 0xff);
}
if (ACCESSING_BITS_16_23)
{
intelflash_write(chip, (offset*4)+1, (data >> 16) & 0xff);
chip->write((offset*4)+1, (data >> 16) & 0xff);
}
if (ACCESSING_BITS_8_15)
{
intelflash_write(chip, (offset*4)+2, (data >> 8) & 0xff);
chip->write((offset*4)+2, (data >> 8) & 0xff);
}
if (ACCESSING_BITS_0_7)
{
intelflash_write(chip, (offset*4)+3, (data >> 0) & 0xff);
chip->write((offset*4)+3, (data >> 0) & 0xff);
}
}
@ -1687,6 +1689,10 @@ static MACHINE_START( firebeat )
/* configure fast RAM regions for DRC */
ppcdrc_add_fastram(machine->device("maincpu"), 0x00000000, 0x01ffffff, FALSE, work_ram);
flash[0] = machine->device<fujitsu_29f016a_device>("flash0");
flash[1] = machine->device<fujitsu_29f016a_device>("flash1");
flash[2] = machine->device<fujitsu_29f016a_device>("flash2");
}
static ADDRESS_MAP_START( firebeat_map, ADDRESS_SPACE_PROGRAM, 32 )
@ -1724,11 +1730,11 @@ static READ8_DEVICE_HANDLER( soundram_r )
{
if (offset >= 0 && offset < 0x200000)
{
return intelflash_read(1, offset & 0x1fffff);
return flash[1]->read(offset & 0x1fffff);
}
else if (offset >= 0x200000 && offset < 0x400000)
{
return intelflash_read(2, offset & 0x1fffff);
return flash[2]->read(offset & 0x1fffff);
}
return 0;
}
@ -1743,13 +1749,6 @@ static const ymz280b_interface ymz280b_intf =
DEVCB_HANDLER(soundram_r)
};
static NVRAM_HANDLER(firebeat)
{
nvram_handler_intelflash(machine, 0, file, read_or_write);
nvram_handler_intelflash(machine, 1, file, read_or_write);
nvram_handler_intelflash(machine, 2, file, read_or_write);
}
static INPUT_PORTS_START(ppp)
PORT_START("IN0")
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_BUTTON1 ) // Left
@ -1904,8 +1903,8 @@ static MACHINE_RESET( firebeat )
for (i=0; i < 0x200000; i++)
{
sound[i] = intelflash_read(1, i);
sound[i+0x200000] = intelflash_read(2, i);
sound[i] = flash[1]->read(i);
sound[i+0x200000] = flash[2]->read(i);
}
SCSIGetDevice( atapi_device_data[1], &cd );
@ -1921,10 +1920,13 @@ static MACHINE_CONFIG_START( firebeat, driver_device )
MDRV_MACHINE_START(firebeat)
MDRV_MACHINE_RESET(firebeat)
MDRV_NVRAM_HANDLER(firebeat)
MDRV_RTC65271_ADD("rtc", NULL)
MDRV_FUJITSU_29F016A_ADD("flash0")
MDRV_FUJITSU_29F016A_ADD("flash1")
MDRV_FUJITSU_29F016A_ADD("flash2")
/* video hardware */
MDRV_SCREEN_ADD("screen", RASTER)
MDRV_SCREEN_REFRESH_RATE(60)
@ -1960,11 +1962,15 @@ static MACHINE_CONFIG_START( firebeat2, driver_device )
MDRV_CPU_PROGRAM_MAP(firebeat_map)
MDRV_CPU_VBLANK_INT("lscreen", firebeat_interrupt)
MDRV_MACHINE_START(firebeat)
MDRV_MACHINE_RESET(firebeat)
MDRV_NVRAM_HANDLER(firebeat)
MDRV_RTC65271_ADD("rtc", NULL)
MDRV_FUJITSU_29F016A_ADD("flash0")
MDRV_FUJITSU_29F016A_ADD("flash1")
MDRV_FUJITSU_29F016A_ADD("flash2")
/* video hardware */
MDRV_PALETTE_LENGTH(32768)
MDRV_PALETTE_INIT(RRRRR_GGGGG_BBBBB)
@ -2176,9 +2182,6 @@ static void init_firebeat(running_machine *machine)
UINT8 *rom = memory_region(machine, "user2");
atapi_init(machine);
intelflash_init(machine, 0, FLASH_FUJITSU_29F016A, NULL);
intelflash_init(machine, 1, FLASH_FUJITSU_29F016A, NULL);
intelflash_init(machine, 2, FLASH_FUJITSU_29F016A, NULL);
pc16552d_init(machine, 0, 19660800, comm_uart_irq_callback, 0); // Network UART
pc16552d_init(machine, 1, 24000000, midi_uart_irq_callback, 0); // MIDI UART

54
src/mame/drivers/konamigv.c
View File

@ -132,6 +132,9 @@ static UINT32 trackball_data[ 2 ];
static UINT16 btc_trackball_prev[ 4 ];
static UINT32 btc_trackball_data[ 4 ];
static fujitsu_29f016a_device *flash8[4];
static sharp_lh28f400_device *flash16[4];
/* EEPROM handlers */
static WRITE32_DEVICE_HANDLER( eeprom_w )
@ -365,6 +368,7 @@ static MACHINE_CONFIG_START( konamigv, driver_device )
MDRV_SOUND_ROUTE( 1, "rspeaker", 1.0 )
MACHINE_CONFIG_END
static INPUT_PORTS_START( konamigv )
PORT_START("P1")
PORT_BIT( 0x00000001, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
@ -426,14 +430,6 @@ INPUT_PORTS_END
/* Simpsons Bowling */
static NVRAM_HANDLER( simpbowl )
{
nvram_handler_intelflash( machine, 0, file, read_or_write );
nvram_handler_intelflash( machine, 1, file, read_or_write );
nvram_handler_intelflash( machine, 2, file, read_or_write );
nvram_handler_intelflash( machine, 3, file, read_or_write );
}
static READ32_HANDLER( flash_r )
{
int reg = offset*2;
@ -455,8 +451,8 @@ static READ32_HANDLER( flash_r )
int chip = (flash_address >= 0x200000) ? 2 : 0;
int ret;
ret = intelflash_read(chip, flash_address & 0x1fffff) & 0xff;
ret |= intelflash_read(chip+1, flash_address & 0x1fffff)<<8;
ret = flash8[chip]->read(flash_address & 0x1fffff) & 0xff;
ret |= flash8[chip+1]->read(flash_address & 0x1fffff)<<8;
flash_address++;
return ret;
@ -479,8 +475,8 @@ static WRITE32_HANDLER( flash_w )
{
case 0:
chip = (flash_address >= 0x200000) ? 2 : 0;
intelflash_write(chip, flash_address & 0x1fffff, data&0xff);
intelflash_write(chip+1, flash_address & 0x1fffff, (data>>8)&0xff);
flash8[chip]->write(flash_address & 0x1fffff, data&0xff);
flash8[chip+1]->write(flash_address & 0x1fffff, (data>>8)&0xff);
break;
case 1:
@ -525,10 +521,10 @@ static READ32_HANDLER( unknown_r )
static DRIVER_INIT( simpbowl )
{
intelflash_init( machine, 0, FLASH_FUJITSU_29F016A, NULL );
intelflash_init( machine, 1, FLASH_FUJITSU_29F016A, NULL );
intelflash_init( machine, 2, FLASH_FUJITSU_29F016A, NULL );
intelflash_init( machine, 3, FLASH_FUJITSU_29F016A, NULL );
flash8[0] = machine->device<fujitsu_29f016a_device>("flash0");
flash8[1] = machine->device<fujitsu_29f016a_device>("flash1");
flash8[2] = machine->device<fujitsu_29f016a_device>("flash2");
flash8[3] = machine->device<fujitsu_29f016a_device>("flash3");
memory_install_readwrite32_handler( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x1f680080, 0x1f68008f, 0, 0, flash_r, flash_w );
memory_install_read32_handler ( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x1f6800c0, 0x1f6800c7, 0, 0, trackball_r );
@ -538,7 +534,10 @@ static DRIVER_INIT( simpbowl )
}
static MACHINE_CONFIG_DERIVED( simpbowl, konamigv )
MDRV_NVRAM_HANDLER( simpbowl )
MDRV_FUJITSU_29F016A_ADD("flash0")
MDRV_FUJITSU_29F016A_ADD("flash1")
MDRV_FUJITSU_29F016A_ADD("flash2")
MDRV_FUJITSU_29F016A_ADD("flash3")
MACHINE_CONFIG_END
static INPUT_PORTS_START( simpbowl )
@ -558,11 +557,11 @@ static READ32_HANDLER( btcflash_r )
{
if (mem_mask == 0x0000ffff)
{
return intelflash_read(0, offset*2);
return flash16[0]->read(offset*2);
}
else if (mem_mask == 0xffff0000)
{
return intelflash_read(0, (offset*2)+1)<<16;
return flash16[0]->read((offset*2)+1)<<16;
}
return 0;
@ -572,11 +571,11 @@ static WRITE32_HANDLER( btcflash_w )
{
if (mem_mask == 0x0000ffff)
{
intelflash_write(0, offset*2, data&0xffff);
flash16[0]->write(offset*2, data&0xffff);
}
else if (mem_mask == 0xffff0000)
{
intelflash_write(0, (offset*2)+1, (data>>16)&0xffff);
flash16[0]->write((offset*2)+1, (data>>16)&0xffff);
}
}
@ -607,14 +606,9 @@ static WRITE32_HANDLER( btc_trackball_w )
// mame_printf_debug( "w %08x %08x %08x %08x\n", cpu_get_pc(space->cpu), offset, data, mem_mask );
}
static NVRAM_HANDLER( btchamp )
{
nvram_handler_intelflash( machine, 0, file, read_or_write );
}
static DRIVER_INIT( btchamp )
{
intelflash_init( machine, 0, FLASH_SHARP_LH28F400, NULL );
flash16[0] = machine->device<sharp_lh28f400_device>("flash");
memory_install_readwrite32_handler( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x1f680080, 0x1f68008f, 0, 0, btc_trackball_r, btc_trackball_w );
memory_nop_write ( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x1f6800e0, 0x1f6800e3, 0, 0 );
@ -624,7 +618,7 @@ static DRIVER_INIT( btchamp )
}
static MACHINE_CONFIG_DERIVED( btchamp, konamigv )
MDRV_NVRAM_HANDLER( btchamp )
MDRV_SHARP_LH28F400_ADD("flash")
MACHINE_CONFIG_END
static INPUT_PORTS_START( btchamp )
@ -700,7 +694,7 @@ static WRITE32_HANDLER( kdeadeye_0_w )
static DRIVER_INIT( kdeadeye )
{
intelflash_init( machine, 0, FLASH_SHARP_LH28F400, NULL );
flash16[0] = machine->device<sharp_lh28f400_device>("flash");
memory_install_read_port ( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x1f680080, 0x1f680083, 0, 0, "GUNX1" );
memory_install_read_port ( cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x1f680090, 0x1f680093, 0, 0, "GUNY1" );
@ -714,7 +708,7 @@ static DRIVER_INIT( kdeadeye )
}
static MACHINE_CONFIG_DERIVED( kdeadeye, konamigv )
MDRV_NVRAM_HANDLER( btchamp )
MDRV_SHARP_LH28F400_ADD("flash")
MACHINE_CONFIG_END
static INPUT_PORTS_START( kdeadeye )

603
src/mame/drivers/ksys573.c
View File

File diff suppressed because it is too large Load Diff

57
src/mame/drivers/naomi.c
View File

@ -1242,6 +1242,8 @@ Notes:
#define CPU_CLOCK (200000000)
static UINT32 *dc_sound_ram;
static macronix_29l001mc_device *awflash;
/* MD2 MD1 MD0 MD6 MD4 MD3 MD5 MD7 MD8 */
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK };
@ -1301,13 +1303,6 @@ jvseeprom_default_game[] =
{ "keyboard", { 0x32, 0x7E, 0x10, 0x42, 0x45, 0x42, 0x30, 0x09, 0x10, 0x00, 0x01, 0x01, 0x01, 0x00, 0x11, 0x11, 0x11, 0x11, 0x32, 0x7E, 0x10, 0x42, 0x45, 0x42, 0x30, 0x09, 0x10, 0x00, 0x01, 0x01, 0x01, 0x00, 0x11, 0x11, 0x11, 0x11, 0xF0, 0x4A, 0x0C, 0x0C, 0xF0, 0x4A, 0x0C, 0x0C, 0x18, 0x09, 0x01, 0x20, 0x02, 0x00, 0x3C, 0x00, 0x32, 0x00, 0x00, 0x00, 0x18, 0x09, 0x01, 0x20, 0x02, 0x00, 0x3C, 0x00, 0x32, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } }
};
static NVRAM_HANDLER( aw_nvram )
{
nvram_handler_intelflash(machine, 0, file, read_or_write);
// TODO: save AW NVRAM at 00200000
}
static NVRAM_HANDLER( naomi_eeproms )
{
if (read_or_write)
@ -1516,8 +1511,8 @@ ADDRESS_MAP_END
static READ64_HANDLER( aw_flash_r )
{
return (UINT64)intelflash_read(0, offset*8) | (UINT64)intelflash_read(0, (offset*8)+1)<<8 | (UINT64)intelflash_read(0, (offset*8)+2)<<16 | (UINT64)intelflash_read(0, (offset*8)+3)<<24 |
(UINT64)intelflash_read(0, (offset*8)+4)<<32 | (UINT64)intelflash_read(0, (offset*8)+5)<<40 | (UINT64)intelflash_read(0, (offset*8)+6)<<48 | (UINT64)intelflash_read(0, (offset*8)+7)<<56;
return (UINT64)awflash->read(offset*8) | (UINT64)awflash->read((offset*8)+1)<<8 | (UINT64)awflash->read((offset*8)+2)<<16 | (UINT64)awflash->read((offset*8)+3)<<24 |
(UINT64)awflash->read((offset*8)+4)<<32 | (UINT64)awflash->read((offset*8)+5)<<40 | (UINT64)awflash->read((offset*8)+6)<<48 | (UINT64)awflash->read((offset*8)+7)<<56;
}
static WRITE64_HANDLER( aw_flash_w )
@ -1536,7 +1531,7 @@ static WRITE64_HANDLER( aw_flash_w )
data >>= (i*8);
intelflash_write(0, addr, data);
awflash->write(addr, data);
}
INLINE int decode_reg32_64(running_machine *machine, UINT32 offset, UINT64 mem_mask, UINT64 *shift)
@ -1601,8 +1596,8 @@ static WRITE64_HANDLER( aw_modem_w )
static ADDRESS_MAP_START( aw_map, ADDRESS_SPACE_PROGRAM, 64 )
/* Area 0 */
AM_RANGE(0x00000000, 0x0001ffff) AM_READWRITE( aw_flash_r, aw_flash_w )
AM_RANGE(0xa0000000, 0xa001ffff) AM_READWRITE( aw_flash_r, aw_flash_w )
AM_RANGE(0x00000000, 0x0001ffff) AM_READWRITE( aw_flash_r, aw_flash_w ) AM_REGION("awflash", 0)
AM_RANGE(0xa0000000, 0xa001ffff) AM_READWRITE( aw_flash_r, aw_flash_w ) AM_REGION("awflash", 0)
AM_RANGE(0x00200000, 0x0021ffff) AM_RAM // battery backed up RAM
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE( dc_sysctrl_r, dc_sysctrl_w )
@ -1989,7 +1984,7 @@ static MACHINE_CONFIG_DERIVED( aw, naomi_base )
// MDRV_DEVICE_REMOVE("main_eeprom")
MDRV_CPU_MODIFY("maincpu")
MDRV_CPU_PROGRAM_MAP(aw_map)
MDRV_NVRAM_HANDLER(aw_nvram)
MDRV_MACRONIX_29L001MC_ADD("awflash")
MDRV_AW_ROM_BOARD_ADD("rom_board", "user1")
MACHINE_CONFIG_END
@ -2264,7 +2259,7 @@ ROM_START( naomi2 )
ROM_END
ROM_START( awbios )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8400000, "user1", ROMREGION_ERASE)
@ -6438,7 +6433,7 @@ static const UINT32 salmankt_key = 0x34b74;
static DRIVER_INIT( atomiswave )
{
UINT64 *ROM = (UINT64 *)memory_region(machine, "maincpu");
UINT64 *ROM = (UINT64 *)memory_region(machine, "awflash");
#if 0
UINT8 *dcdata = (UINT8 *)memory_region(machine, "user1");
FILE *f;
@ -6450,7 +6445,7 @@ static DRIVER_INIT( atomiswave )
// patch out long startup delay
ROM[0x98e/8] = (ROM[0x98e/8] & U64(0xffffffffffff)) | (UINT64)0x0009<<48;
intelflash_init(machine, 0, FLASH_MACRONIX_29L001MC, memory_region(machine, "maincpu"));
awflash = machine->device<macronix_29l001mc_device>("awflash");
}
#define AW_DRIVER_INIT(DRIVER) \
@ -6482,7 +6477,7 @@ AW_DRIVER_INIT(vfurlong)
AW_DRIVER_INIT(salmankt)
ROM_START( fotns )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6497,7 +6492,7 @@ ROM_START( fotns )
ROM_END
ROM_START( rangrmsn )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6510,7 +6505,7 @@ ROM_START( rangrmsn )
ROM_END
ROM_START( sprtshot )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6522,7 +6517,7 @@ ROM_START( sprtshot )
ROM_END
ROM_START( xtrmhunt )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6536,7 +6531,7 @@ ROM_START( xtrmhunt )
ROM_END
ROM_START( xtrmhnt2 )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6555,7 +6550,7 @@ ROM_START( xtrmhnt2 )
ROM_END
ROM_START( dolphin )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6568,7 +6563,7 @@ ROM_START( dolphin )
ROM_END
ROM_START( demofist )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6583,7 +6578,7 @@ ROM_START( demofist )
ROM_END
ROM_START( rumblef )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6598,7 +6593,7 @@ ROM_START( rumblef )
ROM_END
ROM_START( ngbc )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6606,7 +6601,7 @@ ROM_START( ngbc )
ROM_END
ROM_START( kofnw )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6620,7 +6615,7 @@ ROM_START( kofnw )
ROM_END
ROM_START( kofnwj )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6635,7 +6630,7 @@ ROM_START( kofnwj )
ROM_END
ROM_START( kov7sprt )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x8000000, "user1", ROMREGION_ERASE)
@ -6650,7 +6645,7 @@ ROM_START( kov7sprt )
ROM_END
ROM_START( ggisuka )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x9000000, "user1", ROMREGION_ERASE)
@ -6666,7 +6661,7 @@ ROM_START( ggisuka )
ROM_END
ROM_START( vfurlong )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x9000000, "user1", ROMREGION_ERASE)
@ -6681,7 +6676,7 @@ ROM_START( vfurlong )
ROM_END
ROM_START( salmankt )
ROM_REGION( 0x200000, "maincpu", 0)
ROM_REGION( 0x200000, "awflash", 0)
AW_BIOS
ROM_REGION( 0x9000000, "user1", ROMREGION_ERASE)

52
src/mame/drivers/seibuspi.c
View File

@ -740,6 +740,8 @@ Notes:
UINT32 *spimainram;
static intel_e28f008sa_device *flash[2];
static UINT8 *z80_rom;
/********************************************************************/
@ -1085,11 +1087,11 @@ static READ8_DEVICE_HANDLER( flashrom_read )
logerror("Flash Read: %08X\n", offset);
if( offset < 0x100000 )
{
return intelflash_read(0, offset);
return flash[0]->read(offset);
}
else if( offset < 0x200000 )
{
return intelflash_read(1, offset - 0x100000 );
return flash[1]->read(offset - 0x100000 );
}
return 0;
}
@ -1099,11 +1101,11 @@ static WRITE8_DEVICE_HANDLER( flashrom_write )
logerror("Flash Write: %08X, %02X\n", offset, data);
if( offset < 0x100000 )
{
intelflash_write(0, offset + 1, data);
flash[0]->write(offset + 1, data);
}
else if( offset < 0x200000 )
{
intelflash_write(1, offset - 0x100000 + 1, data);
flash[1]->write(offset - 0x100000 + 1, data);
}
}
@ -1785,12 +1787,6 @@ GFXDECODE_END
/********************************************************************************/
static NVRAM_HANDLER( spi )
{
nvram_handler_intelflash(machine, 0, file, read_or_write);
nvram_handler_intelflash(machine, 1, file, read_or_write);
}
/* this is a 93C46 but with reset delay */
static const eeprom_interface eeprom_intf =
{
@ -1842,19 +1838,19 @@ static MACHINE_RESET( spi )
/* If the first value doesn't match, the game shows a checksum error */
/* If any of the other values are wrong, the game goes to update mode */
intelflash_write(0, 0, 0xff);
intelflash_write(0, 0, 0x10);
intelflash_write(0, 0, flash_data); /* country code */
flash[0]->write(0, 0xff);
flash[0]->write(0, 0x10);
flash[0]->write(0, flash_data); /* country code */
for (i=0; i < 0x100000; i++)
{
intelflash_write(0, 0, 0xff);
sound[i] = intelflash_read(0, i);
flash[0]->write(0, 0xff);
sound[i] = flash[0]->read(i);
}
for (i=0; i < 0x100000; i++)
{
intelflash_write(1, 0, 0xff);
sound[0x100000+i] = intelflash_read(1, i);
flash[1]->write(0, 0xff);
sound[0x100000+i] = flash[1]->read(i);
}
}
@ -1872,12 +1868,14 @@ static MACHINE_CONFIG_START( spi, driver_device )
MDRV_MACHINE_START(spi)
MDRV_MACHINE_RESET(spi)
MDRV_NVRAM_HANDLER(spi)
MDRV_EEPROM_ADD("eeprom", eeprom_intf)
MDRV_DS2404_ADD("ds2404", 1995, 1, 1)
MDRV_INTEL_E28F008SA_ADD("flash0")
MDRV_INTEL_E28F008SA_ADD("flash1")
/* video hardware */
MDRV_SCREEN_ADD("screen", RASTER)
MDRV_SCREEN_REFRESH_RATE(54)
@ -1927,7 +1925,8 @@ static MACHINE_CONFIG_DERIVED( sxx2f, spi ) /* Intel i386DX @ 25MHz, YMF271 @ 16
MDRV_MACHINE_START(sxx2f)
MDRV_MACHINE_RESET(sxx2f)
MDRV_NVRAM_HANDLER(0)
MDRV_DEVICE_REMOVE("flash0")
MDRV_DEVICE_REMOVE("flash1")
MACHINE_CONFIG_END
@ -1948,7 +1947,8 @@ static MACHINE_CONFIG_DERIVED( sxx2g, spi ) /* single board version using measur
MDRV_MACHINE_START(sxx2f)
MDRV_MACHINE_RESET(sxx2f)
MDRV_NVRAM_HANDLER(0)
MDRV_DEVICE_REMOVE("flash0")
MDRV_DEVICE_REMOVE("flash1")
MACHINE_CONFIG_END
@ -2079,8 +2079,8 @@ static READ32_HANDLER ( rfjet_speedup_r )
static void init_spi(running_machine *machine)
{
intelflash_init( machine, 0, FLASH_INTEL_E28F008SA, NULL );
intelflash_init( machine, 1, FLASH_INTEL_E28F008SA, NULL );
flash[0] = machine->device<intel_e28f008sa_device>("flash0");
flash[1] = machine->device<intel_e28f008sa_device>("flash1");
seibuspi_text_decrypt(memory_region(machine, "gfx1"));
seibuspi_bg_decrypt(memory_region(machine, "gfx2"), memory_region_length(machine, "gfx2"));
@ -2141,8 +2141,8 @@ static DRIVER_INIT( viprp1o )
static void init_rf2(running_machine *machine)
{
intelflash_init( machine, 0, FLASH_INTEL_E28F008SA, NULL );
intelflash_init( machine, 1, FLASH_INTEL_E28F008SA, NULL );
flash[0] = machine->device<intel_e28f008sa_device>("flash0");
flash[1] = machine->device<intel_e28f008sa_device>("flash1");
memory_install_read32_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x0282AC, 0x0282AF, 0, 0, rf2_speedup_r );
seibuspi_rise10_text_decrypt(memory_region(machine, "gfx1"));
@ -2165,8 +2165,8 @@ static DRIVER_INIT( rdft2us )
static void init_rfjet(running_machine *machine)
{
intelflash_init( machine, 0, FLASH_INTEL_E28F008SA, NULL );
intelflash_init( machine, 1, FLASH_INTEL_E28F008SA, NULL );
flash[0] = machine->device<intel_e28f008sa_device>("flash0");
flash[1] = machine->device<intel_e28f008sa_device>("flash1");
memory_install_read32_handler(cputag_get_address_space(machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0x002894c, 0x002894f, 0, 0, rfjet_speedup_r );
seibuspi_rise11_text_decrypt(memory_region(machine, "gfx1"));

74
src/mame/drivers/taitogn.c
View File

@ -328,6 +328,10 @@ Type 3 (PCMCIA Compact Flash Adaptor + Compact Flash card, sealed together with
#include "sound/psx.h"
#include "audio/taito_zm.h"
static intel_te28f160_device *biosflash;
static intel_e28f400_device *pgmflash;
static intel_te28f160_device *sndflash[3];
static unsigned char cis[512];
static int locked;
@ -438,75 +442,75 @@ static WRITE32_HANDLER(rf5c296_mem_w)
// Flash handling
static UINT32 gen_flash_r(running_machine *machine, int chip, offs_t offset, UINT32 mem_mask)
static UINT32 gen_flash_r(intelfsh16_device *device, offs_t offset, UINT32 mem_mask)
{
UINT32 res = 0;
offset *= 2;
if(ACCESSING_BITS_0_15)
res |= intelflash_read(chip, offset);
res |= device->read(offset);
if(ACCESSING_BITS_16_31)
res |= intelflash_read(chip, offset+1) << 16;
res |= device->read(offset+1) << 16;
return res;
}
static void gen_flash_w(running_machine *machine, int chip, offs_t offset, UINT32 data, UINT32 mem_mask)
static void gen_flash_w(intelfsh16_device *device, offs_t offset, UINT32 data, UINT32 mem_mask)
{
offset *= 2;
if(ACCESSING_BITS_0_15)
intelflash_write(chip, offset, data);
device->write(offset, data);
if(ACCESSING_BITS_16_31)
intelflash_write(chip, offset+1, data >> 16);
device->write(offset+1, data >> 16);
}
static READ32_HANDLER(flash_subbios_r)
{
return gen_flash_r(space->machine, 0, offset, mem_mask);
return gen_flash_r(biosflash, offset, mem_mask);
}
static WRITE32_HANDLER(flash_subbios_w)
{
gen_flash_w(space->machine, 0, offset, data, mem_mask);
gen_flash_w(biosflash, offset, data, mem_mask);
}
static READ32_HANDLER(flash_mn102_r)
{
return gen_flash_r(space->machine, 1, offset, mem_mask);
return gen_flash_r(pgmflash, offset, mem_mask);
}
static WRITE32_HANDLER(flash_mn102_w)
{
gen_flash_w(space->machine, 1, offset, data, mem_mask);
gen_flash_w(pgmflash, offset, data, mem_mask);
}
static READ32_HANDLER(flash_s1_r)
{
return gen_flash_r(space->machine, 2, offset, mem_mask);
return gen_flash_r(sndflash[0], offset, mem_mask);
}
static WRITE32_HANDLER(flash_s1_w)
{
gen_flash_w(space->machine, 2, offset, data, mem_mask);
gen_flash_w(sndflash[0], offset, data, mem_mask);
}
static READ32_HANDLER(flash_s2_r)
{
return gen_flash_r(space->machine, 3, offset, mem_mask);
return gen_flash_r(sndflash[1], offset, mem_mask);
}
static WRITE32_HANDLER(flash_s2_w)
{
gen_flash_w(space->machine, 3, offset, data, mem_mask);
gen_flash_w(sndflash[1], offset, data, mem_mask);
}
static READ32_HANDLER(flash_s3_r)
{
return gen_flash_r(space->machine, 4, offset, mem_mask);
return gen_flash_r(sndflash[2], offset, mem_mask);
}
static WRITE32_HANDLER(flash_s3_w)
{
gen_flash_w(space->machine, 4, offset, data, mem_mask);
gen_flash_w(sndflash[2], offset, data, mem_mask);
}
@ -800,32 +804,13 @@ static READ32_HANDLER( gnet_mahjong_panel_r )
// Init and reset
static NVRAM_HANDLER( coh3002t )
{
nvram_handler_intelflash(machine, 0, file, read_or_write);
nvram_handler_intelflash(machine, 1, file, read_or_write);
nvram_handler_intelflash(machine, 2, file, read_or_write);
nvram_handler_intelflash(machine, 3, file, read_or_write);
nvram_handler_intelflash(machine, 4, file, read_or_write);
if(!file) {
// Only the subbios needs to preexist for the board to work
memcpy(intelflash_getmemptr(0), memory_region(machine, "subbios"), 0x200000);
}
}
static DRIVER_INIT( coh3002t )
{
// Sub-bios (u30)
intelflash_init(machine, 0, FLASH_INTEL_TE28F160, 0);
// mn102 program flash (u27)
intelflash_init(machine, 1, FLASH_INTEL_E28F400, 0);
// Samples (u29, u55, u56)
intelflash_init(machine, 2, FLASH_INTEL_TE28F160, 0);
intelflash_init(machine, 3, FLASH_INTEL_TE28F160, 0);
intelflash_init(machine, 4, FLASH_INTEL_TE28F160, 0);
biosflash = machine->device<intel_te28f160_device>("biosflash");
pgmflash = machine->device<intel_e28f400_device>("pgmflash");
sndflash[0] = machine->device<intel_te28f160_device>("sndflash0");
sndflash[1] = machine->device<intel_te28f160_device>("sndflash1");
sndflash[2] = machine->device<intel_te28f160_device>("sndflash2");
psx_driver_init(machine);
znsec_init(0, tt10);
@ -948,10 +933,15 @@ static MACHINE_CONFIG_START( coh3002t, driver_device )
MDRV_AT28C16_ADD( "at28c16", 0 )
MDRV_IDE_CONTROLLER_ADD( "card", 0 )
MDRV_NVRAM_HANDLER( coh3002t )
MDRV_MB3773_ADD("mb3773")
MDRV_INTEL_TE28F160_ADD("biosflash")
MDRV_INTEL_E28F008SA_ADD("pgmflash")
MDRV_INTEL_TE28F160_ADD("sndflash0")
MDRV_INTEL_TE28F160_ADD("sndflash1")
MDRV_INTEL_TE28F160_ADD("sndflash2")
MDRV_FRAGMENT_ADD( taito_zoom_sound )
MACHINE_CONFIG_END
@ -1075,7 +1065,7 @@ INPUT_PORTS_END
#define TAITOGNET_BIOS \
ROM_REGION32_LE( 0x080000, "mainbios", 0 ) \
ROM_LOAD( "coh-3002t.353", 0x000000, 0x080000, CRC(03967fa7) SHA1(0e17fec2286e4e25deb23d40e41ce0986f373d49) ) \
ROM_REGION16_LE( 0x200000, "subbios", 0 ) \
ROM_REGION16_LE( 0x200000, "biosflash", 0 ) \
ROM_SYSTEM_BIOS( 0, "v1", "G-NET Bios v1" ) \
ROM_LOAD16_WORD_BIOS(0, "flash.u30", 0x000000, 0x200000, CRC(c48c8236) SHA1(c6dad60266ce2ff635696bc0d91903c543273559) ) \
ROM_SYSTEM_BIOS( 1, "v2", "G-NET Bios v2" ) \