xbox: add secondary channel to ide controller and derive nv2a from the agp_device class (nw)

src/mame/drivers/chihiro.cpp

@@ -429,6 +429,7 @@ Thanks to Alex, Mr Mudkips, and Philip Burke for this info.
 
 #include "emu.h"
 #include "machine/pci.h"
+#include "machine/idectrl.h"
 #include "includes/xbox_pci.h"
 #include "includes/xbox.h"
 

src/mame/drivers/xbox.cpp

@@ -9,6 +9,7 @@
 
 #include "emu.h"
 #include "machine/pci.h"
+#include "machine/idectrl.h"
 #include "includes/xbox_pci.h"
 #include "includes/xbox.h"
 

src/mame/includes/xbox.h

@@ -134,10 +134,6 @@ protected:
 
 	virtual void machine_start() override;
 	DECLARE_WRITE_LINE_MEMBER(maincpu_interrupt);
-	DECLARE_WRITE_LINE_MEMBER(ohci_usb_interrupt_changed);
-	DECLARE_WRITE_LINE_MEMBER(smbus_interrupt_changed);
-	DECLARE_WRITE_LINE_MEMBER(ide_interrupt_changed);
-	DECLARE_WRITE_LINE_MEMBER(nv2a_interrupt_changed);
 	IRQ_CALLBACK_MEMBER(irq_callback);
 
 	nv2a_renderer *nvidia_nv2a;

src/mame/includes/xbox_pci.h

@@ -106,6 +106,7 @@ public:
 	DECLARE_WRITE_LINE_MEMBER(irq11);
 	DECLARE_WRITE_LINE_MEMBER(irq10);
 	DECLARE_WRITE_LINE_MEMBER(irq14);
+	DECLARE_WRITE_LINE_MEMBER(irq15);
 
 protected:
 	virtual void device_start() override;
@@ -358,6 +359,10 @@ public:
 	virtual void config_map(address_map &map) override;
 
 	DECLARE_WRITE32_MEMBER(class_rev_w);
+	DECLARE_READ8_MEMBER(pri_read_cs1_r);
+	DECLARE_WRITE8_MEMBER(pri_write_cs1_w);
+	DECLARE_READ8_MEMBER(sec_read_cs1_r);
+	DECLARE_WRITE8_MEMBER(sec_write_cs1_w);
 
 protected:
 	virtual void device_start() override;
@@ -367,6 +372,8 @@ protected:
 		uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space) override;
 
 private:
+	required_device<bus_master_ide_controller_device> m_pri;
+	required_device<bus_master_ide_controller_device> m_sec;
 	devcb_write_line m_pri_interrupt_handler;
 	devcb_write_line m_sec_interrupt_handler;
 	void ide_pri_command(address_map &map);
@@ -394,6 +401,11 @@ public:
 	}
 	nv2a_agp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
 
+	void config_map(address_map& map) override;
+
+	DECLARE_READ32_MEMBER(unknown_r);
+	DECLARE_WRITE32_MEMBER(unknown_w);
+
 protected:
 	virtual void device_start() override;
 	virtual void device_reset() override;
@@ -405,7 +417,7 @@ DECLARE_DEVICE_TYPE(NV2A_AGP, nv2a_agp_device)
  * NV2A 3D Accelerator
  */
 
-class nv2a_gpu_device : public pci_device {
+class nv2a_gpu_device : public agp_device {
 public:
 	template <typename T>
 	nv2a_gpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&cpu_tag)

src/mame/machine/xbox.cpp

@@ -3,6 +3,7 @@
 
 #include "emu.h"
 #include "machine/pci.h"
+#include "machine/idectrl.h"
 #include "includes/xbox_pci.h"
 #include "includes/xbox.h"
 
@@ -553,26 +554,6 @@ IRQ_CALLBACK_MEMBER(xbox_base_state::irq_callback)
 	return r;
 }
 
-WRITE_LINE_MEMBER(xbox_base_state::ohci_usb_interrupt_changed)
-{
-	mcpxlpc->irq1(state);
-}
-
-WRITE_LINE_MEMBER(xbox_base_state::nv2a_interrupt_changed)
-{
-	mcpxlpc->irq3(state);
-}
-
-WRITE_LINE_MEMBER(xbox_base_state::smbus_interrupt_changed)
-{
-	mcpxlpc->irq11(state);
-}
-
-WRITE_LINE_MEMBER(xbox_base_state::ide_interrupt_changed)
-{
-	mcpxlpc->irq14(state);
-}
-
 /*
  * SMbus devices
  */
@@ -882,20 +863,20 @@ void xbox_base_state::xbox_base(machine_config &config)
 	NV2A_RAM(config,        ":pci:00.3", 0, 128); // 128 megabytes
 	MCPX_ISALPC(config,     ":pci:01.0", 0, 0).interrupt_output().set(FUNC(xbox_base_state::maincpu_interrupt));
 	XBOX_SUPERIO(config,    ":pci:01.0:0", 0);
-	MCPX_SMBUS(config,      ":pci:01.1", 0).interrupt_handler().set(FUNC(xbox_base_state::smbus_interrupt_changed));
+	MCPX_SMBUS(config,      ":pci:01.1", 0).interrupt_handler().set(":pci:01.0", FUNC(mcpx_isalpc_device::irq11)); //.set(FUNC(xbox_base_state::smbus_interrupt_changed));
 	XBOX_PIC16LC(config,    ":pci:01.1:110", 0); // these 3 are on smbus number 1
 	XBOX_CX25871(config,    ":pci:01.1:145", 0);
 	XBOX_EEPROM(config,     ":pci:01.1:154", 0);
-	MCPX_OHCI(config,       ":pci:02.0", 0).interrupt_handler().set(FUNC(xbox_base_state::ohci_usb_interrupt_changed));
+	MCPX_OHCI(config,       ":pci:02.0", 0).interrupt_handler().set(":pci:01.0", FUNC(mcpx_isalpc_device::irq1));  //.set(FUNC(xbox_base_state::ohci_usb_interrupt_changed));
 	MCPX_OHCI(config,       ":pci:03.0", 0);
 	MCPX_ETH(config,        ":pci:04.0", 0);
 	MCPX_APU(config,        ":pci:05.0", 0, m_maincpu);
 	MCPX_AC97_AUDIO(config, ":pci:06.0", 0);
 	MCPX_AC97_MODEM(config, ":pci:06.1", 0);
 	PCI_BRIDGE(config,      ":pci:08.0", 0, 0x10de01b8, 0);
-	MCPX_IDE(config,        ":pci:09.0", 0).pri_interrupt_handler().set(FUNC(xbox_base_state::ide_interrupt_changed));
+	MCPX_IDE(config,        ":pci:09.0", 0).pri_interrupt_handler().set(":pci:01.0", FUNC(mcpx_isalpc_device::irq14));  //.set(FUNC(xbox_base_state::ide_interrupt_changed));
 	NV2A_AGP(config,        ":pci:1e.0", 0, 0x10de01b7, 0);
-	NV2A_GPU(config,        ":pci:1e.0:00.0", 0, m_maincpu).interrupt_handler().set(FUNC(xbox_base_state::nv2a_interrupt_changed));
+	NV2A_GPU(config,        ":pci:1e.0:00.0", 0, m_maincpu).interrupt_handler().set(":pci:01.0", FUNC(mcpx_isalpc_device::irq3)); //.set(FUNC(xbox_base_state::nv2a_interrupt_changed));
 
 	/* video hardware */
 	screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));

src/mame/machine/xbox_pci.cpp

@@ -3,6 +3,7 @@
 
 #include "emu.h"
 #include "machine/pci.h"
+#include "machine/idectrl.h"
 #include "includes/xbox_pci.h"
 #include "includes/xbox.h"
 #include "machine/ds128x.h"
@@ -329,6 +330,11 @@ WRITE_LINE_MEMBER(mcpx_isalpc_device::irq14)
 	pic8259_2->ir6_w(state);
 }
 
+WRITE_LINE_MEMBER(mcpx_isalpc_device::irq15)
+{
+	pic8259_2->ir7_w(state);
+}
+
 uint32_t mcpx_isalpc_device::acknowledge()
 {
 	return pic8259_1->acknowledge();
@@ -1043,6 +1049,8 @@ void mcpx_ide_device::ide_pri_command(address_map &map)
 
 void mcpx_ide_device::ide_pri_control(address_map &map)
 {
+	// 3f6
+	map(2, 2).rw(*this, FUNC(mcpx_ide_device::pri_read_cs1_r), FUNC(mcpx_ide_device::pri_write_cs1_w));
 }
 
 void mcpx_ide_device::ide_sec_command(address_map &map)
@@ -1052,6 +1060,8 @@ void mcpx_ide_device::ide_sec_command(address_map &map)
 
 void mcpx_ide_device::ide_sec_control(address_map &map)
 {
+	// 376
+	map(2, 2).rw(*this, FUNC(mcpx_ide_device::sec_read_cs1_r), FUNC(mcpx_ide_device::sec_write_cs1_w));
 }
 
 void mcpx_ide_device::ide_io(address_map &map)
@@ -1063,7 +1073,9 @@ void mcpx_ide_device::ide_io(address_map &map)
 mcpx_ide_device::mcpx_ide_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
 	: pci_device(mconfig, MCPX_IDE, tag, owner, clock),
 	m_pri_interrupt_handler(*this),
-	m_sec_interrupt_handler(*this)
+	m_sec_interrupt_handler(*this),
+	m_pri(*this, "ide1"),
+	m_sec(*this, "ide2")
 {
 	set_ids(0x10de01bc, 0, 0x01018a, 0);
 }
@@ -1101,20 +1113,79 @@ void mcpx_ide_device::device_add_mconfig(machine_config &config)
 void mcpx_ide_device::map_extra(uint64_t memory_window_start, uint64_t memory_window_end, uint64_t memory_offset, address_space *memory_space,
 	uint64_t io_window_start, uint64_t io_window_end, uint64_t io_offset, address_space *io_space)
 {
-	if (~pclass & 1)
+	if (~pclass & 1) // compatibility mode
+	{
 		io_space->install_device(0x1f0, 0x1f7, *this, &mcpx_ide_device::ide_pri_command);
-	/*if (~pclass & 4)
+		io_space->install_device(0x3f4, 0x3f7, *this, &mcpx_ide_device::ide_pri_control);
-	    io_space->install_device(0x3f0, 0x3f7, *this, &mcpx_ide_device::ide_sec_command);*/
+	}
+	if (~pclass & 4)
+	{
+		io_space->install_device(0x170, 0x177, *this, &mcpx_ide_device::ide_sec_command);
+		io_space->install_device(0x374, 0x377, *this, &mcpx_ide_device::ide_sec_control);
+	}
 }
 
 WRITE32_MEMBER(mcpx_ide_device::class_rev_w)
 {
 	if (ACCESSING_BITS_8_15)
 	{
+		uint32_t old = pclass;
 		// bit 0 specifies if the primary channel is in compatibility or native-pci mode
 		// bit 2 specifies if the secondary channel is in compatibility or native-pci mode
 		pclass = (pclass & 0xfffffffa) | ((data >> 8) & 5);
+		if (old ^ pclass)
+		{
+			if (~pclass & 1) // compatibility mode
+			{
+				bank_infos[0].flags |= M_DISABLED;
+				bank_infos[1].flags |= M_DISABLED;
 			}
+			else
+			{
+				bank_infos[0].flags &= ~M_DISABLED;
+				bank_infos[1].flags &= ~M_DISABLED;
+			}
+			if (~pclass & 1) // compatibility mode
+			{
+				bank_infos[2].flags |= M_DISABLED;
+				bank_infos[3].flags |= M_DISABLED;
+			}
+			else
+			{
+				bank_infos[2].flags &= ~M_DISABLED;
+				bank_infos[3].flags &= ~M_DISABLED;
+			}
+			remap_cb();
+		}
+	}
+}
+
+READ8_MEMBER(mcpx_ide_device::pri_read_cs1_r)
+{
+	if (!(command & 1))
+		return 0xff;
+	return m_pri->read_cs1(1, 0xff0000) >> 16;
+}
+
+WRITE8_MEMBER(mcpx_ide_device::pri_write_cs1_w)
+{
+	if (!(command & 1))
+		return;
+	m_pri->write_cs1(1, data << 16, 0xff0000);
+}
+
+READ8_MEMBER(mcpx_ide_device::sec_read_cs1_r)
+{
+	if (!(command & 1))
+		return 0xff;
+	return m_sec->read_cs1(1, 0xff0000) >> 16;
+}
+
+WRITE8_MEMBER(mcpx_ide_device::sec_write_cs1_w)
+{
+	if (!(command & 1))
+		return;
+	m_sec->write_cs1(1, data << 16, 0xff0000);
 }
 
 WRITE_LINE_MEMBER(mcpx_ide_device::ide_pri_interrupt)
@@ -1133,6 +1204,12 @@ WRITE_LINE_MEMBER(mcpx_ide_device::ide_sec_interrupt)
 
 DEFINE_DEVICE_TYPE(NV2A_AGP, nv2a_agp_device, "nv2a_agp", "NV2A AGP Host to PCI Bridge")
 
+void nv2a_agp_device::config_map(address_map& map)
+{
+	agp_bridge_device::config_map(map);
+	map(0x40, 0xff).rw(FUNC(nv2a_agp_device::unknown_r), FUNC(nv2a_agp_device::unknown_w));
+}
+
 nv2a_agp_device::nv2a_agp_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
 	: agp_bridge_device(mconfig, NV2A_AGP, tag, owner, clock)
 {
@@ -1148,6 +1225,24 @@ void nv2a_agp_device::device_reset()
 	agp_bridge_device::device_reset();
 }
 
+READ32_MEMBER(nv2a_agp_device::unknown_r)
+{
+	// 4c 8 or 32
+	// 44 8
+	// 45 8
+	// 46 8
+	// 47 8
+	printf("R %08X %08X\n",0x40+offset*4,mem_mask);
+	if (offset == 3)
+		return 1;
+	return 0;
+}
+
+WRITE32_MEMBER(nv2a_agp_device::unknown_w)
+{
+	printf("W %08X %08X %08X\n", 0x40+offset*4, mem_mask, data);
+}
+
 /*
  * NV2A 3D Accelerator
  */
@@ -1165,7 +1260,7 @@ void nv2a_gpu_device::nv2a_mirror(address_map &map)
 }
 
 nv2a_gpu_device::nv2a_gpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
-	pci_device(mconfig, NV2A_GPU, tag, owner, clock),
+	agp_device(mconfig, NV2A_GPU, tag, owner, clock),
 	nvidia_nv2a(nullptr),
 	cpu(*this, finder_base::DUMMY_TAG),
 	m_interrupt_handler(*this),
@@ -1176,7 +1271,7 @@ nv2a_gpu_device::nv2a_gpu_device(const machine_config &mconfig, const char *tag,
 
 void nv2a_gpu_device::device_start()
 {
-	pci_device::device_start();
+	agp_device::device_start();
 	m_interrupt_handler.resolve_safe();
 	add_map(0x01000000, M_MEM, FUNC(nv2a_gpu_device::nv2a_mmio));
 	bank_infos[0].adr = 0xfd000000;
@@ -1196,7 +1291,7 @@ void nv2a_gpu_device::device_start()
 
 void nv2a_gpu_device::device_reset()
 {
-	pci_device::device_reset();
+	agp_device::device_reset();
 	nvidia_nv2a->set_ram_base(m_program->get_read_ptr(0));
 }
 

src/mame/machine/xbox_usb.cpp

@@ -3,6 +3,7 @@
 
 #include "emu.h"
 #include "machine/pci.h"
+#include "machine/idectrl.h"
 #include "includes/xbox_pci.h"
 #include "includes/xbox_usb.h"
 #include "includes/xbox.h"