CCPU and T-11 pointer-ification.
This commit is contained in:
Aaron Giles
parent
a20dadc633
commit
dd87df6926
File diff suppressed because it is too large
Load Diff
@ -23,7 +23,7 @@
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enum
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{
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CCPU_PC=1,
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Ccpu_get_flags,
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CCPU_FLAGS,
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CCPU_A,
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CCPU_B,
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CCPU_I,
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@ -40,11 +40,14 @@ enum
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CONFIG STRUCTURE
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***************************************************************************/
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typedef UINT8 (*ccpu_input_func)(const device_config *device);
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typedef void (*ccpu_vector_func)(const device_config *device, INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift);
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typedef struct _ccpu_config ccpu_config;
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struct _ccpu_config
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{
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UINT8 (*external_input)(void); /* if NULL, assume JMI jumper is present */
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void (*vector_callback)(INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift);
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ccpu_input_func external_input; /* if NULL, assume JMI jumper is present */
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ccpu_vector_func vector_callback;
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};
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@ -54,7 +57,7 @@ struct _ccpu_config
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***************************************************************************/
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CPU_GET_INFO( ccpu );
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void ccpu_wdt_timer_trigger(void);
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void ccpu_wdt_timer_trigger(const device_config *device);
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CPU_DISASSEMBLE( ccpu );
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@ -21,32 +21,20 @@
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*
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*************************************/
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typedef struct
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typedef struct _t11_state t11_state;
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struct _t11_state
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{
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PAIR ppc; /* previous program counter */
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PAIR reg[8];
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PAIR psw;
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UINT16 op;
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UINT16 initial_pc;
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UINT8 wait_state;
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UINT8 irq_state;
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INT32 interrupt_cycles;
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cpu_irq_callback irq_callback;
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PAIR ppc; /* previous program counter */
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PAIR reg[8];
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PAIR psw;
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UINT16 initial_pc;
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UINT8 wait_state;
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UINT8 irq_state;
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int icount;
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cpu_irq_callback irq_callback;
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const device_config *device;
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const address_space *program;
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} t11_Regs;
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static t11_Regs t11;
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/*************************************
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*
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* Global variables
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*
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*************************************/
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static int t11_ICount;
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};
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@ -57,16 +45,16 @@ static int t11_ICount;
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*************************************/
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/* registers of various sizes */
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#define REGD(x) t11.reg[x].d
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#define REGW(x) t11.reg[x].w.l
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#define REGB(x) t11.reg[x].b.l
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#define REGD(x) reg[x].d
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#define REGW(x) reg[x].w.l
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#define REGB(x) reg[x].b.l
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/* PC, SP, and PSW definitions */
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#define SP REGW(6)
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#define PC REGW(7)
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#define SPD REGD(6)
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#define PCD REGD(7)
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#define PSW t11.psw.b.l
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#define SP REGW(6)
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#define PC REGW(7)
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#define SPD REGD(6)
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#define PCD REGD(7)
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#define PSW psw.b.l
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@ -76,35 +64,35 @@ static int t11_ICount;
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*
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*************************************/
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INLINE int ROPCODE(void)
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INLINE int ROPCODE(t11_state *cpustate)
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{
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int val = memory_decrypted_read_word(t11.program, PC);
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PC += 2;
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int val = memory_decrypted_read_word(cpustate->program, cpustate->PC);
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cpustate->PC += 2;
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return val;
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}
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INLINE int RBYTE(int addr)
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INLINE int RBYTE(t11_state *cpustate, int addr)
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{
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return T11_RDMEM(addr);
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return T11_RDMEM(cpustate, addr);
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}
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INLINE void WBYTE(int addr, int data)
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INLINE void WBYTE(t11_state *cpustate, int addr, int data)
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{
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T11_WRMEM(addr, data);
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T11_WRMEM(cpustate, addr, data);
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}
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INLINE int RWORD(int addr)
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INLINE int RWORD(t11_state *cpustate, int addr)
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{
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return T11_RDMEM_WORD(addr & 0xfffe);
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return T11_RDMEM_WORD(cpustate, addr & 0xfffe);
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}
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INLINE void WWORD(int addr, int data)
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INLINE void WWORD(t11_state *cpustate, int addr, int data)
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{
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T11_WRMEM_WORD(addr & 0xfffe, data);
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T11_WRMEM_WORD(cpustate, addr & 0xfffe, data);
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}
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@ -115,17 +103,17 @@ INLINE void WWORD(int addr, int data)
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*
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*************************************/
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INLINE void PUSH(int val)
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INLINE void PUSH(t11_state *cpustate, int val)
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{
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SP -= 2;
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WWORD(SPD, val);
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cpustate->SP -= 2;
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WWORD(cpustate, cpustate->SPD, val);
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}
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INLINE int POP(void)
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INLINE int POP(t11_state *cpustate)
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{
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int result = RWORD(SPD);
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SP += 2;
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int result = RWORD(cpustate, cpustate->SPD);
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cpustate->SP += 2;
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return result;
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}
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@ -144,22 +132,22 @@ INLINE int POP(void)
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#define NFLAG 8
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/* extracts flags */
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#define GET_C (PSW & CFLAG)
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#define GET_V (PSW & VFLAG)
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#define GET_Z (PSW & ZFLAG)
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#define GET_N (PSW & NFLAG)
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#define GET_C (cpustate->PSW & CFLAG)
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#define GET_V (cpustate->PSW & VFLAG)
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#define GET_Z (cpustate->PSW & ZFLAG)
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#define GET_N (cpustate->PSW & NFLAG)
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/* clears flags */
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#define CLR_C (PSW &= ~CFLAG)
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#define CLR_V (PSW &= ~VFLAG)
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#define CLR_Z (PSW &= ~ZFLAG)
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#define CLR_N (PSW &= ~NFLAG)
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#define CLR_C (cpustate->PSW &= ~CFLAG)
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#define CLR_V (cpustate->PSW &= ~VFLAG)
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#define CLR_Z (cpustate->PSW &= ~ZFLAG)
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#define CLR_N (cpustate->PSW &= ~NFLAG)
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/* sets flags */
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#define SET_C (PSW |= CFLAG)
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#define SET_V (PSW |= VFLAG)
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#define SET_Z (PSW |= ZFLAG)
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#define SET_N (PSW |= NFLAG)
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#define SET_C (cpustate->PSW |= CFLAG)
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#define SET_V (cpustate->PSW |= VFLAG)
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#define SET_Z (cpustate->PSW |= ZFLAG)
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#define SET_N (cpustate->PSW |= NFLAG)
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@ -195,10 +183,10 @@ static const struct irq_table_entry irq_table[] =
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{ 7<<5, 0x60 }
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};
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static void t11_check_irqs(void)
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static void t11_check_irqs(t11_state *cpustate)
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{
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const struct irq_table_entry *irq = &irq_table[t11.irq_state & 15];
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int priority = PSW & 0xe0;
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const struct irq_table_entry *irq = &irq_table[cpustate->irq_state & 15];
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int priority = cpustate->PSW & 0xe0;
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/* compare the priority of the interrupt to the PSW */
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if (irq->priority > priority)
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@ -207,28 +195,28 @@ static void t11_check_irqs(void)
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int new_pc, new_psw;
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/* call the callback; if we don't get -1 back, use the return value as our vector */
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if (t11.irq_callback != NULL)
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if (cpustate->irq_callback != NULL)
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{
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int new_vector = (*t11.irq_callback)(t11.device, t11.irq_state & 15);
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int new_vector = (*cpustate->irq_callback)(cpustate->device, cpustate->irq_state & 15);
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if (new_vector != -1)
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vector = new_vector;
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}
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/* fetch the new PC and PSW from that vector */
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assert((vector & 3) == 0);
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new_pc = RWORD(vector);
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new_psw = RWORD(vector + 2);
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new_pc = RWORD(cpustate, vector);
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new_psw = RWORD(cpustate, vector + 2);
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/* push the old state, set the new one */
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PUSH(PSW);
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PUSH(PC);
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PCD = new_pc;
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PSW = new_psw;
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t11_check_irqs();
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PUSH(cpustate, cpustate->PSW);
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PUSH(cpustate, cpustate->PC);
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cpustate->PCD = new_pc;
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cpustate->PSW = new_psw;
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t11_check_irqs(cpustate);
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/* count cycles and clear the WAIT flag */
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t11.interrupt_cycles += 114;
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t11.wait_state = 0;
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cpustate->icount -= 114;
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cpustate->wait_state = 0;
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}
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}
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@ -256,8 +244,6 @@ static void t11_check_irqs(void)
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static CPU_GET_CONTEXT( t11 )
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{
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if (dst)
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*(t11_Regs *)dst = t11;
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}
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@ -270,9 +256,6 @@ static CPU_GET_CONTEXT( t11 )
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static CPU_SET_CONTEXT( t11 )
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{
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if (src)
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t11 = *(t11_Regs *)src;
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t11_check_irqs();
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}
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@ -291,33 +274,26 @@ static CPU_INIT( t11 )
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0x1000, 0x0000, 0xf600, 0xf400
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};
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const struct t11_setup *setup = device->static_config;
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t11_state *cpustate = device->token;
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t11.initial_pc = initial_pc[setup->mode >> 13];
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t11.irq_callback = irqcallback;
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t11.device = device;
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t11.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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cpustate->initial_pc = initial_pc[setup->mode >> 13];
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cpustate->irq_callback = irqcallback;
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cpustate->device = device;
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cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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state_save_register_item("t11", device->tag, 0, t11.ppc.w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[0].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[1].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[2].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[3].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[4].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[5].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[6].w.l);
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state_save_register_item("t11", device->tag, 0, t11.reg[7].w.l);
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state_save_register_item("t11", device->tag, 0, t11.psw.w.l);
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state_save_register_item("t11", device->tag, 0, t11.op);
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state_save_register_item("t11", device->tag, 0, t11.initial_pc);
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state_save_register_item("t11", device->tag, 0, t11.wait_state);
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state_save_register_item("t11", device->tag, 0, t11.irq_state);
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state_save_register_item("t11", device->tag, 0, t11.interrupt_cycles);
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}
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static CPU_EXIT( t11 )
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{
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/* nothing to do */
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state_save_register_item("t11", device->tag, 0, cpustate->ppc.w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[0].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[1].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[2].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[3].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[4].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[5].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[6].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->reg[7].w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->psw.w.l);
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state_save_register_item("t11", device->tag, 0, cpustate->initial_pc);
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state_save_register_item("t11", device->tag, 0, cpustate->wait_state);
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state_save_register_item("t11", device->tag, 0, cpustate->irq_state);
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}
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@ -330,28 +306,29 @@ static CPU_EXIT( t11 )
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static CPU_RESET( t11 )
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{
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t11_state *cpustate = device->token;
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/* initial SP is 376 octal, or 0xfe */
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SP = 0x00fe;
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cpustate->SP = 0x00fe;
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/* initial PC comes from the setup word */
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PC = t11.initial_pc;
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cpustate->PC = cpustate->initial_pc;
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/* PSW starts off at highest priority */
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PSW = 0xe0;
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cpustate->PSW = 0xe0;
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/* initialize the IRQ state */
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t11.irq_state = 0;
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cpustate->irq_state = 0;
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/* reset the remaining state */
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REGD(0) = 0;
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REGD(1) = 0;
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REGD(2) = 0;
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REGD(3) = 0;
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REGD(4) = 0;
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REGD(5) = 0;
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t11.ppc.d = 0;
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t11.wait_state = 0;
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t11.interrupt_cycles = 0;
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cpustate->REGD(0) = 0;
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cpustate->REGD(1) = 0;
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cpustate->REGD(2) = 0;
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cpustate->REGD(3) = 0;
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cpustate->REGD(4) = 0;
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cpustate->REGD(5) = 0;
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cpustate->ppc.d = 0;
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cpustate->wait_state = 0;
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}
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@ -362,16 +339,13 @@ static CPU_RESET( t11 )
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*
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*************************************/
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static void set_irq_line(int irqline, int state)
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static void set_irq_line(t11_state *cpustate, int irqline, int state)
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{
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/* set the appropriate bit */
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if (state == CLEAR_LINE)
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t11.irq_state &= ~(1 << irqline);
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cpustate->irq_state &= ~(1 << irqline);
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else
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t11.irq_state |= 1 << irqline;
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/* recheck for interrupts */
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t11_check_irqs();
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cpustate->irq_state |= 1 << irqline;
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}
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@ -384,33 +358,33 @@ static void set_irq_line(int irqline, int state)
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static CPU_EXECUTE( t11 )
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{
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t11_ICount = cycles;
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t11_ICount -= t11.interrupt_cycles;
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t11.interrupt_cycles = 0;
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t11_state *cpustate = device->token;
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if (t11.wait_state)
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cpustate->icount = cycles;
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t11_check_irqs(cpustate);
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if (cpustate->wait_state)
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{
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t11_ICount = 0;
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cpustate->icount = 0;
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goto getout;
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}
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do
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{
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t11.ppc = t11.reg[7]; /* copy PC to previous PC */
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UINT16 op;
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cpustate->ppc = cpustate->reg[7]; /* copy PC to previous PC */
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debugger_instruction_hook(device, PCD);
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debugger_instruction_hook(device, cpustate->PCD);
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t11.op = ROPCODE();
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(*opcode_table[t11.op >> 3])();
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op = ROPCODE(cpustate);
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(*opcode_table[op >> 3])(cpustate, op);
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} while (t11_ICount > 0);
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} while (cpustate->icount > 0);
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getout:
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t11_ICount -= t11.interrupt_cycles;
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t11.interrupt_cycles = 0;
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return cycles - t11_ICount;
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return cycles - cpustate->icount;
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}
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@ -421,25 +395,27 @@ getout:
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static CPU_SET_INFO( t11 )
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{
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t11_state *cpustate = device->token;
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switch (state)
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{
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/* --- the following bits of info are set as 64-bit signed integers --- */
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case CPUINFO_INT_INPUT_STATE + T11_IRQ0: set_irq_line(T11_IRQ0, info->i); break;
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case CPUINFO_INT_INPUT_STATE + T11_IRQ1: set_irq_line(T11_IRQ1, info->i); break;
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||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ2: set_irq_line(T11_IRQ2, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: set_irq_line(T11_IRQ3, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ0: set_irq_line(cpustate, T11_IRQ0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ1: set_irq_line(cpustate, T11_IRQ1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ2: set_irq_line(cpustate, T11_IRQ2, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: set_irq_line(cpustate, T11_IRQ3, info->i); break;
|
||||
|
||||
case CPUINFO_INT_PC:
|
||||
case CPUINFO_INT_REGISTER + T11_PC: PC = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_PC: cpustate->PC = info->i; break;
|
||||
case CPUINFO_INT_SP:
|
||||
case CPUINFO_INT_REGISTER + T11_SP: SP = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_PSW: PSW = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R0: REGW(0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R1: REGW(1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R2: REGW(2) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R3: REGW(3) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R4: REGW(4) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R5: REGW(5) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_SP: cpustate->SP = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_PSW: cpustate->PSW = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R0: cpustate->REGW(0) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R1: cpustate->REGW(1) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R2: cpustate->REGW(2) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R3: cpustate->REGW(3) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R4: cpustate->REGW(4) = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R5: cpustate->REGW(5) = info->i; break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -451,10 +427,12 @@ static CPU_SET_INFO( t11 )
|
||||
|
||||
CPU_GET_INFO( t11 )
|
||||
{
|
||||
t11_state *cpustate = (device != NULL) ? device->token : NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(t11); break;
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(t11_state); break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 4; break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = -1; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
|
||||
@ -475,36 +453,34 @@ CPU_GET_INFO( t11 )
|
||||
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
|
||||
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ0: info->i = (t11.irq_state & 1) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ1: info->i = (t11.irq_state & 2) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ2: info->i = (t11.irq_state & 4) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: info->i = (t11.irq_state & 8) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ0: info->i = (cpustate->irq_state & 1) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ1: info->i = (cpustate->irq_state & 2) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ2: info->i = (cpustate->irq_state & 4) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
case CPUINFO_INT_INPUT_STATE + T11_IRQ3: info->i = (cpustate->irq_state & 8) ? ASSERT_LINE : CLEAR_LINE; break;
|
||||
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = t11.ppc.w.l; break;
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc.w.l; break;
|
||||
|
||||
case CPUINFO_INT_PC:
|
||||
case CPUINFO_INT_REGISTER + T11_PC: info->i = PCD; break;
|
||||
case CPUINFO_INT_REGISTER + T11_PC: info->i = cpustate->PCD; break;
|
||||
case CPUINFO_INT_SP:
|
||||
case CPUINFO_INT_REGISTER + T11_SP: info->i = SPD; break;
|
||||
case CPUINFO_INT_REGISTER + T11_PSW: info->i = PSW; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R0: info->i = REGD(0); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R1: info->i = REGD(1); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R2: info->i = REGD(2); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R3: info->i = REGD(3); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R4: info->i = REGD(4); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R5: info->i = REGD(5); break;
|
||||
case CPUINFO_INT_REGISTER + T11_SP: info->i = cpustate->SPD; break;
|
||||
case CPUINFO_INT_REGISTER + T11_PSW: info->i = cpustate->PSW; break;
|
||||
case CPUINFO_INT_REGISTER + T11_R0: info->i = cpustate->REGD(0); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R1: info->i = cpustate->REGD(1); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R2: info->i = cpustate->REGD(2); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R3: info->i = cpustate->REGD(3); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R4: info->i = cpustate->REGD(4); break;
|
||||
case CPUINFO_INT_REGISTER + T11_R5: info->i = cpustate->REGD(5); break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(t11); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(t11); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(t11); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(t11); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(t11); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(t11); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(t11); break;
|
||||
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(t11); break;
|
||||
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(t11); break;
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(t11); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(t11); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &t11_ICount; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(t11); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "T11"); break;
|
||||
@ -515,24 +491,24 @@ CPU_GET_INFO( t11 )
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
||||
t11.psw.b.l & 0x80 ? '?':'.',
|
||||
t11.psw.b.l & 0x40 ? 'I':'.',
|
||||
t11.psw.b.l & 0x20 ? 'I':'.',
|
||||
t11.psw.b.l & 0x10 ? 'T':'.',
|
||||
t11.psw.b.l & 0x08 ? 'N':'.',
|
||||
t11.psw.b.l & 0x04 ? 'Z':'.',
|
||||
t11.psw.b.l & 0x02 ? 'V':'.',
|
||||
t11.psw.b.l & 0x01 ? 'C':'.');
|
||||
cpustate->psw.b.l & 0x80 ? '?':'.',
|
||||
cpustate->psw.b.l & 0x40 ? 'I':'.',
|
||||
cpustate->psw.b.l & 0x20 ? 'I':'.',
|
||||
cpustate->psw.b.l & 0x10 ? 'T':'.',
|
||||
cpustate->psw.b.l & 0x08 ? 'N':'.',
|
||||
cpustate->psw.b.l & 0x04 ? 'Z':'.',
|
||||
cpustate->psw.b.l & 0x02 ? 'V':'.',
|
||||
cpustate->psw.b.l & 0x01 ? 'C':'.');
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + T11_PC: sprintf(info->s, "PC:%04X", t11.reg[7].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_SP: sprintf(info->s, "SP:%04X", t11.reg[6].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_PSW: sprintf(info->s, "PSW:%02X", t11.psw.b.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R0: sprintf(info->s, "R0:%04X", t11.reg[0].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R1: sprintf(info->s, "R1:%04X", t11.reg[1].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R2: sprintf(info->s, "R2:%04X", t11.reg[2].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R3: sprintf(info->s, "R3:%04X", t11.reg[3].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R4: sprintf(info->s, "R4:%04X", t11.reg[4].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R5: sprintf(info->s, "R5:%04X", t11.reg[5].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_PC: sprintf(info->s, "PC:%04X", cpustate->reg[7].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_SP: sprintf(info->s, "SP:%04X", cpustate->reg[6].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_PSW: sprintf(info->s, "PSW:%02X", cpustate->psw.b.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R0: sprintf(info->s, "R0:%04X", cpustate->reg[0].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R1: sprintf(info->s, "R1:%04X", cpustate->reg[1].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R2: sprintf(info->s, "R2:%04X", cpustate->reg[2].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R3: sprintf(info->s, "R3:%04X", cpustate->reg[3].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R4: sprintf(info->s, "R4:%04X", cpustate->reg[4].w.l); break;
|
||||
case CPUINFO_STR_REGISTER + T11_R5: sprintf(info->s, "R5:%04X", cpustate->reg[5].w.l); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -38,14 +38,14 @@ extern CPU_GET_INFO( t11 );
|
||||
/****************************************************************************/
|
||||
/* Read a byte from given memory location */
|
||||
/****************************************************************************/
|
||||
#define T11_RDMEM(A) ((unsigned)memory_read_byte_16le(t11.program, A))
|
||||
#define T11_RDMEM_WORD(A) ((unsigned)memory_read_word_16le(t11.program, A))
|
||||
#define T11_RDMEM(T,A) ((unsigned)memory_read_byte_16le((T)->program, A))
|
||||
#define T11_RDMEM_WORD(T,A) ((unsigned)memory_read_word_16le((T)->program, A))
|
||||
|
||||
/****************************************************************************/
|
||||
/* Write a byte to given memory location */
|
||||
/****************************************************************************/
|
||||
#define T11_WRMEM(A,V) (memory_write_byte_16le(t11.program, A,V))
|
||||
#define T11_WRMEM_WORD(A,V) (memory_write_word_16le(t11.program, A,V))
|
||||
#define T11_WRMEM(T,A,V) (memory_write_byte_16le((T)->program, A,V))
|
||||
#define T11_WRMEM_WORD(T,A,V) (memory_write_word_16le((T)->program, A,V))
|
||||
|
||||
CPU_DISASSEMBLE( t11 );
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -149,14 +149,14 @@ static WRITE8_HANDLER( mux_select_w )
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static UINT8 joystick_read(void)
|
||||
static UINT8 joystick_read(const device_config *device)
|
||||
{
|
||||
if (mame_get_phase(Machine) != MAME_PHASE_RUNNING)
|
||||
if (mame_get_phase(device->machine) != MAME_PHASE_RUNNING)
|
||||
return 0;
|
||||
else
|
||||
{
|
||||
int xval = (INT16)(cpu_get_reg(Machine->cpu[0], CCPU_X) << 4) >> 4;
|
||||
return (input_port_read_safe(Machine, mux_select ? "ANALOGX" : "ANALOGY", 0) - xval) < 0x800;
|
||||
int xval = (INT16)(cpu_get_reg(device, CCPU_X) << 4) >> 4;
|
||||
return (input_port_read_safe(device->machine, mux_select ? "ANALOGX" : "ANALOGY", 0) - xval) < 0x800;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -34,8 +34,8 @@ MACHINE_DRIVER_EXTERN( qb3_sound );
|
||||
|
||||
/*----------- defined in video/cinemat.c -----------*/
|
||||
|
||||
void cinemat_vector_callback(INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift);
|
||||
WRITE8_HANDLER(cinemat_vector_control_w);
|
||||
void cinemat_vector_callback(const device_config *device, INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift);
|
||||
WRITE8_HANDLER( cinemat_vector_control_w );
|
||||
|
||||
VIDEO_START( cinemat_bilevel );
|
||||
VIDEO_START( cinemat_16level );
|
||||
|
||||
@ -47,9 +47,9 @@ static UINT8 last_control;
|
||||
*
|
||||
*************************************/
|
||||
|
||||
void cinemat_vector_callback(INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift)
|
||||
void cinemat_vector_callback(const device_config *device, INT16 sx, INT16 sy, INT16 ex, INT16 ey, UINT8 shift)
|
||||
{
|
||||
const rectangle *visarea = video_screen_get_visible_area(Machine->primary_screen);
|
||||
const rectangle *visarea = video_screen_get_visible_area(device->machine->primary_screen);
|
||||
int intensity = 0xff;
|
||||
|
||||
/* adjust for slop */
|
||||
@ -227,7 +227,7 @@ VIDEO_UPDATE( cinemat )
|
||||
vector_clear_list();
|
||||
|
||||
cpu_push_context(screen->machine->cpu[0]);
|
||||
ccpu_wdt_timer_trigger();
|
||||
ccpu_wdt_timer_trigger(screen->machine->cpu[0]);
|
||||
cpu_pop_context();
|
||||
|
||||
return 0;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user