mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
mc8030:don't write to regions; fk1: cleanup
This commit is contained in:
Robbbert
parent
b9ef046299
commit
de153ba412
@ -2,9 +2,9 @@
|
||||
// copyright-holders:Miodrag Milanovic
|
||||
/***************************************************************************
|
||||
|
||||
FK-1
|
||||
FK-1
|
||||
|
||||
12/05/2009 Skeleton driver.
|
||||
2009-05-12 Skeleton driver.
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
@ -22,52 +22,61 @@
|
||||
class fk1_state : public driver_device
|
||||
{
|
||||
public:
|
||||
fk1_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
driver_device(mconfig, type, tag),
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_ram(*this, RAM_TAG)
|
||||
fk1_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_rom(*this, "maincpu")
|
||||
, m_ram(*this, RAM_TAG)
|
||||
, m_bankr(*this, "bankr1")
|
||||
, m_bankw(*this, "bankw1")
|
||||
, m_bank2(*this, "bank2")
|
||||
{ }
|
||||
|
||||
void fk1(machine_config &config);
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ram_device> m_ram;
|
||||
|
||||
void fk1_ppi_1_a_w(uint8_t data);
|
||||
void fk1_ppi_1_b_w(uint8_t data);
|
||||
void fk1_ppi_1_c_w(uint8_t data);
|
||||
uint8_t fk1_ppi_1_a_r();
|
||||
uint8_t fk1_ppi_1_b_r();
|
||||
uint8_t fk1_ppi_1_c_r();
|
||||
void fk1_ppi_2_a_w(uint8_t data);
|
||||
void fk1_ppi_2_c_w(uint8_t data);
|
||||
uint8_t fk1_ppi_2_b_r();
|
||||
uint8_t fk1_ppi_2_c_r();
|
||||
void fk1_ppi_3_a_w(uint8_t data);
|
||||
void fk1_ppi_3_b_w(uint8_t data);
|
||||
void fk1_ppi_3_c_w(uint8_t data);
|
||||
uint8_t fk1_ppi_3_a_r();
|
||||
uint8_t fk1_ppi_3_b_r();
|
||||
uint8_t fk1_ppi_3_c_r();
|
||||
DECLARE_WRITE_LINE_MEMBER(fk1_pit_out0);
|
||||
DECLARE_WRITE_LINE_MEMBER(fk1_pit_out1);
|
||||
DECLARE_WRITE_LINE_MEMBER(fk1_pit_out2);
|
||||
void fk1_intr_w(uint8_t data);
|
||||
uint8_t fk1_bank_ram_r();
|
||||
uint8_t fk1_bank_rom_r();
|
||||
void fk1_disk_w(uint8_t data);
|
||||
uint8_t fk1_mouse_r();
|
||||
void fk1_reset_int_w(uint8_t data);
|
||||
void ppi1_a_w(uint8_t data);
|
||||
void ppi1_b_w(uint8_t data);
|
||||
void ppi1_c_w(uint8_t data);
|
||||
uint8_t ppi1_a_r();
|
||||
uint8_t ppi1_b_r();
|
||||
uint8_t ppi1_c_r();
|
||||
void ppi2_a_w(uint8_t data);
|
||||
void ppi2_c_w(uint8_t data);
|
||||
uint8_t ppi2_b_r();
|
||||
uint8_t ppi2_c_r();
|
||||
void ppi3_a_w(uint8_t data);
|
||||
void ppi3_b_w(uint8_t data);
|
||||
void ppi3_c_w(uint8_t data);
|
||||
uint8_t ppi3_a_r();
|
||||
uint8_t ppi3_b_r();
|
||||
uint8_t ppi3_c_r();
|
||||
DECLARE_WRITE_LINE_MEMBER(pit_out0);
|
||||
DECLARE_WRITE_LINE_MEMBER(pit_out1);
|
||||
DECLARE_WRITE_LINE_MEMBER(pit_out2);
|
||||
void intr_w(uint8_t data);
|
||||
uint8_t bank_ram_r();
|
||||
uint8_t bank_rom_r();
|
||||
void disk_w(uint8_t data);
|
||||
uint8_t mouse_r();
|
||||
void reset_int_w(uint8_t data);
|
||||
uint8_t m_video_rol;
|
||||
uint8_t m_int_vector;
|
||||
virtual void machine_reset() override;
|
||||
void machine_start() override;
|
||||
void machine_reset() override;
|
||||
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(keyboard_callback);
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(vsync_callback);
|
||||
IRQ_CALLBACK_MEMBER(fk1_irq_callback);
|
||||
void fk1_io(address_map &map);
|
||||
void fk1_mem(address_map &map);
|
||||
IRQ_CALLBACK_MEMBER(irq_callback);
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_region_ptr<u8> m_rom;
|
||||
required_device<ram_device> m_ram;
|
||||
required_memory_bank m_bankr;
|
||||
required_memory_bank m_bankw;
|
||||
required_memory_bank m_bank2;
|
||||
};
|
||||
|
||||
|
||||
@ -91,34 +100,34 @@ Port C:
|
||||
2 - INTE keyboard
|
||||
*/
|
||||
|
||||
void fk1_state::fk1_ppi_1_a_w(uint8_t data)
|
||||
void fk1_state::ppi1_a_w(uint8_t data)
|
||||
{
|
||||
// logerror("fk1_ppi_1_a_w %02x\n",data);
|
||||
}
|
||||
|
||||
void fk1_state::fk1_ppi_1_b_w(uint8_t data)
|
||||
void fk1_state::ppi1_b_w(uint8_t data)
|
||||
{
|
||||
// logerror("fk1_ppi_1_b_w %02x\n",data);
|
||||
}
|
||||
|
||||
void fk1_state::fk1_ppi_1_c_w(uint8_t data)
|
||||
void fk1_state::ppi1_c_w(uint8_t data)
|
||||
{
|
||||
//logerror("fk1_ppi_1_c_w %02x\n",data);
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_1_a_r()
|
||||
uint8_t fk1_state::ppi1_a_r()
|
||||
{
|
||||
//logerror("fk1_ppi_1_a_r\n");
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_1_b_r()
|
||||
uint8_t fk1_state::ppi1_b_r()
|
||||
{
|
||||
// logerror("fk1_ppi_1_b_r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_1_c_r()
|
||||
uint8_t fk1_state::ppi1_c_r()
|
||||
{
|
||||
// logerror("fk1_ppi_1_c_r\n");
|
||||
return 0;
|
||||
@ -145,23 +154,23 @@ Port C:
|
||||
2 - INTE B - writing data
|
||||
*/
|
||||
|
||||
void fk1_state::fk1_ppi_2_a_w(uint8_t data)
|
||||
void fk1_state::ppi2_a_w(uint8_t data)
|
||||
{
|
||||
// logerror("write to disk %02x\n",data);
|
||||
}
|
||||
|
||||
void fk1_state::fk1_ppi_2_c_w(uint8_t data)
|
||||
void fk1_state::ppi2_c_w(uint8_t data)
|
||||
{
|
||||
// logerror("fk1_ppi_2_c_w %02x\n",data);
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_2_b_r()
|
||||
uint8_t fk1_state::ppi2_b_r()
|
||||
{
|
||||
// logerror("read from disk\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_2_c_r()
|
||||
uint8_t fk1_state::ppi2_c_r()
|
||||
{
|
||||
// logerror("fk1_ppi_2_c_r\n");
|
||||
return 0;
|
||||
@ -193,51 +202,51 @@ Port C
|
||||
0 - STEP, move disk (0 1 .. 0.).
|
||||
|
||||
*/
|
||||
void fk1_state::fk1_ppi_3_a_w(uint8_t data)
|
||||
void fk1_state::ppi3_a_w(uint8_t data)
|
||||
{
|
||||
// logerror("fk1_ppi_3_a_w %02x\n",data);
|
||||
}
|
||||
|
||||
void fk1_state::fk1_ppi_3_b_w(uint8_t data)
|
||||
void fk1_state::ppi3_b_w(uint8_t data)
|
||||
{
|
||||
m_video_rol = data;
|
||||
}
|
||||
|
||||
void fk1_state::fk1_ppi_3_c_w(uint8_t data)
|
||||
void fk1_state::ppi3_c_w(uint8_t data)
|
||||
{
|
||||
// logerror("fk1_ppi_3_c_w %02x\n",data);
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_3_a_r()
|
||||
uint8_t fk1_state::ppi3_a_r()
|
||||
{
|
||||
// logerror("fk1_ppi_3_a_r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_3_b_r()
|
||||
uint8_t fk1_state::ppi3_b_r()
|
||||
{
|
||||
return m_video_rol;
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_ppi_3_c_r()
|
||||
uint8_t fk1_state::ppi3_c_r()
|
||||
{
|
||||
// logerror("fk1_ppi_3_c_r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( fk1_state::fk1_pit_out0 )
|
||||
WRITE_LINE_MEMBER( fk1_state::pit_out0 )
|
||||
{
|
||||
// System time
|
||||
logerror("WRITE_LINE_MEMBER(fk1_pit_out0)\n");
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( fk1_state::fk1_pit_out1 )
|
||||
WRITE_LINE_MEMBER( fk1_state::pit_out1 )
|
||||
{
|
||||
// Timeout for disk operation
|
||||
logerror("WRITE_LINE_MEMBER(fk1_pit_out1)\n");
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER( fk1_state::fk1_pit_out2 )
|
||||
WRITE_LINE_MEMBER( fk1_state::pit_out2 )
|
||||
{
|
||||
// Overflow for disk operations
|
||||
logerror("WRITE_LINE_MEMBER(fk1_pit_out2)\n");
|
||||
@ -250,28 +259,22 @@ WRITE_LINE_MEMBER( fk1_state::fk1_pit_out2 )
|
||||
8 any interruption allowed.
|
||||
*/
|
||||
|
||||
void fk1_state::fk1_intr_w(uint8_t data)
|
||||
void fk1_state::intr_w(uint8_t data)
|
||||
{
|
||||
logerror("fk1_intr_w %02x\n",data);
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_bank_ram_r()
|
||||
uint8_t fk1_state::bank_ram_r()
|
||||
{
|
||||
address_space &space_mem = m_maincpu->space(AS_PROGRAM);
|
||||
uint8_t *ram = m_ram->pointer();
|
||||
|
||||
space_mem.install_write_bank(0x0000, 0x3fff, "bank1");
|
||||
membank("bank1")->set_base(ram);
|
||||
membank("bank2")->set_base(ram + 0x4000);
|
||||
m_bankr->set_entry(0);
|
||||
m_bank2->set_entry(0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
uint8_t fk1_state::fk1_bank_rom_r()
|
||||
uint8_t fk1_state::bank_rom_r()
|
||||
{
|
||||
address_space &space_mem = m_maincpu->space(AS_PROGRAM);
|
||||
space_mem.unmap_write(0x0000, 0x3fff);
|
||||
membank("bank1")->set_base(memregion("maincpu")->base());
|
||||
membank("bank2")->set_base(m_ram->pointer() + 0x10000);
|
||||
m_bankr->set_entry(1);
|
||||
m_bank2->set_entry(1);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -284,7 +287,7 @@ uint8_t fk1_state::fk1_bank_rom_r()
|
||||
Functions are allowed in one.
|
||||
*/
|
||||
|
||||
void fk1_state::fk1_disk_w(uint8_t data)
|
||||
void fk1_state::disk_w(uint8_t data)
|
||||
{
|
||||
// logerror("fk1_disk_w %02x\n",data);
|
||||
}
|
||||
@ -299,7 +302,7 @@ void fk1_state::fk1_disk_w(uint8_t data)
|
||||
0 - / AX, X-axis
|
||||
*/
|
||||
|
||||
uint8_t fk1_state::fk1_mouse_r()
|
||||
uint8_t fk1_state::mouse_r()
|
||||
{
|
||||
// logerror("fk1_mouse_r\n");
|
||||
return 0;
|
||||
@ -307,31 +310,31 @@ uint8_t fk1_state::fk1_mouse_r()
|
||||
|
||||
/*Write to port 70 resets the interrupt from the system clock of 50 Hz. */
|
||||
|
||||
void fk1_state::fk1_reset_int_w(uint8_t data)
|
||||
void fk1_state::reset_int_w(uint8_t data)
|
||||
{
|
||||
logerror("fk1_reset_int_w\n");
|
||||
}
|
||||
|
||||
void fk1_state::fk1_mem(address_map &map)
|
||||
void fk1_state::mem_map(address_map &map)
|
||||
{
|
||||
map(0x0000, 0x3fff).bankrw("bank1");
|
||||
map(0x0000, 0x3fff).bankr("bankr1").bankw("bankw1");
|
||||
map(0x4000, 0x7fff).bankrw("bank2");
|
||||
map(0x8000, 0xbfff).bankrw("bank3");
|
||||
map(0xc000, 0xffff).bankrw("bank4");
|
||||
map(0x8000, 0xbfff).ram();
|
||||
map(0xc000, 0xffff).ram();
|
||||
}
|
||||
|
||||
void fk1_state::fk1_io(address_map &map)
|
||||
void fk1_state::io_map(address_map &map)
|
||||
{
|
||||
map.global_mask(0xff);
|
||||
map.unmap_value_high();
|
||||
map(0x00, 0x03).rw("ppi8255_1", FUNC(i8255_device::read), FUNC(i8255_device::write));
|
||||
map(0x10, 0x13).rw("pit8253", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
|
||||
map(0x20, 0x23).rw("ppi8255_2", FUNC(i8255_device::read), FUNC(i8255_device::write));
|
||||
map(0x30, 0x30).rw(FUNC(fk1_state::fk1_bank_ram_r), FUNC(fk1_state::fk1_intr_w));
|
||||
map(0x00, 0x03).rw("ppi1", FUNC(i8255_device::read), FUNC(i8255_device::write));
|
||||
map(0x10, 0x13).rw("pit", FUNC(pit8253_device::read), FUNC(pit8253_device::write));
|
||||
map(0x20, 0x23).rw("ppi2", FUNC(i8255_device::read), FUNC(i8255_device::write));
|
||||
map(0x30, 0x30).rw(FUNC(fk1_state::bank_ram_r), FUNC(fk1_state::intr_w));
|
||||
map(0x40, 0x41).rw("uart", FUNC(i8251_device::read), FUNC(i8251_device::write));
|
||||
map(0x50, 0x50).rw(FUNC(fk1_state::fk1_bank_rom_r), FUNC(fk1_state::fk1_disk_w));
|
||||
map(0x60, 0x63).rw("ppi8255_3", FUNC(i8255_device::read), FUNC(i8255_device::write));
|
||||
map(0x70, 0x70).rw(FUNC(fk1_state::fk1_mouse_r), FUNC(fk1_state::fk1_reset_int_w));
|
||||
map(0x50, 0x50).rw(FUNC(fk1_state::bank_rom_r), FUNC(fk1_state::disk_w));
|
||||
map(0x60, 0x63).rw("ppi3", FUNC(i8255_device::read), FUNC(i8255_device::write));
|
||||
map(0x70, 0x70).rw(FUNC(fk1_state::mouse_r), FUNC(fk1_state::reset_int_w));
|
||||
}
|
||||
|
||||
/* Input ports */
|
||||
@ -367,7 +370,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(fk1_state::keyboard_callback)
|
||||
0 ? PRINTER
|
||||
*/
|
||||
|
||||
IRQ_CALLBACK_MEMBER(fk1_state::fk1_irq_callback)
|
||||
IRQ_CALLBACK_MEMBER(fk1_state::irq_callback)
|
||||
{
|
||||
logerror("IRQ %02x\n", m_int_vector*2);
|
||||
return m_int_vector * 2;
|
||||
@ -380,16 +383,23 @@ TIMER_DEVICE_CALLBACK_MEMBER(fk1_state::vsync_callback)
|
||||
}
|
||||
|
||||
|
||||
void fk1_state::machine_start()
|
||||
{
|
||||
save_item(NAME(m_video_rol));
|
||||
save_item(NAME(m_int_vector));
|
||||
u8 *r = m_ram->pointer();
|
||||
m_bankr->configure_entry(0, r);
|
||||
m_bankr->configure_entry(1, m_rom);
|
||||
m_bankw->configure_entry(0, r);
|
||||
m_bank2->configure_entry(0, r+0x4000);
|
||||
m_bank2->configure_entry(1, r+0x8000);
|
||||
}
|
||||
|
||||
void fk1_state::machine_reset()
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
uint8_t *ram = m_ram->pointer();
|
||||
|
||||
space.unmap_write(0x0000, 0x3fff);
|
||||
membank("bank1")->set_base(memregion("maincpu")->base()); // ROM
|
||||
membank("bank2")->set_base(ram + 0x10000); // VRAM
|
||||
membank("bank3")->set_base(ram + 0x8000);
|
||||
membank("bank4")->set_base(ram + 0xc000);
|
||||
m_bankr->set_entry(1);
|
||||
m_bankw->set_entry(0);
|
||||
m_bank2->set_entry(1);
|
||||
}
|
||||
|
||||
uint32_t fk1_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
@ -402,11 +412,9 @@ uint32_t fk1_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, c
|
||||
{
|
||||
for (y = 0; y < 256; y++)
|
||||
{
|
||||
code = ram[x * 0x100 + ((y + m_video_rol) & 0xff) + 0x10000];
|
||||
code = ram[x * 0x100 + ((y + m_video_rol) & 0xff) + 0x8000];
|
||||
for (b = 0; b < 8; b++)
|
||||
{
|
||||
bitmap.pix16(y, x*8+b) = ((code << b) & 0x80) ? 1 : 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
@ -416,9 +424,9 @@ void fk1_state::fk1(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
Z80(config, m_maincpu, XTAL(8'000'000) / 2);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &fk1_state::fk1_mem);
|
||||
m_maincpu->set_addrmap(AS_IO, &fk1_state::fk1_io);
|
||||
m_maincpu->set_irq_acknowledge_callback(FUNC(fk1_state::fk1_irq_callback));
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &fk1_state::mem_map);
|
||||
m_maincpu->set_addrmap(AS_IO, &fk1_state::io_map);
|
||||
m_maincpu->set_irq_acknowledge_callback(FUNC(fk1_state::irq_callback));
|
||||
|
||||
/* video hardware */
|
||||
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER, rgb_t::green()));
|
||||
@ -431,49 +439,49 @@ void fk1_state::fk1(machine_config &config)
|
||||
|
||||
PALETTE(config, "palette", palette_device::MONOCHROME);
|
||||
|
||||
pit8253_device &pit8253(PIT8253(config, "pit8253", 0));
|
||||
pit8253_device &pit8253(PIT8253(config, "pit", 0));
|
||||
pit8253.set_clk<0>(50);
|
||||
pit8253.out_handler<0>().set(FUNC(fk1_state::fk1_pit_out0));
|
||||
pit8253.out_handler<0>().set(FUNC(fk1_state::pit_out0));
|
||||
pit8253.set_clk<1>(1000000);
|
||||
pit8253.out_handler<1>().set(FUNC(fk1_state::fk1_pit_out1));
|
||||
pit8253.out_handler<1>().set(FUNC(fk1_state::pit_out1));
|
||||
pit8253.set_clk<2>(0);
|
||||
pit8253.out_handler<2>().set(FUNC(fk1_state::fk1_pit_out2));
|
||||
pit8253.out_handler<2>().set(FUNC(fk1_state::pit_out2));
|
||||
|
||||
i8255_device &ppi1(I8255(config, "ppi8255_1"));
|
||||
ppi1.in_pa_callback().set(FUNC(fk1_state::fk1_ppi_1_a_r));
|
||||
ppi1.out_pa_callback().set(FUNC(fk1_state::fk1_ppi_1_a_w));
|
||||
ppi1.in_pb_callback().set(FUNC(fk1_state::fk1_ppi_1_b_r));
|
||||
ppi1.out_pb_callback().set(FUNC(fk1_state::fk1_ppi_1_b_w));
|
||||
ppi1.in_pc_callback().set(FUNC(fk1_state::fk1_ppi_1_c_r));
|
||||
ppi1.out_pc_callback().set(FUNC(fk1_state::fk1_ppi_1_c_w));
|
||||
i8255_device &ppi1(I8255(config, "ppi1"));
|
||||
ppi1.in_pa_callback().set(FUNC(fk1_state::ppi1_a_r));
|
||||
ppi1.out_pa_callback().set(FUNC(fk1_state::ppi1_a_w));
|
||||
ppi1.in_pb_callback().set(FUNC(fk1_state::ppi1_b_r));
|
||||
ppi1.out_pb_callback().set(FUNC(fk1_state::ppi1_b_w));
|
||||
ppi1.in_pc_callback().set(FUNC(fk1_state::ppi1_c_r));
|
||||
ppi1.out_pc_callback().set(FUNC(fk1_state::ppi1_c_w));
|
||||
|
||||
i8255_device &ppi2(I8255(config, "ppi8255_2"));
|
||||
ppi2.out_pa_callback().set(FUNC(fk1_state::fk1_ppi_2_a_w));
|
||||
ppi2.in_pb_callback().set(FUNC(fk1_state::fk1_ppi_2_b_r));
|
||||
ppi2.in_pc_callback().set(FUNC(fk1_state::fk1_ppi_2_c_r));
|
||||
ppi2.out_pc_callback().set(FUNC(fk1_state::fk1_ppi_2_c_w));
|
||||
i8255_device &ppi2(I8255(config, "ppi2"));
|
||||
ppi2.out_pa_callback().set(FUNC(fk1_state::ppi2_a_w));
|
||||
ppi2.in_pb_callback().set(FUNC(fk1_state::ppi2_b_r));
|
||||
ppi2.in_pc_callback().set(FUNC(fk1_state::ppi2_c_r));
|
||||
ppi2.out_pc_callback().set(FUNC(fk1_state::ppi2_c_w));
|
||||
|
||||
i8255_device &ppi3(I8255(config, "ppi8255_3"));
|
||||
ppi3.in_pa_callback().set(FUNC(fk1_state::fk1_ppi_3_a_r));
|
||||
ppi3.out_pa_callback().set(FUNC(fk1_state::fk1_ppi_3_a_w));
|
||||
ppi3.in_pb_callback().set(FUNC(fk1_state::fk1_ppi_3_b_r));
|
||||
ppi3.out_pb_callback().set(FUNC(fk1_state::fk1_ppi_3_b_w));
|
||||
ppi3.in_pc_callback().set(FUNC(fk1_state::fk1_ppi_3_c_r));
|
||||
ppi3.out_pc_callback().set(FUNC(fk1_state::fk1_ppi_3_c_w));
|
||||
i8255_device &ppi3(I8255(config, "ppi3"));
|
||||
ppi3.in_pa_callback().set(FUNC(fk1_state::ppi3_a_r));
|
||||
ppi3.out_pa_callback().set(FUNC(fk1_state::ppi3_a_w));
|
||||
ppi3.in_pb_callback().set(FUNC(fk1_state::ppi3_b_r));
|
||||
ppi3.out_pb_callback().set(FUNC(fk1_state::ppi3_b_w));
|
||||
ppi3.in_pc_callback().set(FUNC(fk1_state::ppi3_c_r));
|
||||
ppi3.out_pc_callback().set(FUNC(fk1_state::ppi3_c_w));
|
||||
|
||||
/* uart */
|
||||
I8251(config, "uart", 0);
|
||||
|
||||
/* internal ram */
|
||||
RAM(config, RAM_TAG).set_default_size("80K"); // 64 + 16
|
||||
RAM(config, RAM_TAG).set_default_size("48K"); // 32 for banks1,2 + 16 for vram
|
||||
|
||||
TIMER(config, "keyboard_timer").configure_periodic(FUNC(fk1_state::keyboard_callback), attotime::from_hz(24000));
|
||||
TIMER(config, "keyboard_timer").configure_periodic(FUNC(fk1_state::keyboard_callback), attotime::from_hz(300));
|
||||
TIMER(config, "vsync_timer").configure_periodic(FUNC(fk1_state::vsync_callback), attotime::from_hz(50));
|
||||
}
|
||||
|
||||
/* ROM definition */
|
||||
ROM_START( fk1 )
|
||||
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
|
||||
ROM_REGION( 0x4000, "maincpu", ROMREGION_ERASEFF )
|
||||
ROM_SYSTEM_BIOS( 0, "orig", "Original BIOS" )
|
||||
ROMX_LOAD( "fk1.u65", 0x0000, 0x0800, CRC(145561f8) SHA1(a4eb17d773e51b34620c508b6cebcb4531ae99c2), ROM_BIOS(0))
|
||||
ROM_SYSTEM_BIOS( 1, "diag", "Diag BIOS" )
|
||||
@ -483,4 +491,4 @@ ROM_END
|
||||
/* Driver */
|
||||
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1989, fk1, 0, 0, fk1, fk1, fk1_state, empty_init, "Statni statek Klicany", "FK-1", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
COMP( 1989, fk1, 0, 0, fk1, fk1, fk1_state, empty_init, "Statni statek Klicany", "FK-1", MACHINE_NOT_WORKING | MACHINE_NO_SOUND | MACHINE_SUPPORTS_SAVE )
|
||||
|
||||
@ -34,7 +34,6 @@ class mc8030_state : public driver_device
|
||||
public:
|
||||
mc8030_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_p_videoram(*this, "vram")
|
||||
, m_maincpu(*this, "maincpu")
|
||||
{ }
|
||||
|
||||
@ -52,12 +51,13 @@ private:
|
||||
uint8_t asp_port_b_r();
|
||||
void asp_port_a_w(uint8_t data);
|
||||
void asp_port_b_w(uint8_t data);
|
||||
void machine_start() override;
|
||||
uint32_t screen_update_mc8030(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
|
||||
|
||||
void io_map(address_map &map);
|
||||
void mem_map(address_map &map);
|
||||
|
||||
required_region_ptr<uint8_t> m_p_videoram;
|
||||
std::unique_ptr<u8[]> m_vram;
|
||||
required_device<z80_device> m_maincpu;
|
||||
};
|
||||
|
||||
@ -113,9 +113,9 @@ void mc8030_state::vis_w(offs_t offset, uint8_t data)
|
||||
uint16_t addr = ((offset & 0xff00) >> 2) | ((offset & 0x08) << 2) | (data >> 3);
|
||||
uint8_t c = 1 << (data & 7);
|
||||
if (BIT(offset, 0))
|
||||
m_p_videoram[addr] |= c;
|
||||
m_vram[addr] |= c;
|
||||
else
|
||||
m_p_videoram[addr] &= ~c;
|
||||
m_vram[addr] &= ~c;
|
||||
}
|
||||
|
||||
void mc8030_state::eprom_prog_w(uint8_t data)
|
||||
@ -154,7 +154,7 @@ uint32_t mc8030_state::screen_update_mc8030(screen_device &screen, bitmap_ind16
|
||||
{
|
||||
for (x = ma; x < ma + 64; x++)
|
||||
{
|
||||
gfx = m_p_videoram[x^0x3fff];
|
||||
gfx = m_vram[x^0x3fff];
|
||||
|
||||
/* Display a scanline of a character */
|
||||
*p++ = BIT(gfx, 7);
|
||||
@ -183,6 +183,11 @@ static const z80_daisy_config daisy_chain[] =
|
||||
{ nullptr }
|
||||
};
|
||||
|
||||
void mc8030_state::machine_start()
|
||||
{
|
||||
m_vram = make_unique_clear<u8[]>(0x4000);
|
||||
save_pointer(NAME(m_vram), 0x4000);
|
||||
}
|
||||
|
||||
void mc8030_state::mc8030(machine_config &config)
|
||||
{
|
||||
@ -253,8 +258,6 @@ ROM_START( mc8030 )
|
||||
ROM_LOAD( "spe_1.rom", 0x2000, 0x0400, CRC(826f609c) SHA1(e77ff6c180f5a6d7756d076173ae264a0e26f066))
|
||||
ROM_LOAD( "spe_2.rom", 0x2400, 0x0400, CRC(98320040) SHA1(6baf87e196f1ccdf44912deafa6042becbfb0679))
|
||||
|
||||
ROM_REGION( 0x4000, "vram", ROMREGION_ERASE00 )
|
||||
|
||||
ROM_REGION( 0x4000, "user1", 0 )
|
||||
// marked as "80.3x"
|
||||
ROM_LOAD( "mc80.3-x-2c00-c63c.bin", 0x2c00, 0x0400, CRC(469be754) SHA1(a7fea257a1c0970349f75504c0870a2649b50303) )
|
||||
|
||||
Loading…
Reference in New Issue
Block a user