i386: preliminary cpu-side smi support (nw)
This commit is contained in:
cracyc
parent
74b1a0a00b
commit
de38e289c9
@ -136,7 +136,7 @@ static void i386_load_segment_descriptor(i386_state *cpustate, int segment )
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{
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cpustate->sreg[segment].base = cpustate->sreg[segment].selector << 4;
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cpustate->sreg[segment].limit = 0xffff;
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cpustate->sreg[segment].flags = (segment == CS) ? 0x009a : 0x0092;
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cpustate->sreg[segment].flags = (segment == CS) ? 0x00fb : 0x00f3;
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cpustate->sreg[segment].d = 0;
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cpustate->sreg[segment].valid = true;
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}
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@ -3069,7 +3069,18 @@ static void i386_common_init(legacy_cpu_device *device, device_irq_acknowledge_c
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device->save_item(NAME(cpustate->irq_state));
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device->save_item(NAME(cpustate->performed_intersegment_jump));
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device->save_item(NAME(cpustate->mxcsr));
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device->save_item(NAME(cpustate->smm));
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device->save_item(NAME(cpustate->nmi_masked));
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device->save_item(NAME(cpustate->nmi_latched));
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device->save_item(NAME(cpustate->smbase));
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device->machine().save().register_postload(save_prepost_delegate(FUNC(i386_postload), cpustate));
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i386_interface *intf = (i386_interface *) device->static_config();
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if (intf != NULL)
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cpustate->smiact.resolve(intf->smiact, *device);
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else
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memset(&cpustate->smiact, 0, sizeof(cpustate->smiact));
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}
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CPU_INIT( i386 )
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@ -3159,6 +3170,9 @@ static CPU_RESET( i386 )
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cpustate->idtr.base = 0;
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cpustate->idtr.limit = 0x3ff;
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cpustate->smm = false;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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cpustate->a20_mask = ~0;
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@ -3183,6 +3197,94 @@ static CPU_RESET( i386 )
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CHANGE_PC(cpustate,cpustate->eip);
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}
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static void pentium_smi(i386_state *cpustate)
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{
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UINT32 smram_state = cpustate->smbase + 0xfe00;
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UINT32 old_cr0 = cpustate->cr[0];
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UINT32 old_flags = get_flags(cpustate);
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if(cpustate->smm)
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return; // TODO: latch
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cpustate->cr[0] &= ~(0x8000000d);
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set_flags(cpustate, 2);
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if(!cpustate->smiact.isnull())
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cpustate->smiact(true);
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cpustate->smm = true;
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// save state
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WRITE32(cpustate, cpustate->cr[4], smram_state+SMRAM_IP5_CR4);
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WRITE32(cpustate, cpustate->sreg[ES].limit, smram_state+SMRAM_IP5_ESLIM);
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WRITE32(cpustate, cpustate->sreg[ES].base, smram_state+SMRAM_IP5_ESBASE);
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WRITE32(cpustate, cpustate->sreg[ES].flags, smram_state+SMRAM_IP5_ESACC);
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WRITE32(cpustate, cpustate->sreg[CS].limit, smram_state+SMRAM_IP5_CSLIM);
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WRITE32(cpustate, cpustate->sreg[CS].base, smram_state+SMRAM_IP5_CSBASE);
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WRITE32(cpustate, cpustate->sreg[CS].flags, smram_state+SMRAM_IP5_CSACC);
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WRITE32(cpustate, cpustate->sreg[SS].limit, smram_state+SMRAM_IP5_SSLIM);
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WRITE32(cpustate, cpustate->sreg[SS].base, smram_state+SMRAM_IP5_SSBASE);
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WRITE32(cpustate, cpustate->sreg[SS].flags, smram_state+SMRAM_IP5_SSACC);
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WRITE32(cpustate, cpustate->sreg[DS].limit, smram_state+SMRAM_IP5_DSLIM);
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WRITE32(cpustate, cpustate->sreg[DS].base, smram_state+SMRAM_IP5_DSBASE);
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WRITE32(cpustate, cpustate->sreg[DS].flags, smram_state+SMRAM_IP5_DSACC);
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WRITE32(cpustate, cpustate->sreg[FS].limit, smram_state+SMRAM_IP5_FSLIM);
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WRITE32(cpustate, cpustate->sreg[FS].base, smram_state+SMRAM_IP5_FSBASE);
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WRITE32(cpustate, cpustate->sreg[FS].flags, smram_state+SMRAM_IP5_FSACC);
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WRITE32(cpustate, cpustate->sreg[GS].limit, smram_state+SMRAM_IP5_GSLIM);
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WRITE32(cpustate, cpustate->sreg[GS].base, smram_state+SMRAM_IP5_GSBASE);
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WRITE32(cpustate, cpustate->sreg[GS].flags, smram_state+SMRAM_IP5_GSACC);
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WRITE32(cpustate, cpustate->ldtr.flags, smram_state+SMRAM_IP5_LDTACC);
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WRITE32(cpustate, cpustate->ldtr.limit, smram_state+SMRAM_IP5_LDTLIM);
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WRITE32(cpustate, cpustate->ldtr.base, smram_state+SMRAM_IP5_LDTBASE);
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WRITE32(cpustate, cpustate->gdtr.limit, smram_state+SMRAM_IP5_GDTLIM);
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WRITE32(cpustate, cpustate->gdtr.base, smram_state+SMRAM_IP5_GDTBASE);
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WRITE32(cpustate, cpustate->idtr.limit, smram_state+SMRAM_IP5_IDTLIM);
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WRITE32(cpustate, cpustate->idtr.base, smram_state+SMRAM_IP5_IDTBASE);
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WRITE32(cpustate, cpustate->task.limit, smram_state+SMRAM_IP5_TRLIM);
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WRITE32(cpustate, cpustate->task.base, smram_state+SMRAM_IP5_TRBASE);
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WRITE32(cpustate, cpustate->task.flags, smram_state+SMRAM_IP5_TRACC);
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WRITE32(cpustate, cpustate->sreg[ES].selector, smram_state+SMRAM_ES);
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WRITE32(cpustate, cpustate->sreg[CS].selector, smram_state+SMRAM_CS);
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WRITE32(cpustate, cpustate->sreg[SS].selector, smram_state+SMRAM_SS);
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WRITE32(cpustate, cpustate->sreg[DS].selector, smram_state+SMRAM_DS);
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WRITE32(cpustate, cpustate->sreg[FS].selector, smram_state+SMRAM_FS);
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WRITE32(cpustate, cpustate->sreg[GS].selector, smram_state+SMRAM_GS);
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WRITE32(cpustate, cpustate->ldtr.segment, smram_state+SMRAM_LDTR);
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WRITE32(cpustate, cpustate->task.segment, smram_state+SMRAM_TR);
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WRITE32(cpustate, cpustate->dr[7], smram_state+SMRAM_DR7);
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WRITE32(cpustate, cpustate->dr[6], smram_state+SMRAM_DR6);
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WRITE32(cpustate, REG32(EAX), smram_state+SMRAM_EAX);
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WRITE32(cpustate, REG32(ECX), smram_state+SMRAM_ECX);
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WRITE32(cpustate, REG32(EDX), smram_state+SMRAM_EDX);
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WRITE32(cpustate, REG32(EBX), smram_state+SMRAM_EBX);
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WRITE32(cpustate, REG32(ESP), smram_state+SMRAM_ESP);
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WRITE32(cpustate, REG32(EBP), smram_state+SMRAM_EBP);
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WRITE32(cpustate, REG32(ESI), smram_state+SMRAM_ESI);
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WRITE32(cpustate, REG32(EDI), smram_state+SMRAM_EDI);
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WRITE32(cpustate, cpustate->eip, smram_state+SMRAM_EIP);
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WRITE32(cpustate, old_flags, smram_state+SMRAM_EAX);
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WRITE32(cpustate, cpustate->cr[3], smram_state+SMRAM_CR3);
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WRITE32(cpustate, old_cr0, smram_state+SMRAM_CR0);
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cpustate->sreg[DS].selector = cpustate->sreg[ES].selector = cpustate->sreg[FS].selector = cpustate->sreg[GS].selector = cpustate->sreg[SS].selector = 0;
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cpustate->sreg[DS].base = cpustate->sreg[ES].base = cpustate->sreg[FS].base = cpustate->sreg[GS].base = cpustate->sreg[SS].base = 0x00000000;
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cpustate->sreg[DS].limit = cpustate->sreg[ES].limit = cpustate->sreg[FS].limit = cpustate->sreg[GS].limit = cpustate->sreg[SS].limit = 0xffffffff;
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cpustate->sreg[DS].flags = cpustate->sreg[ES].flags = cpustate->sreg[FS].flags = cpustate->sreg[GS].flags = cpustate->sreg[SS].flags = 0x8093;
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cpustate->sreg[DS].valid = cpustate->sreg[ES].valid = cpustate->sreg[FS].valid = cpustate->sreg[GS].valid = cpustate->sreg[SS].valid =true;
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cpustate->sreg[CS].selector = 0x3000; // pentium only, ppro sel = smbase >> 4
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cpustate->sreg[CS].base = cpustate->smbase;
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cpustate->sreg[CS].limit = 0xffffffff;
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cpustate->sreg[CS].flags = 0x809b;
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cpustate->sreg[CS].valid = true;
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cpustate->cr[4] = 0;
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cpustate->dr[7] = 0x400;
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cpustate->eip = 0x8000;
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cpustate->nmi_masked = true;
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CHANGE_PC(cpustate,cpustate->eip);
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}
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static void i386_set_irq_line(i386_state *cpustate,int irqline, int state)
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{
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if (state != CLEAR_LINE && cpustate->halted)
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@ -3193,6 +3295,11 @@ static void i386_set_irq_line(i386_state *cpustate,int irqline, int state)
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if ( irqline == INPUT_LINE_NMI )
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{
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/* NMI (I do not think that this is 100% right) */
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if(cpustate->nmi_masked)
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{
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cpustate->nmi_latched = true;
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return;
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}
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if ( state )
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i386_trap(cpustate,2, 1, 0);
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}
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@ -3669,6 +3776,9 @@ static CPU_RESET( i486 )
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cpustate->eflags = 0;
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cpustate->eflags_mask = 0x00077fd7;
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cpustate->eip = 0xfff0;
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cpustate->smm = false;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -3781,6 +3891,10 @@ static CPU_RESET( pentium )
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cpustate->eflags_mask = 0x003f7fd7;
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cpustate->eip = 0xfff0;
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cpustate->mxcsr = 0x1f80;
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cpustate->smm = false;
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cpustate->smbase = 0x30000;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -3823,6 +3937,10 @@ static CPU_SET_INFO( pentium )
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i386_state *cpustate = get_safe_token(device);
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switch (state)
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{
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case CPUINFO_INT_INPUT_STATE+INPUT_LINE_SMI:
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if(state)
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pentium_smi(cpustate);
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break;
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case CPUINFO_INT_REGISTER + X87_CTRL: cpustate->x87_cw = info->i; break;
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case CPUINFO_INT_REGISTER + X87_STATUS: cpustate->x87_sw = info->i; break;
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case CPUINFO_INT_REGISTER + X87_TAG: cpustate->x87_tw = info->i; break;
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@ -3907,6 +4025,9 @@ static CPU_RESET( mediagx )
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cpustate->eflags = 0x00200000;
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cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
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cpustate->eip = 0xfff0;
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cpustate->smm = false;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -4027,6 +4148,10 @@ static CPU_RESET( pentium_pro )
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cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
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cpustate->eip = 0xfff0;
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cpustate->mxcsr = 0x1f80;
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cpustate->smm = false;
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cpustate->smbase = 0x30000;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -4127,6 +4252,10 @@ static CPU_RESET( pentium_mmx )
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cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
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cpustate->eip = 0xfff0;
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cpustate->mxcsr = 0x1f80;
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cpustate->smm = false;
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cpustate->smbase = 0x30000;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -4227,6 +4356,10 @@ static CPU_RESET( pentium2 )
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cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
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cpustate->eip = 0xfff0;
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cpustate->mxcsr = 0x1f80;
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cpustate->smm = false;
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cpustate->smbase = 0x30000;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -4327,6 +4460,10 @@ static CPU_RESET( pentium3 )
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cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
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cpustate->eip = 0xfff0;
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cpustate->mxcsr = 0x1f80;
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cpustate->smm = false;
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cpustate->smbase = 0x30000;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -4429,6 +4566,10 @@ static CPU_RESET( pentium4 )
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cpustate->eflags_mask = 0x00277fd7; /* TODO: is this correct? */
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cpustate->eip = 0xfff0;
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cpustate->mxcsr = 0x1f80;
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cpustate->smm = false;
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cpustate->smbase = 0x30000;
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cpustate->nmi_masked = false;
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cpustate->nmi_latched = false;
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x87_reset(cpustate);
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@ -4,7 +4,12 @@
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#define __I386INTF_H__
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#define INPUT_LINE_A20 1
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#define INPUT_LINE_SMI 2
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struct i386_interface
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{
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devcb_write_line smiact;
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};
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// mingw has this defined for 32-bit compiles
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#undef i386
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@ -2498,12 +2498,6 @@ static void I386OP(loadall)(i386_state *cpustate) // Opcode 0x0f 0x07 (0x0
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fatalerror("i386: LOADALL unimplemented at %08X\n", cpustate->pc - 1);
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}
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static void I386OP(rsm)(i386_state *cpustate)
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{
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logerror("i386: Invalid RSM outside SMM at %08X\n", cpustate->pc - 1);
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i386_trap(cpustate, 6, 0, 0);
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}
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static void I386OP(invalid)(i386_state *cpustate)
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{
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report_invalid_opcode(cpustate);
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@ -354,7 +354,7 @@ static const X86_OPCODE x86_opcode_table[] =
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{ 0xA5, OP_2BYTE|OP_I386, I386OP(shld16_cl), I386OP(shld32_cl), },
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{ 0xA8, OP_2BYTE|OP_I386, I386OP(push_gs16), I386OP(push_gs32), },
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{ 0xA9, OP_2BYTE|OP_I386, I386OP(pop_gs16), I386OP(pop_gs32), },
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{ 0xAA, OP_2BYTE|OP_I386, I386OP(rsm), I386OP(rsm), },
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{ 0xAA, OP_2BYTE|OP_PENTIUM, PENTIUMOP(rsm), PENTIUMOP(rsm), },
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{ 0xAB, OP_2BYTE|OP_I386, I386OP(bts_rm16_r16), I386OP(bts_rm32_r32), },
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{ 0xAC, OP_2BYTE|OP_I386, I386OP(shrd16_i8), I386OP(shrd32_i8), },
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{ 0xAD, OP_2BYTE|OP_I386, I386OP(shrd16_cl), I386OP(shrd32_cl), },
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@ -170,6 +170,76 @@ enum
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MMX_MM7=X87_ST7
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};
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enum smram
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{
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SMRAM_SMBASE = 0xF8,
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SMRAM_SMREV = 0xFC,
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SMRAM_IORSRT = 0x100,
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SMRAM_AHALT = 0x102,
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SMRAM_IOEDI = 0x104,
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SMRAM_IOECX = 0x108,
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SMRAM_IOESI = 0x10C,
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SMRAM_ES = 0x1A8,
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SMRAM_CS = 0x1AC,
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SMRAM_SS = 0x1B0,
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SMRAM_DS = 0x1B4,
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SMRAM_FS = 0x1B8,
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SMRAM_GS = 0x1BC,
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SMRAM_LDTR = 0x1C0,
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SMRAM_TR = 0x1C4,
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SMRAM_DR7 = 0x1C8,
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SMRAM_DR6 = 0x1CC,
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SMRAM_EAX = 0x1D0,
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SMRAM_ECX = 0x1D4,
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SMRAM_EDX = 0x1D8,
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SMRAM_EBX = 0x1DC,
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SMRAM_ESP = 0x1E0,
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SMRAM_EBP = 0x1E4,
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SMRAM_ESI = 0x1E8,
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SMRAM_EDI = 0x1EC,
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SMRAM_EIP = 0x1F0,
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SMRAM_EFLAGS = 0x1F4,
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SMRAM_CR3 = 0x1F8,
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SMRAM_CR0 = 0x1FC,
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};
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enum smram_intel_p5
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{
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SMRAM_IP5_IOEIP = 0x110,
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SMRAM_IP5_CR4 = 0x128,
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SMRAM_IP5_ESLIM = 0x130,
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SMRAM_IP5_ESBASE = 0x134,
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SMRAM_IP5_ESACC = 0x138,
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SMRAM_IP5_CSLIM = 0x13C,
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SMRAM_IP5_CSBASE = 0x140,
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SMRAM_IP5_CSACC = 0x144,
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SMRAM_IP5_SSLIM = 0x148,
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SMRAM_IP5_SSBASE = 0x14C,
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SMRAM_IP5_SSACC = 0x150,
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SMRAM_IP5_DSLIM = 0x154,
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SMRAM_IP5_DSBASE = 0x158,
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SMRAM_IP5_DSACC = 0x15C,
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SMRAM_IP5_FSLIM = 0x160,
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SMRAM_IP5_FSBASE = 0x164,
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SMRAM_IP5_FSACC = 0x168,
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SMRAM_IP5_GSLIM = 0x16C,
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SMRAM_IP5_GSBASE = 0x170,
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||||
SMRAM_IP5_GSACC = 0x174,
|
||||
SMRAM_IP5_LDTLIM = 0x178,
|
||||
SMRAM_IP5_LDTBASE = 0x17C,
|
||||
SMRAM_IP5_LDTACC = 0x180,
|
||||
SMRAM_IP5_GDTLIM = 0x184,
|
||||
SMRAM_IP5_GDTBASE = 0x188,
|
||||
SMRAM_IP5_GDTACC = 0x18C,
|
||||
SMRAM_IP5_IDTLIM = 0x190,
|
||||
SMRAM_IP5_IDTBASE = 0x194,
|
||||
SMRAM_IP5_IDTACC = 0x198,
|
||||
SMRAM_IP5_TRLIM = 0x19C,
|
||||
SMRAM_IP5_TRBASE = 0x1A0,
|
||||
SMRAM_IP5_TRACC = 0x1A4,
|
||||
};
|
||||
|
||||
/* Protected mode exceptions */
|
||||
#define FAULT_UD 6 // Invalid Opcode
|
||||
#define FAULT_NM 7 // Coprocessor not available
|
||||
@ -363,6 +433,12 @@ struct i386_state
|
||||
|
||||
vtlb_state *vtlb;
|
||||
|
||||
bool smm;
|
||||
bool nmi_masked;
|
||||
bool nmi_latched;
|
||||
UINT32 smbase;
|
||||
devcb_resolved_write_line smiact;
|
||||
|
||||
// bytes in current opcode, debug only
|
||||
#ifdef DEBUG_MISSING_OPCODE
|
||||
UINT8 opcode_bytes[16];
|
||||
|
||||
@ -144,6 +144,98 @@ static void PENTIUMOP(ud2)(i386_state *cpustate) // Opcode 0x0f 0b
|
||||
i386_trap(cpustate, 6, 0, 0);
|
||||
}
|
||||
|
||||
static void PENTIUMOP(rsm)(i386_state *cpustate)
|
||||
{
|
||||
UINT32 smram_state = cpustate->smbase + 0xfe00;
|
||||
if(!cpustate->smm)
|
||||
{
|
||||
logerror("i386: Invalid RSM outside SMM at %08X\n", cpustate->pc - 1);
|
||||
i386_trap(cpustate, 6, 0, 0);
|
||||
return;
|
||||
}
|
||||
|
||||
// load state, no sanity checks anywhere
|
||||
cpustate->smbase = READ32(cpustate, smram_state+SMRAM_SMBASE);
|
||||
cpustate->cr[4] = READ32(cpustate, smram_state+SMRAM_IP5_CR4);
|
||||
cpustate->sreg[ES].limit = READ32(cpustate, smram_state+SMRAM_IP5_ESLIM);
|
||||
cpustate->sreg[ES].base = READ32(cpustate, smram_state+SMRAM_IP5_ESBASE);
|
||||
cpustate->sreg[ES].flags = READ32(cpustate, smram_state+SMRAM_IP5_ESACC);
|
||||
cpustate->sreg[CS].limit = READ32(cpustate, smram_state+SMRAM_IP5_CSLIM);
|
||||
cpustate->sreg[CS].base = READ32(cpustate, smram_state+SMRAM_IP5_CSBASE);
|
||||
cpustate->sreg[CS].flags = READ32(cpustate, smram_state+SMRAM_IP5_CSACC);
|
||||
cpustate->sreg[SS].limit = READ32(cpustate, smram_state+SMRAM_IP5_SSLIM);
|
||||
cpustate->sreg[SS].base = READ32(cpustate, smram_state+SMRAM_IP5_SSBASE);
|
||||
cpustate->sreg[SS].flags = READ32(cpustate, smram_state+SMRAM_IP5_SSACC);
|
||||
cpustate->sreg[DS].limit = READ32(cpustate, smram_state+SMRAM_IP5_DSLIM);
|
||||
cpustate->sreg[DS].base = READ32(cpustate, smram_state+SMRAM_IP5_DSBASE);
|
||||
cpustate->sreg[DS].flags = READ32(cpustate, smram_state+SMRAM_IP5_DSACC);
|
||||
cpustate->sreg[FS].limit = READ32(cpustate, smram_state+SMRAM_IP5_FSLIM);
|
||||
cpustate->sreg[FS].base = READ32(cpustate, smram_state+SMRAM_IP5_FSBASE);
|
||||
cpustate->sreg[FS].flags = READ32(cpustate, smram_state+SMRAM_IP5_FSACC);
|
||||
cpustate->sreg[GS].limit = READ32(cpustate, smram_state+SMRAM_IP5_GSLIM);
|
||||
cpustate->sreg[GS].base = READ32(cpustate, smram_state+SMRAM_IP5_GSBASE);
|
||||
cpustate->sreg[GS].flags = READ32(cpustate, smram_state+SMRAM_IP5_GSACC);
|
||||
cpustate->ldtr.flags = READ32(cpustate, smram_state+SMRAM_IP5_LDTACC);
|
||||
cpustate->ldtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_LDTLIM);
|
||||
cpustate->ldtr.base = READ32(cpustate, smram_state+SMRAM_IP5_LDTBASE);
|
||||
cpustate->gdtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_GDTLIM);
|
||||
cpustate->gdtr.base = READ32(cpustate, smram_state+SMRAM_IP5_GDTBASE);
|
||||
cpustate->idtr.limit = READ32(cpustate, smram_state+SMRAM_IP5_IDTLIM);
|
||||
cpustate->idtr.base = READ32(cpustate, smram_state+SMRAM_IP5_IDTBASE);
|
||||
cpustate->task.limit = READ32(cpustate, smram_state+SMRAM_IP5_TRLIM);
|
||||
cpustate->task.base = READ32(cpustate, smram_state+SMRAM_IP5_TRBASE);
|
||||
cpustate->task.flags = READ32(cpustate, smram_state+SMRAM_IP5_TRACC);
|
||||
|
||||
cpustate->sreg[ES].selector = READ32(cpustate, smram_state+SMRAM_ES);
|
||||
cpustate->sreg[CS].selector = READ32(cpustate, smram_state+SMRAM_CS);
|
||||
cpustate->sreg[SS].selector = READ32(cpustate, smram_state+SMRAM_SS);
|
||||
cpustate->sreg[DS].selector = READ32(cpustate, smram_state+SMRAM_DS);
|
||||
cpustate->sreg[FS].selector = READ32(cpustate, smram_state+SMRAM_FS);
|
||||
cpustate->sreg[GS].selector = READ32(cpustate, smram_state+SMRAM_GS);
|
||||
cpustate->ldtr.segment = READ32(cpustate, smram_state+SMRAM_LDTR);
|
||||
cpustate->task.segment = READ32(cpustate, smram_state+SMRAM_TR);
|
||||
|
||||
cpustate->dr[7] = READ32(cpustate, smram_state+SMRAM_DR7);
|
||||
cpustate->dr[6] = READ32(cpustate, smram_state+SMRAM_DR6);
|
||||
REG32(EAX) = READ32(cpustate, smram_state+SMRAM_EAX);
|
||||
REG32(ECX) = READ32(cpustate, smram_state+SMRAM_ECX);
|
||||
REG32(EDX) = READ32(cpustate, smram_state+SMRAM_EDX);
|
||||
REG32(EBX) = READ32(cpustate, smram_state+SMRAM_EBX);
|
||||
REG32(ESP) = READ32(cpustate, smram_state+SMRAM_ESP);
|
||||
REG32(EBP) = READ32(cpustate, smram_state+SMRAM_EBP);
|
||||
REG32(ESI) = READ32(cpustate, smram_state+SMRAM_ESI);
|
||||
REG32(EDI) = READ32(cpustate, smram_state+SMRAM_EDI);
|
||||
cpustate->eip = READ32(cpustate, smram_state+SMRAM_EIP);
|
||||
cpustate->eflags = READ32(cpustate, smram_state+SMRAM_EAX);
|
||||
cpustate->cr[3] = READ32(cpustate, smram_state+SMRAM_CR3);
|
||||
cpustate->cr[0] = READ32(cpustate, smram_state+SMRAM_CR0);
|
||||
|
||||
cpustate->CPL = (cpustate->sreg[SS].flags >> 13) & 3; // cpl == dpl of ss
|
||||
|
||||
for(int i = 0; i < GS; i++)
|
||||
{
|
||||
if(PROTECTED_MODE && !V8086_MODE)
|
||||
{
|
||||
cpustate->sreg[i].valid = cpustate->sreg[i].selector ? true : false;
|
||||
cpustate->sreg[i].d = (cpustate->sreg[i].flags & 0x4000) ? 1 : 0;
|
||||
}
|
||||
else
|
||||
cpustate->sreg[i].valid = true;
|
||||
}
|
||||
|
||||
if(!cpustate->smiact.isnull())
|
||||
cpustate->smiact(false);
|
||||
cpustate->smm = false;
|
||||
|
||||
CHANGE_PC(cpustate,cpustate->eip);
|
||||
cpustate->nmi_masked = false;
|
||||
if(cpustate->nmi_latched)
|
||||
{
|
||||
cpustate->nmi_latched = false;
|
||||
i386_trap(cpustate, 2, 1, 0);
|
||||
}
|
||||
}
|
||||
|
||||
static void SSEOP(cvttss2si)(i386_state *cpustate) // Opcode f3 0f 2c
|
||||
{
|
||||
UINT32 src;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user