mirror of
https://github.com/holub/mame
synced 2025-05-21 13:18:56 +03:00
Added a basic FIFO mechanism, added Abort mechanism
This commit is contained in:
Angelo Salese
parent
d719220c6e
commit
dfa4dc5d77
@ -7,12 +7,198 @@
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#include "emu.h"
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#include "video/h63484.h"
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#define LOG 1
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typedef struct _h63484_state h63484_state;
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struct _h63484_state
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{
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h63484_display_pixels_func display_func;
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screen_device *screen; /* screen */
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UINT8 vram[0x40000];
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UINT8 ar;
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UINT8 vreg[0x100];
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UINT8 sr;
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UINT8 fifo[16]; /* FIFO data queue */
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int fifo_flag[16]; /* FIFO flag queue */
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int fifo_ptr; /* FIFO pointer */
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int fifo_dir; /* FIFO direction */
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UINT8 cr;
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UINT8 pr[17]; /* parameter byte register */
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int param_ptr; /* parameter pointer */
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};
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enum
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{
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FIFO_READ = 0,
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FIFO_WRITE
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};
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enum
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{
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FIFO_EMPTY = -1,
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FIFO_PARAMETER,
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FIFO_COMMAND
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};
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#define H63484_SR_CER 0x80 // Command Error
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#define H63484_SR_ARD 0x40 // Area Detect
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#define H63484_SR_CED 0x20 // Command End
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#define H63484_SR_LPD 0x10 // Light Pen Strobe Detect
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#define H63484_SR_RFF 0x08 // Read FIFO Full
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#define H63484_SR_RFR 0x04 // Read FIFO Ready
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#define H63484_SR_WFR 0x02 // Write FIFO Ready
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#define H63484_SR_WFE 0x01 // Write FIFO Empty
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#define CCR 0x02
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// Command Control
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#define ABT 0x8000
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static const char *const acrtc_regnames[0x100/2] =
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{
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"FIFO Entry", // 0x00
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"Command Control (CCR)", // 0x02
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"Operation Mode (OMR)", // 0x04
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"Display Control (DCR)", // 0x06
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"(Undefined)", // 0x08
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"(Undefined)", // 0x0a
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"(Undefined)", // 0x0c
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"(Undefined)", // 0x0e
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"(Undefined)", // 0x10
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"(Undefined)", // 0x12
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"(Undefined)", // 0x14
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"(Undefined)", // 0x16
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"(Undefined)", // 0x18
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"(Undefined)", // 0x1a
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"(Undefined)", // 0x1c
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"(Undefined)", // 0x1e
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"(Undefined)", // 0x20
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"(Undefined)", // 0x22
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"(Undefined)", // 0x24
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"(Undefined)", // 0x26
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"(Undefined)", // 0x28
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"(Undefined)", // 0x2a
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"(Undefined)", // 0x2c
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"(Undefined)", // 0x2e
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"(Undefined)", // 0x30
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"(Undefined)", // 0x32
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"(Undefined)", // 0x34
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"(Undefined)", // 0x36
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"(Undefined)", // 0x38
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"(Undefined)", // 0x3a
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"(Undefined)", // 0x3c
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"(Undefined)", // 0x3e
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"(Undefined)", // 0x40
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"(Undefined)", // 0x42
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"(Undefined)", // 0x44
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"(Undefined)", // 0x46
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"(Undefined)", // 0x48
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"(Undefined)", // 0x4a
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"(Undefined)", // 0x4c
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"(Undefined)", // 0x4e
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"(Undefined)", // 0x50
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"(Undefined)", // 0x52
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"(Undefined)", // 0x54
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"(Undefined)", // 0x56
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"(Undefined)", // 0x58
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"(Undefined)", // 0x5a
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"(Undefined)", // 0x5c
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"(Undefined)", // 0x5e
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"(Undefined)", // 0x60
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"(Undefined)", // 0x62
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"(Undefined)", // 0x64
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"(Undefined)", // 0x66
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"(Undefined)", // 0x68
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"(Undefined)", // 0x6a
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"(Undefined)", // 0x6c
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"(Undefined)", // 0x6e
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"(Undefined)", // 0x70
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"(Undefined)", // 0x72
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"(Undefined)", // 0x74
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"(Undefined)", // 0x76
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"(Undefined)", // 0x78
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"(Undefined)", // 0x7a
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"(Undefined)", // 0x7c
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"(Undefined)", // 0x7e
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"Raster Count (RCR)", // 0x80
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"Horizontal Sync (HSR)", // 0x82
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"Horizontal Display (HDR)", // 0x84
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"Vertical Sync (VSR)", // 0x86
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"Vertical Display (VDR)", // 0x88
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"Split Screen Width (SSW) 0x8a", // 0x8a
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"Split Screen Width (SSW) 0x8c", // 0x8c
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"Split Screen Width (SSW) 0x8e", // 0x8e
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"Blink Control (BCR)", // 0x90
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"Horizontal Window Display (HWR)", // 0x92
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"Vertical Window Display (VWR) 0x94", // 0x94
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"Vertical Window Display (VWR) 0x96", // 0x96
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"Graphic Cursor (GCR0)", // 0x98
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"Graphic Cursor (GCR1)", // 0x9a
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"Graphic Cursor (GCR2)", // 0x9c
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"(Undefined)", // 0x9e
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"(Undefined)", // 0xa0
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"(Undefined)", // 0xa2
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"(Undefined)", // 0xa4
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"(Undefined)", // 0xa6
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"(Undefined)", // 0xa8
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"(Undefined)", // 0xaa
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"(Undefined)", // 0xac
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"(Undefined)", // 0xae
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"(Undefined)", // 0xb0
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"(Undefined)", // 0xb2
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"(Undefined)", // 0xb4
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"(Undefined)", // 0xb6
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"(Undefined)", // 0xb8
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"(Undefined)", // 0xba
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"(Undefined)", // 0xbc
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"(Undefined)", // 0xbe
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// upper screen
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"Raster Address 0 (RAR0)", // 0xc0
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"Memory Width 0 (MWR0)", // 0xc2
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"Start Address 0 (SAR0) 0xc4", // 0xc4
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"Start Address 0 (SAR0) 0xc6", // 0xc6
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// base screen
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"Raster Address 1 (RAR1)", // 0xc8
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"Memory Width 1 (MWR1)", // 0xca
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"Start Address 1 (SAR1) 0xcc", // 0xcc
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"Start Address 1 (SAR1) 0xce", // 0xce
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// lower screen
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"Raster Address 2 (RAR2)", // 0xd0
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"Memory Width 2 (MWR2)", // 0xd2
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"Start Address 2 (SAR2) 0xd4", // 0xd4
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"Start Address 2 (SAR2) 0xd6", // 0xd6
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// window screen
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"Raster Address 3 (RAR3)", // 0xd8
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"Memory Width 3 (MWR3)", // 0xda
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"Start Address 3 (SAR3) 0xdc", // 0xdc
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"Start Address 3 (SAR3) 0xde", // 0xde
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// block cursor 1
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"Block Cursor 1 (BCUR1) 0xe0",
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"Block Cursor 1 (BCUR1) 0xe2",
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// block cursor 2
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"Block Cursor 2 (BCUR2) 0xe4",
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"Block Cursor 2 (BCUR2) 0xe6",
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"Cursor Definition (CDR)",
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"Zoom Factor (ZFR)",
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"Lightpen Address (LPAR) 0xec",
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"Lightpen Address (LPAR) 0xee",
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"(Undefined)", // 0xf0
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"(Undefined)", // 0xf2
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"(Undefined)", // 0xf4
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"(Undefined)", // 0xf6
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"(Undefined)", // 0xf8
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"(Undefined)", // 0xfa
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"(Undefined)", // 0xfc
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"(Undefined)" // 0xfe
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};
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enum
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{
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COMMAND_INVALID = -1
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};
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/*****************************************************************************
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@ -34,6 +220,94 @@ INLINE const h63484_interface *get_interface( device_t *device )
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return (const h63484_interface *) device->static_config();
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}
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INLINE void fifo_clear(h63484_state *h63484)
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{
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int i;
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for (i = 0; i < 16; i++)
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{
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h63484->fifo[i] = 0;
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h63484->fifo_flag[i] = FIFO_EMPTY;
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}
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h63484->fifo_ptr = -1;
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h63484->sr |= H63484_SR_WFR;
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h63484->sr |= H63484_SR_WFE;
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}
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INLINE int fifo_param_count(h63484_state *h63484)
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{
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int i;
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for (i = 0; i < 16; i++)
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{
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if (h63484->fifo_flag[i] != FIFO_PARAMETER) break;
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}
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return i;
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}
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INLINE void fifo_set_direction(h63484_state *h63484, int dir)
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{
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if (h63484->fifo_dir != dir)
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{
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fifo_clear(h63484);
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}
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h63484->fifo_dir = dir;
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}
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INLINE void queue(h63484_state *h63484, UINT8 data, int flag)
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{
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if (h63484->fifo_ptr < 15)
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{
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h63484->fifo_ptr++;
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h63484->fifo[h63484->fifo_ptr] = data;
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h63484->fifo_flag[h63484->fifo_ptr] = flag;
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if (h63484->fifo_ptr == 16)
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h63484->sr &= ~H63484_SR_WFR;
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h63484->sr &= ~H63484_SR_WFE;
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}
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else
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{
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// TODO what happen? somebody set us up the bomb
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printf("FIFO?\n");
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}
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}
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INLINE void dequeue(h63484_state *h63484, UINT8 *data, int *flag)
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{
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int i;
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*data = h63484->fifo[0];
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*flag = h63484->fifo_flag[0];
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if (h63484->fifo_ptr > -1)
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{
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for (i = 0; i < 15; i++)
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{
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h63484->fifo[i] = h63484->fifo[i + 1];
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h63484->fifo_flag[i] = h63484->fifo_flag[i + 1];
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}
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h63484->fifo[15] = 0;
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h63484->fifo_flag[15] = 0;
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h63484->fifo_ptr--;
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h63484->sr |= H63484_SR_WFR;
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if (h63484->fifo_ptr == -1)
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h63484->sr |= H63484_SR_WFE;
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}
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}
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/*-------------------------------------------------
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ROM( h63484 )
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-------------------------------------------------*/
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@ -43,15 +317,103 @@ ROM_START( h63484 )
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ROM_LOAD( "h63484.bin", 0x000, 0x100, NO_DUMP ) /* internal control ROM */
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ROM_END
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/*-------------------------------------------------
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ADDRESS_MAP( upd7220 )
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-------------------------------------------------*/
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READ8_DEVICE_HANDLER( h63484_vram_r )
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{
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h63484_state *h63484 = get_safe_token(device);
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return h63484->vram[offset];
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}
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WRITE8_DEVICE_HANDLER( h63484_vram_w )
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{
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h63484_state *h63484 = get_safe_token(device);
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h63484->vram[offset] = data;
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}
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/*****************************************************************************
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IMPLEMENTATION
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*****************************************************************************/
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static int translate_command(UINT8 data)
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{
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int command = COMMAND_INVALID;
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switch (data)
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{
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}
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return command;
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}
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static void process_fifo(device_t *device)
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{
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h63484_state *h63484 = get_safe_token(device);
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UINT8 data;
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int flag;
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dequeue(h63484, &data, &flag);
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if (flag == FIFO_COMMAND)
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{
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h63484->cr = (data & 0xff00) >> 8;
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h63484->param_ptr = 1;
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h63484->sr &= ~H63484_SR_CED;
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dequeue(h63484, &data, &flag);
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h63484->pr[h63484->param_ptr] = data & 0xff;
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h63484->param_ptr++;
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}
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else
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{
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h63484->pr[h63484->param_ptr] = (data & 0xff00) >> 8;
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h63484->param_ptr++;
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dequeue(h63484, &data, &flag);
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h63484->pr[h63484->param_ptr] = data & 0xff;
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h63484->param_ptr++;
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}
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switch (translate_command(h63484->cr))
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{
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// ...
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}
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}
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static void exec_abort_sequence(device_t *device)
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{
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h63484_state *h63484 = get_safe_token(device);
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fifo_clear(h63484);
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h63484->sr = H63484_SR_WFR | H63484_SR_WFE | H63484_SR_CED; // set to 0x23
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}
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static void check_video_registers(device_t *device, int offset)
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{
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h63484_state *h63484 = get_safe_token(device);
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UINT16 vreg_data;
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vreg_data = (h63484->vreg[offset]<<8)|(h63484->vreg[offset+1]&0xff);
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switch(offset)
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{
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case 0x00: // FIFO entry, not covered there
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break;
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case CCR: // Command Entry
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if(vreg_data & ABT) // abort sequence
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exec_abort_sequence(device);
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break;
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}
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}
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READ16_DEVICE_HANDLER( h63484_status_r )
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{
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//h63484_state *h63484 = get_safe_token(device);
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h63484_state *h63484 = get_safe_token(device);
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return 0;
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return h63484->sr;
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}
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READ16_DEVICE_HANDLER( h63484_data_r )
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@ -66,12 +428,39 @@ READ16_DEVICE_HANDLER( h63484_data_r )
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WRITE16_DEVICE_HANDLER( h63484_address_w )
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{
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//h63484_state *h63484 = get_safe_token(device);
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h63484_state *h63484 = get_safe_token(device);
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if(ACCESSING_BITS_0_7)
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h63484->ar = data & 0xff;
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}
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WRITE16_DEVICE_HANDLER( h63484_data_w )
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{
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//h63484_state *h63484 = get_safe_token(device);
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h63484_state *h63484 = get_safe_token(device);
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if(LOG) printf("%s -> %02x\n",acrtc_regnames[h63484->ar/2],data);
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if(ACCESSING_BITS_8_15)
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h63484->vreg[h63484->ar] = (data & 0xff00) >> 8;
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if(ACCESSING_BITS_0_7)
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h63484->vreg[h63484->ar+1] = (data & 0xff);
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if(h63484->ar == 0)
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{
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fifo_set_direction(h63484, FIFO_WRITE);
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queue(h63484, (data & 0xff00) >> 8, (h63484->sr & H63484_SR_CED) >> 5);
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queue(h63484, (data & 0x00ff) >> 0, 0);
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process_fifo(device);
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}
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else
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check_video_registers(device,h63484->ar);
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if(h63484->ar & 0x80)
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{
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h63484->ar+=2;
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h63484->ar &= 0xff; // TODO: what happens if it overflows?
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}
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}
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static DEVICE_START( h63484 )
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@ -51,6 +51,9 @@ READ16_DEVICE_HANDLER( h63484_data_r );
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WRITE16_DEVICE_HANDLER( h63484_address_w );
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WRITE16_DEVICE_HANDLER( h63484_data_w );
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READ8_DEVICE_HANDLER( h63484_vram_r );
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WRITE8_DEVICE_HANDLER( h63484_vram_w );
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#endif /* __H63484_H__ */
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@ -643,12 +643,12 @@ static READ8_HANDLER( h63484_rom_r )
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}
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static ADDRESS_MAP_START( adp_h63484_map, AS_0, 8 )
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AM_RANGE(0x00000, 0x3ffff) AM_RAM
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AM_RANGE(0x00000, 0x3ffff) AM_DEVREADWRITE("h63484",h63484_vram_r,h63484_vram_w)
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AM_RANGE(0x40000, 0x7ffff) AM_READ(h63484_rom_r)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( fashiong_h63484_map, AS_0, 8 )
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AM_RANGE(0x00000, 0x3ffff) AM_RAM
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AM_RANGE(0x00000, 0x3ffff) AM_DEVREADWRITE("h63484",h63484_vram_r,h63484_vram_w)
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// AM_RANGE(0x40000, 0x7ffff) AM_ROM AM_REGION("gfx1", 0)
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ADDRESS_MAP_END
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