mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
Checkpoint (nw)
This commit is contained in:
Olivier Galibert
parent
3d9257963e
commit
e0090f499c
@ -93,9 +93,9 @@ protected:
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f |= F_Z;
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if(r & 0x80000000)
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f |= F_N;
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if(((v1 & r) | ((~v2) & (v1 | r))) & 0x80000000)
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if(((v2 & r) | ((~v1) & (v2 | r))) & 0x80000000)
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f |= F_C;
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if(((v1 ^ v2) & (v2 ^ r)) & 0x80000000)
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if(((v1 ^ v2) & (v1 ^ r)) & 0x80000000)
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f |= F_V;
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m_hr[4] = (m_hr[4] & ~F_MASK) | f;
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return r;
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@ -46,10 +46,17 @@ private:
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u16 m_dma_count;
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emu_timer *m_dma_timer;
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u32 m_port0_ddr, m_port0_data;
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u16 m_port0_ddr;
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u8 m_port0_dataw, m_port0_data;
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u8 m_port0_maskw, m_port0_maskr;
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u16 m_gpu0_adr, m_gpu0_count, m_gpu1_adr, m_gpu1_count;
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u16 m_gpu0b_adr, m_gpu0b_count, m_gpu1b_adr, m_gpu1b_count;
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u16 m_gpu_adr, m_gpu_descsize_adr, m_gpu_descdata_adr;
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u32 m_int_active;
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u32 m_int_enabled;
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u32 m_int_nmi;
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u32 m_sd[0x400][0x800];
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@ -59,8 +66,30 @@ private:
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void irq_clear(u32 level);
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bool irq_state(u32 level) const;
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void irq_clear_w(u16 data);
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u16 irq_nmi_r();
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void irq_nmi_w(u16 data);
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u16 irq_enable_r();
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void irq_enable_w(u16 data);
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u8 irq_level_r();
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void gpu0_adr_w(u16 data);
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u16 gpu0b_adr_r();
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void gpu0b_adr_w(u16 data);
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void gpu0_count_w(u16 data);
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u16 gpu0b_count_r();
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void gpu0b_count_w(u16 data);
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void gpu0_trigger_w(u8 data);
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void gpu1_adr_w(u16 data);
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u16 gpu1b_adr_r();
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void gpu1b_adr_w(u16 data);
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void gpu1_count_w(u16 data);
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u16 gpu1b_count_r();
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void gpu1b_count_w(u16 data);
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void gpu1_trigger_w(u8 data);
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void gpu_update(u16 count, u16 adr);
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void gpu_descsize_w(u16 data);
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void gpu_descdata_w(u16 data);
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void gpu_adr_w(u16 data);
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@ -80,10 +109,11 @@ private:
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u8 debug_port_r();
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u8 debug_port_status_r();
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void port0_ddr_w(offs_t, u32 data, u32 mem_mask);
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u32 port0_ddr_r();
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void port0_w(offs_t, u32 data, u32 mem_mask);
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u32 port0_r();
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void port0_ddr_w(u16 data);
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u16 port0_ddr_r();
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void port0_update();
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void port0_w(u8 data);
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u8 port0_r();
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void crtc_w(offs_t reg, u16 data);
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@ -97,9 +127,12 @@ private:
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void xavix2_state::irq_raise(u32 level)
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{
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if(!m_int_active)
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m_maincpu->set_input_line(0, ASSERT_LINE);
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m_int_active |= 1 << level;
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u32 line = 1 << level;
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if ((m_int_enabled | m_int_nmi) & line) {
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if(!m_int_active)
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m_maincpu->set_input_line(0, ASSERT_LINE);
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m_int_active |= line;
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}
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}
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void xavix2_state::irq_clear(u32 level)
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@ -117,9 +150,30 @@ void xavix2_state::irq_clear_w(u16 data)
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}
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u16 xavix2_state::irq_nmi_r()
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{
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return m_int_nmi;
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}
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void xavix2_state::irq_nmi_w(u16 data)
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{
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m_int_nmi = data;
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}
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u16 xavix2_state::irq_enable_r()
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{
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return m_int_enabled;
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}
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void xavix2_state::irq_enable_w(u16 data)
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{
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irq_clear(~data);
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m_int_enabled = data;
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}
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u8 xavix2_state::irq_level_r()
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{
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for(u32 i=31; i>=0; i--)
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for(u32 i=0; i<=12; i++)
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if(m_int_active & (1 << i))
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return i;
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return 0xff;
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@ -130,15 +184,80 @@ bool xavix2_state::irq_state(u32 level) const
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return m_int_active & (1 << level);
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}
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void xavix2_state::gpu_adr_w(u16 data)
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void xavix2_state::gpu0_adr_w(u16 data)
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{
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m_gpu_adr = data;
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m_gpu0_adr = data;
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}
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void xavix2_state::gpu_count_w(u16 data)
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u16 xavix2_state::gpu0b_adr_r()
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{
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for(u32 i=0; i != data; i++) {
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u64 command = m_maincpu->space(AS_PROGRAM).read_qword(m_gpu_adr + 8*i);
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return m_gpu0b_adr;
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}
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void xavix2_state::gpu0b_adr_w(u16 data)
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{
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m_gpu0b_adr = data;
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}
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void xavix2_state::gpu0_count_w(u16 data)
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{
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m_gpu0_count = data;
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}
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u16 xavix2_state::gpu0b_count_r()
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{
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return m_gpu0b_count;
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}
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void xavix2_state::gpu0b_count_w(u16 data)
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{
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m_gpu0b_count = data;
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}
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void xavix2_state::gpu0_trigger_w(u8 data)
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{
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gpu_update(m_gpu0_count, m_gpu0_adr);
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}
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void xavix2_state::gpu1_adr_w(u16 data)
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{
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m_gpu1_adr = data;
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}
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u16 xavix2_state::gpu1b_adr_r()
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{
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return m_gpu1b_adr;
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}
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void xavix2_state::gpu1b_adr_w(u16 data)
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{
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m_gpu1b_adr = data;
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}
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void xavix2_state::gpu1_count_w(u16 data)
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{
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m_gpu1_count = data;
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}
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u16 xavix2_state::gpu1b_count_r()
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{
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return m_gpu1b_count;
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}
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void xavix2_state::gpu1b_count_w(u16 data)
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{
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m_gpu1b_count = data;
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}
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void xavix2_state::gpu1_trigger_w(u8 data)
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{
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gpu_update(m_gpu1_count, m_gpu1_adr);
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}
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void xavix2_state::gpu_update(u16 count, u16 adr)
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{
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for(u32 i=0; i != count; i++) {
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u64 command = m_maincpu->space(AS_PROGRAM).read_qword(adr + 8*i);
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logerror("gpu %02d: %016x x=%03x y=%03x ?=%02x ?=%x ?=%02x w=%02x h=%02x c=%04x %s\n",
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i, command,
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(command >> 0) & 0x7ff,
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@ -150,9 +269,10 @@ void xavix2_state::gpu_count_w(u16 data)
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(command >> 42) & 0x3f,
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(command >> 48) & 0xffff,
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machine().describe_context());
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u32 idx = (command >> 58) & 0x3f;
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u32 idx = (command >> 30) & 0x3f;
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u32 idx2 = (command >> 58) & 0x3f;
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u32 descsize = m_maincpu->space(AS_PROGRAM).read_dword(m_gpu_descsize_adr + 4*idx);
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u16 descdata = m_maincpu->space(AS_PROGRAM).read_word(m_gpu_descdata_adr + 2*idx);
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u16 descdata = m_maincpu->space(AS_PROGRAM).read_word(m_gpu_descdata_adr + 2*idx2);
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u32 sadr = (descdata << 14) | ((command >> 43) & 0x3fe0);
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u32 x = (command >> 0) & 0x7ff;
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@ -162,13 +282,31 @@ void xavix2_state::gpu_count_w(u16 data)
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u32 bpp = 1 + ((descsize >> 24) & 7);
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logerror("gpu - data %06x size %08x w=%x h=%x ?=%x bpp=%x ?=%x\n", sadr, descsize, sx, sy, (descsize >> 16) & 0xff, bpp, descsize >> 27);
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u32 stride = sx;
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if(x+sx > 0x800)
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sx = 0x800 - x;
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if(y+sy > 0x400)
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sy = 0x400 - y;
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u32 avail = 0;
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u32 mask = (1 << bpp) - 1;
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u32 shift = (8 - bpp);
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for(u32 yy=0; yy<sy; yy++) {
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u64 v = m_maincpu->space(AS_PROGRAM).read_qword(sadr);
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sadr += 8;
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avail = 64;
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for(u32 xx=0; xx<sx; xx++) {
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if (avail < bpp) {
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v = m_maincpu->space(AS_PROGRAM).read_qword(sadr);
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sadr += 8;
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avail = 64;
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}
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u32 c = (v & mask) << shift;
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m_sd[y+yy][x+xx] = 0xff000000 | (0x010101 * c);
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v >>= bpp;
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avail -= bpp;
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}
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}
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/*
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switch(bpp) {
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case 2: {
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stride = 8*((sx+31)/32);
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@ -216,6 +354,7 @@ void xavix2_state::gpu_count_w(u16 data)
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m_sd[yy+y][xx+x] = 0xffff0000;
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break;
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}
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*/
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}
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}
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@ -307,30 +446,50 @@ u8 xavix2_state::debug_port_status_r()
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return 1<<1;
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}
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void xavix2_state::port0_ddr_w(offs_t, u32 data, u32 mem_mask)
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void xavix2_state::port0_ddr_w(u16 data)
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{
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COMBINE_DATA(&m_port0_ddr);
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logerror("port0 ddr %08x\n", data);
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// logerror("%s: port0 ddr %04x -> %04x\n", machine().describe_context(), m_port0_ddr, data);
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m_port0_ddr = data;
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m_port0_maskr = m_port0_maskw = 0;
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for (u32 i=0; i<8; i++) {
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m_port0_maskr |= ((data & 3) == 0) ? 1 << i : 0;
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m_port0_maskw |= ((data & 3) == 3) ? 1 << i : 0;
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data >>= 2;
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}
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// logerror("%s: port0 maskr %04x, maskw %04x\n", machine().describe_context(), m_port0_maskr, m_port0_maskw);
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port0_update();
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}
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u32 xavix2_state::port0_ddr_r()
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u16 xavix2_state::port0_ddr_r()
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{
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return m_port0_ddr;
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}
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void xavix2_state::port0_w(offs_t, u32 data, u32 mem_mask)
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void xavix2_state::port0_update()
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{
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COMBINE_DATA(&m_port0_data);
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m_i2cmem->write_sda((m_port0_data & 0x00200000) && m_i2cmem->read_sda());
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m_i2cmem->write_scl(!!(m_port0_data & 0x00100000));
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logerror("port0_w %08x\n", m_port0_data);
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u8 old = m_port0_data;
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m_port0_data &= ~m_port0_maskw;
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m_port0_data |= (m_port0_dataw & m_port0_maskw);
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// logerror("%s: port0 %04x -> %04x (%04x)\n", machine().describe_context(), old, m_port0_data, m_port0_dataw);
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if (m_port0_maskw & 0x20)
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m_i2cmem->write_sda((m_port0_dataw >> 5) & 0x1);
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if (m_port0_maskw & 0x10)
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m_i2cmem->write_scl((m_port0_dataw >> 4) & 0x1);
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if ((old ^ m_port0_dataw) & 0x30) {
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m_port0_data &= ~m_port0_maskr;
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m_port0_data |= ((m_i2cmem->read_sda() << 5) & m_port0_maskr);
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}
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}
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u32 xavix2_state::port0_r()
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void xavix2_state::port0_w(u8 data)
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{
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// Slightly hacky, should take ddr into account
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u32 data = m_i2cmem->read_sda() ? m_port0_data | 0x00200000 : m_port0_data & ~0x00200000;
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logerror("port0_r %08x\n", data);
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m_port0_dataw = data;
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port0_update();
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}
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u8 xavix2_state::port0_r()
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{
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u8 data = (m_port0_dataw & m_port0_maskw) | (m_port0_data & m_port0_maskr);
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return data;
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}
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@ -385,15 +544,25 @@ void xavix2_state::mem(address_map &map)
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map(0xffffe00c, 0xffffe00c).w(FUNC(xavix2_state::dma_control_w));
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map(0xffffe010, 0xffffe010).rw(FUNC(xavix2_state::dma_status_r), FUNC(xavix2_state::dma_status_w));
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map(0xffffe204, 0xffffe207).rw(FUNC(xavix2_state::port0_ddr_r), FUNC(xavix2_state::port0_ddr_w));
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map(0xffffe208, 0xffffe20b).rw(FUNC(xavix2_state::port0_r), FUNC(xavix2_state::port0_w));
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map(0xffffe204, 0xffffe205).rw(FUNC(xavix2_state::port0_ddr_r), FUNC(xavix2_state::port0_ddr_w));
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map(0xffffe20a, 0xffffe20a).rw(FUNC(xavix2_state::port0_r), FUNC(xavix2_state::port0_w));
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map(0xffffe238, 0xffffe238).rw(FUNC(xavix2_state::debug_port_r), FUNC(xavix2_state::debug_port_w));
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map(0xffffe239, 0xffffe239).r(FUNC(xavix2_state::debug_port_status_r));
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map(0xffffe604, 0xffffe605).w(FUNC(xavix2_state::gpu_adr_w));
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map(0xffffe606, 0xffffe607).w(FUNC(xavix2_state::gpu_count_w));
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map(0xffffe400, 0xffffe401).w(FUNC(xavix2_state::gpu0_adr_w));
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map(0xffffe404, 0xffffe405).w(FUNC(xavix2_state::gpu0_count_w));
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map(0xffffe408, 0xffffe408).w(FUNC(xavix2_state::gpu0_trigger_w));
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map(0xffffe40c, 0xffffe40d).w(FUNC(xavix2_state::gpu1_adr_w));
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map(0xffffe410, 0xffffe411).w(FUNC(xavix2_state::gpu1_count_w));
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map(0xffffe414, 0xffffe414).w(FUNC(xavix2_state::gpu1_trigger_w));
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map(0xffffe600, 0xffffe601).rw(FUNC(xavix2_state::gpu0b_adr_r), FUNC(xavix2_state::gpu0b_adr_w));
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map(0xffffe602, 0xffffe603).rw(FUNC(xavix2_state::gpu0b_count_r), FUNC(xavix2_state::gpu0b_count_w));
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map(0xffffe604, 0xffffe605).rw(FUNC(xavix2_state::gpu1b_adr_r), FUNC(xavix2_state::gpu1b_adr_w));
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map(0xffffe606, 0xffffe607).rw(FUNC(xavix2_state::gpu1b_count_r), FUNC(xavix2_state::gpu1b_count_w));
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map(0xffffe608, 0xffffe609).w(FUNC(xavix2_state::gpu_descsize_w));
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map(0xffffe60a, 0xffffe60a).lr8(NAME([]() { return 0x40; })); // pal/ntsc
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map(0xffffe60a, 0xffffe60b).lr16(NAME([]() { return 0x240; })); // pal/ntsc
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map(0xffffe622, 0xffffe623).w(FUNC(xavix2_state::gpu_descdata_w));
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map(0xffffe630, 0xffffe631).lr16(NAME([]() { return 0x210; }));
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map(0xffffe632, 0xffffe633).lr16(NAME([]() { return 0x210; }));
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@ -401,10 +570,17 @@ void xavix2_state::mem(address_map &map)
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map(0xfffffc00, 0xfffffc00).r(FUNC(xavix2_state::irq_level_r));
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map(0xfffffc04, 0xfffffc05).w(FUNC(xavix2_state::irq_clear_w));
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map(0xfffffc08, 0xfffffc09).rw(FUNC(xavix2_state::irq_nmi_r), FUNC(xavix2_state::irq_nmi_w));
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map(0xfffffc0a, 0xfffffc0b).rw(FUNC(xavix2_state::irq_enable_r), FUNC(xavix2_state::irq_enable_w));
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}
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uint32_t xavix2_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
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{
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if(machine().input().code_pressed_once(KEYCODE_8))
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irq_raise(8);
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if(machine().input().code_pressed_once(KEYCODE_0))
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irq_raise(10);
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constexpr int dx = 0x400 - 320;
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constexpr int dy = 0x200 - 200;
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