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s3: added configuration registers for Trio/Virge chipsets. Are read-only for now. (no whatsnew)

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mahlemiut 2014-03-28 01:26:59 +00:00
parent d18d514e4e
commit e013e80064
2 changed files with 40 additions and 0 deletions
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18
src/emu/bus/isa/s3virge.c
View File

@ -111,6 +111,18 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index)
case 0x35:
res = s3.crt_reg_lock;
break;
case 0x36: // Configuration register 1
res = 0x12; // PCI (not really), 1-cycle EDO
if(vga.svga_intf.vram_size == 0x200000)
res |= 0x80;
else if(vga.svga_intf.vram_size == 0x400000)
res |= 0x00;
else
res |= 0x80; // shouldn't get here...
break;
case 0x37: // Configuration register 2
res = 0x09; // enable chipset, 64k BIOS size, internal DCLK/MCLK
break;
case 0x38:
res = s3.reg_lock1;
break;
@ -175,12 +187,18 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index)
case 0x67:
res = s3.ext_misc_ctrl_2;
break;
case 0x68: // Configuration register 3
res = 0x03; // no /CAS,/OE stretch time
break;
case 0x69:
res = vga.crtc.start_addr_latch >> 16;
break;
case 0x6a:
res = svga.bank_r & 0x7f;
break;
case 0x6f: // Configuration register 4
res = 0x18; // Serial port I/O at port 0xe8, Serial port I/O disabled (MMIO only), no /WE delay
break;
default:
res = vga.crtc.data[index];
//debugger_break(machine);

22
src/emu/video/pc_vga.c
View File

@ -2758,6 +2758,22 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index)
case 0x35:
res = s3.crt_reg_lock;
break;
case 0x36: // Configuration register 1
res = 0x1e; // PCI (not really), Fast Page Mode DRAM
if(vga.svga_intf.vram_size == 0x80000)
res |= 0xe0;
else if(vga.svga_intf.vram_size == 0x100000)
res |= 0xd0;
else if(vga.svga_intf.vram_size == 0x200000)
res |= 0x80;
else if(vga.svga_intf.vram_size == 0x400000)
res |= 0x00;
else
res |= 0xe0; // shouldn't get here...
break;
case 0x37: // Configuration register 2
res = 0x09; // enable chipset, 64k BIOS size, internal DCLK/MCLK
break;
case 0x38:
res = s3.reg_lock1;
break;
@ -2823,12 +2839,18 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index)
case 0x67:
res = s3.ext_misc_ctrl_2;
break;
case 0x68: // Configuration register 3
res = 0x03; // no /CAS,/OE stretch time, 32-bit data bus size
break;
case 0x69:
res = vga.crtc.start_addr_latch >> 16;
break;
case 0x6a:
res = svga.bank_r & 0x7f;
break;
case 0x6f: // Configuration register 4
res = 0x18; // LPB(?) mode, Serial port I/O at port 0xe8, Serial port I/O disabled (MMIO only), no WE delay
break;
default:
res = vga.crtc.data[index];
//debugger_break(machine);