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https://github.com/holub/mame
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mc68hc11: Added LSRA, LSRB, DEC EXT, BLS, NEGA, NEGB, BHI
This commit is contained in:
Angelo Salese
parent
23d8a23308
commit
e0473bb579
@ -824,6 +824,18 @@ static void HC11OP(beq)(hc11_state *cpustate)
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}
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/* BHI 0x22 */
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static void HC11OP(bhi)(hc11_state *cpustate)
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{
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INT8 rel = FETCH(cpustate);
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if (((cpustate->ccr & CC_C) == 0) && ((cpustate->ccr & CC_Z) == 0)) /* Branch if C and Z flag clear */
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{
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SET_PC(cpustate, cpustate->ppc + rel + 2);
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}
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CYCLES(cpustate, 3);
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}
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/* BNE 0x26 */
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static void HC11OP(bne)(hc11_state *cpustate)
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{
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@ -849,6 +861,17 @@ static void HC11OP(ble)(hc11_state *cpustate)
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CYCLES(cpustate, 3);
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}
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/* BLS 0x23 */
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static void HC11OP(bls)(hc11_state *cpustate)
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{
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INT8 rel = FETCH(cpustate);
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if (cpustate->ccr & CC_C || cpustate->ccr & CC_Z) /* Branch if C or Z flag set */
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{
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SET_PC(cpustate, cpustate->ppc + rel + 2);
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}
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CYCLES(cpustate, 3);
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}
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/* BMI 0x2B */
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static void HC11OP(bmi)(hc11_state *cpustate)
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{
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@ -1485,6 +1508,22 @@ static void HC11OP(decb)(hc11_state *cpustate)
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CYCLES(cpustate, 2);
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}
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/* DEC EXT 0x7A */
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static void HC11OP(dec_ext)(hc11_state *cpustate)
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{
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UINT16 adr = FETCH16(cpustate);
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UINT8 i = READ8(cpustate, adr);
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CLEAR_NZV(cpustate);
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if (i == 0x80)
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SET_VFLAG(cpustate);
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i--;
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SET_N8(i);
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SET_Z8(i);
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WRITE8(cpustate, adr, i);
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CYCLES(cpustate, 6);
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}
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/* DEX 0x09 */
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static void HC11OP(dex)(hc11_state *cpustate)
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{
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@ -2123,6 +2162,32 @@ static void HC11OP(lsld)(hc11_state *cpustate)
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CYCLES(cpustate, 3);
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}
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/* LSRA 0x44 */
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static void HC11OP(lsra)(hc11_state *cpustate)
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{
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UINT16 r = REG_A >> 1;
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (REG_A & 1) ? CC_C : 0;
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REG_A = (UINT8)(r);
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cpustate->ccr |= ((cpustate->ccr & CC_C) == CC_C) ? CC_V : 0;
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SET_Z8(REG_A);
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CYCLES(cpustate, 2);
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}
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/* LSRB 0x54 */
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static void HC11OP(lsrb)(hc11_state *cpustate)
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{
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UINT16 r = REG_B >> 1;
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CLEAR_NZVC(cpustate);
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cpustate->ccr |= (REG_B & 1) ? CC_C : 0;
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REG_B = (UINT8)(r);
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cpustate->ccr |= ((cpustate->ccr & CC_C) == CC_C) ? CC_V : 0;
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SET_Z8(REG_B);
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CYCLES(cpustate, 2);
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}
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/* LSRD 0x04 */
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static void HC11OP(lsrd)(hc11_state *cpustate)
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{
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@ -2148,6 +2213,33 @@ static void HC11OP(mul)(hc11_state *cpustate)
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CYCLES(cpustate, 10);
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}
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/* NEGA 0x40 */
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static void HC11OP(nega)(hc11_state *cpustate)
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{
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INT8 r = 0x00 - REG_A;
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REG_A = r;
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CLEAR_NZVC(cpustate);
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SET_N8(r);
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SET_Z8(r);
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cpustate->ccr |= (REG_A == 0x80) ? CC_V : 0;
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cpustate->ccr |= (REG_A == 0x00) ? CC_C : 0;
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CYCLES(cpustate, 2);
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}
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/* NEGB 0x50 */
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static void HC11OP(negb)(hc11_state *cpustate)
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{
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INT8 r = 0x00 - REG_B;
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REG_B = r;
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CLEAR_NZVC(cpustate);
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SET_N8(r);
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SET_Z8(r);
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cpustate->ccr |= (REG_B == 0x80) ? CC_V : 0;
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cpustate->ccr |= (REG_B == 0x00) ? CC_C : 0;
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CYCLES(cpustate, 2);
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}
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/* NOP 0x01 */
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static void HC11OP(nop)(hc11_state *cpustate)
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{
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@ -65,6 +65,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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{ 0, 0x27, HC11OP(beq) },
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// { 0, 0x2c, HC11OP(bge) },
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// { 0, 0x2e, HC11OP(bgt) },
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{ 0, 0x22, HC11OP(bhi) },
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{ 0, 0x85, HC11OP(bita_imm) },
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{ 0, 0x95, HC11OP(bita_dir) },
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{ 0, 0xb5, HC11OP(bita_ext) },
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@ -76,7 +77,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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{ 0, 0xe5, HC11OP(bitb_indx) },
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{ 0x18, 0xe5, HC11OP(bitb_indy) },
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{ 0, 0x2f, HC11OP(ble) },
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// { 0, 0x23, HC11OP(bls) },
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{ 0, 0x23, HC11OP(bls) },
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// { 0, 0x2d, HC11OP(blt) },
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{ 0, 0x2b, HC11OP(bmi) },
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{ 0, 0x26, HC11OP(bne) },
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@ -137,7 +138,7 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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// { 0, 0x19, HC11OP(daa) },
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{ 0, 0x4a, HC11OP(deca) },
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{ 0, 0x5a, HC11OP(decb) },
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// { 0, 0x7a, HC11OP(dec_ext) },
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{ 0, 0x7a, HC11OP(dec_ext) },
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// { 0, 0x6a, HC11OP(dec_indx) },
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// { 0x18, 0x6a, HC11OP(dec_indy) },
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// { 0, 0x34, HC11OP(des) },
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@ -201,15 +202,15 @@ static const hc11_opcode_list_struct hc11_opcode_list[] =
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{ 0x1a, 0xee, HC11OP(ldy_indx) },
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{ 0x18, 0xee, HC11OP(ldy_indy) },
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{ 0, 0x05, HC11OP(lsld) },
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// { 0, 0x44, HC11OP(lsra) },
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// { 0, 0x54, HC11OP(lsrb) },
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{ 0, 0x44, HC11OP(lsra) },
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{ 0, 0x54, HC11OP(lsrb) },
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// { 0, 0x74, HC11OP(lsr_ext) },
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// { 0, 0x64, HC11OP(lsr_indx) },
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// { 0x18, 0x64, HC11OP(lsr_indy) },
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{ 0, 0x04, HC11OP(lsrd) },
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{ 0, 0x3d, HC11OP(mul) },
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// { 0, 0x40, HC11OP(nega) },
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// { 0, 0x50, HC11OP(negb) },
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{ 0, 0x40, HC11OP(nega) },
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{ 0, 0x50, HC11OP(negb) },
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// { 0, 0x70, HC11OP(neg_ext) },
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// { 0, 0x60, HC11OP(neg_indx) },
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// { 0x18, 0x60, HC11OP(neg_indy) },
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@ -7,6 +7,7 @@ Many thanks to Olivier Galibert for the CPU identify effort ;-)
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TODO:
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- Fix the CPU core bugs! (too many to list)
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- at some point it jumps to illegal ROM addresses, why?
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- video HW looks awkward;
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- paletteram format is wrong;
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- sound;
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@ -63,9 +64,10 @@ Some debug tricks (let's test this CPU as more as possible):
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#include "driver.h"
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#include "cpu/mc68hc11/mc68hc11.h"
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#include "sound/ay8910.h"
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static UINT8 *work_ram;
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static UINT8 *hitpoker_sys_regs;
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static UINT8 hitpoker_pic_data;
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VIDEO_START(hitpoker)
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{
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@ -99,22 +101,11 @@ VIDEO_UPDATE(hitpoker)
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return 0;
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}
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/* It wants that the even/odd memory is equal for this, 8-bit vram on a 16-bit wide bus? */
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static READ8_HANDLER( hitpoker_work_ram_r )
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{
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return work_ram[offset & ~1];
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}
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static WRITE8_HANDLER( hitpoker_work_ram_w )
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{
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work_ram[offset & ~1] = data;
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}
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static READ8_HANDLER( hitpoker_vram_r )
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{
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UINT8 *ROM = memory_region(space->machine, "maincpu");
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if(hitpoker_sys_regs[0x00] & 0x10)
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if(hitpoker_pic_data & 0x10)
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return videoram[offset];
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else
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return ROM[offset+0x8000];
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@ -132,7 +123,7 @@ static READ8_HANDLER( hitpoker_cram_r )
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{
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UINT8 *ROM = memory_region(space->machine, "maincpu");
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if(hitpoker_sys_regs[0x00] & 0x10)
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if(hitpoker_pic_data & 0x10)
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return paletteram[offset];
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else
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return ROM[offset+0xbf00];
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@ -174,15 +165,37 @@ static READ8_HANDLER( rtc_r )
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return 0x80; //kludge it for now
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}
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static READ8_HANDLER( hitpoker_pic_r )
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{
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// logerror("R\n");
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if(cpu_get_pc(space->cpu) == 0x3143 ||
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cpu_get_pc(space->cpu) == 0x314e ||
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cpu_get_pc(space->cpu) == 0x3164 ||
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cpu_get_pc(space->cpu) == 0x3179)
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return hitpoker_pic_data;
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return (hitpoker_pic_data & 0x7f) | (hitpoker_pic_data & 0x40 ? 0x80 : 0x00);
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}
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static WRITE8_HANDLER( hitpoker_pic_w )
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{
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hitpoker_pic_data = (data & 0xff);// | (data & 0x40) ? 0x80 : 0x00;
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// logerror("%02x W\n",data);
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}
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/* overlap empty rom addresses */
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static ADDRESS_MAP_START( main_map, ADDRESS_SPACE_PROGRAM, 8 )
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AM_RANGE(0x0000, 0x00ff) AM_RAM // stack ram
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AM_RANGE(0x1000, 0x1000) AM_READWRITE(hitpoker_pic_r,hitpoker_pic_w) // protection
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AM_RANGE(0x1000, 0x103f) AM_RAM AM_BASE(&hitpoker_sys_regs) // hw regs?
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AM_RANGE(0x8000, 0xb5ff) AM_READWRITE(hitpoker_vram_r,hitpoker_vram_w)
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AM_RANGE(0xb600, 0xbdff) AM_RAM
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AM_RANGE(0xbe0c, 0xbe0c) AM_READNOP //irq ack?
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AM_RANGE(0xbe0d, 0xbe0d) AM_READ(rtc_r)
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// AM_RANGE(0xbe0a, 0xbe5f) AM_READ(test_r)
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AM_RANGE(0xbe80, 0xbe81) AM_WRITE(hitpoker_crtc_w)
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AM_RANGE(0xbe90, 0xbe91) AM_READWRITE(hitpoker_work_ram_r,hitpoker_work_ram_w) AM_BASE(&work_ram) //???
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AM_RANGE(0xbe90, 0xbe91) AM_DEVREADWRITE("ay", ay8910_r,ay8910_address_data_w)
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AM_RANGE(0xbea0, 0xbea0) AM_READ_PORT("VBLANK") //probably other bits as well
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AM_RANGE(0xc000, 0xefff) AM_READWRITE(hitpoker_cram_r,hitpoker_cram_w)
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AM_RANGE(0x0000, 0xbdff) AM_ROM
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@ -194,6 +207,9 @@ ADDRESS_MAP_END
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static INPUT_PORTS_START( hitpoker )
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PORT_START("VBLANK")
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PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) //scanline counter probably
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_VBLANK )
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INPUT_PORTS_END
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@ -235,6 +251,12 @@ static MACHINE_DRIVER_START( hitpoker )
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MDRV_VIDEO_START(hitpoker)
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MDRV_VIDEO_UPDATE(hitpoker)
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MDRV_SPEAKER_STANDARD_MONO("mono")
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MDRV_SOUND_ADD("ay", AY8910, 1500000)
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// MDRV_SOUND_CONFIG(ay8910_config)
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MDRV_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.50)
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MACHINE_DRIVER_END
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DRIVER_INIT(hitpoker)
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@ -273,7 +295,7 @@ DRIVER_INIT(hitpoker)
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ROM_START( hitpoker )
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ROM_REGION( 0x10000, "maincpu", 0 )
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ROM_LOAD( "u4.bin", 0x0000, 0x10000, CRC(0016497a) SHA1(017320bfe05fea8a48e26a66c0412415846cee7c) )
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ROM_LOAD( "u4.bin", 0x00000, 0x10000, CRC(0016497a) SHA1(017320bfe05fea8a48e26a66c0412415846cee7c) )
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ROM_REGION( 0x100000, "gfx1", 0 ) // tile 0x4c8 seems to contain something non-gfx related, could be tilemap / colour data, check!
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ROM_LOAD16_BYTE( "u42.bin", 0x00001, 0x40000, CRC(cbe56fec) SHA1(129bfd10243eaa7fb6a087f96de90228e6030353) )
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