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https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
completed Rx and serial interface handshake support
This commit is contained in:
Joakim Larsson Edstrom
parent
316ae121c7
commit
e0b8d253dc
@ -55,6 +55,7 @@ FEATURES
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#define LOG_DCD 0x200
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#define LOG_SYNC 0x400
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#define LOG_CHAR 0x800
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#define LOG_RX 0x1000
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#define VERBOSE 0 // (LOG_PRINTF | LOG_SETUP | LOG_GENERAL)
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@ -72,6 +73,7 @@ FEATURES
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#define LOGDCD(...) LOGMASK(LOG_DCD, __VA_ARGS__)
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#define LOGSYNC(...) LOGMASK(LOG_SYNC, __VA_ARGS__)
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#define LOGCHAR(...) LOGMASK(LOG_CHAR, __VA_ARGS__)
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#define LOGRX(...) LOGMASK(LOG_RX, __VA_ARGS__)
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#if VERBOSE & LOG_PRINTF
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#define logerror printf
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@ -274,6 +276,10 @@ void mpcc_device::device_reset()
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m_ccr = 0x00;
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m_ecr = 0x04;
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// Clear fifos
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m_tx_data_fifo.clear();
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m_rx_data_fifo.clear();
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// Init out callbacks to known inactive state
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m_out_txd_cb(1);
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m_out_dtr_cb(1);
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@ -292,6 +298,76 @@ void mpcc_device::device_timer(emu_timer &timer, device_timer_id id, int param,
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device_serial_interface::device_timer(timer, id, param, ptr);
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}
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WRITE_LINE_MEMBER(mpcc_device::cts_w)
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{
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if (state == CLEAR_LINE)
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{
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uint8_t old_sisr = m_sisr;
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m_sisr &= ~REG_SISR_CTSLVL;
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if ( (old_sisr & REG_SISR_CTSLVL) &&
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(m_sicr & REG_SICR_RTSLVL) &&
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(m_tcr & REG_TCR_TEN))
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{
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m_sisr |= REG_SISR_CTST;
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if (m_sier & REG_SIER_CTS)
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{
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// TODO: make sure interrupt is issued with the next negative transition of TxC
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trigger_interrupt(INT_SR_CTS);
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// TODO: Make sure TxC has negative transition after CTS goes inactive before INT can be reset in SISR7
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}
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}
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}
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else
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m_sisr |= REG_SISR_CTSLVL;
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}
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WRITE_LINE_MEMBER(mpcc_device::dsr_w)
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{
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if (state == ASSERT_LINE)
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{
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uint8_t old_sisr = m_sisr;
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m_sisr |= REG_SISR_DSRLVL;
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if ( !(old_sisr & REG_SISR_DSRLVL) &&
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!(m_rcr & REG_RCR_RRES))
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{
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m_sisr |= REG_SISR_DSRT;
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if (m_sier & REG_SIER_DSR)
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{
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// TODO: make sure interrupt is issued with the next negative transition of RxC
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trigger_interrupt(INT_SR_DSR);
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// TODO: Make sure RxC has negative transition after DSR goes inactive before INT can be reset in SISR6
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}
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}
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}
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else
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m_sisr &= ~REG_SISR_DSRLVL;
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}
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WRITE_LINE_MEMBER(mpcc_device::dcd_w)
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{
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if (state == CLEAR_LINE)
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{
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uint8_t old_sisr = m_sisr;
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m_sisr &= ~REG_SISR_DCDLVL;
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if ( (old_sisr & REG_SISR_DCDLVL) &&
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!(m_rcr & REG_RCR_RRES))
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{
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m_sisr |= REG_SISR_DCDT;
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if (m_sier & REG_SIER_DCD)
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{
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// TODO: make sure interrupt is issued with the next negative transition of RxC
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trigger_interrupt(INT_SR_DCD);
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// TODO: Make sure RxC has negative transition before INT can be reset in SISR5
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}
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}
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}
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else
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m_sisr |= REG_SISR_DCDLVL;
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}
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//-------------------------------------------------
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// get_brg_rate - helper function
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//-------------------------------------------------
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@ -430,7 +506,7 @@ void mpcc_device::update_serial()
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parity_t parity = get_parity();
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LOGSETUP(" %s() %s Setting data frame %d+%d%c%s\n", FUNCNAME, m_owner->tag(), 1,
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data_bits, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O',
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data_bits, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O',
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stop_bits == STOP_BITS_1 ? "1" : (stop_bits == STOP_BITS_2 ? "2" : "1.5"));
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set_data_frame(1, data_bits, parity, stop_bits);
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@ -439,16 +515,16 @@ void mpcc_device::update_serial()
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// check if the receiver is in reset mode
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if (m_rcr & REG_RCR_RRES)
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{
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LOG("- Rx in reset\n");
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LOGSETUP("- Rx in reset\n");
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set_rcv_rate(0);
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}
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// Rx is running
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else
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{
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LOG("- Rx enabled\n");
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LOGSETUP("- Rx enabled\n");
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m_brg_rate = get_rx_rate();
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LOG("- BRG rate %d\n", m_brg_rate);
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LOGSETUP("- BRG rate %d\n", m_brg_rate);
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set_rcv_rate(m_brg_rate);
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}
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@ -456,7 +532,7 @@ void mpcc_device::update_serial()
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// check if Rx is in reset
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if (m_tcr & REG_TCR_TRES)
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{
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LOG("- Tx in reset\n");
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LOGSETUP("- Tx in reset\n");
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set_tra_rate(0);
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}
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// Tx is running
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@ -465,15 +541,15 @@ void mpcc_device::update_serial()
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// Check that Tx is enabled
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if (m_tcr & REG_TCR_TEN)
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{
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LOG("- Tx enabled\n");
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LOGSETUP("- Tx enabled\n");
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m_brg_rate = get_tx_rate();
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LOG("- BRG rate %d\n", m_brg_rate);
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LOGSETUP("- BRG rate %d\n", m_brg_rate);
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set_tra_rate(m_brg_rate);
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}
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else
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{
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LOG("- Tx disabled\n");
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LOGSETUP("- Tx disabled\n");
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set_tra_rate(0);
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}
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}
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@ -532,6 +608,7 @@ void mpcc_device::tra_complete()
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else
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{
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m_out_rts_cb(CLEAR_LINE); // TODO: respect the RTSLV bit
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m_sicr &= ~REG_SICR_RTSLVL;
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}
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// Check if Tx interrupts are enabled
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@ -574,6 +651,7 @@ void mpcc_device::rcv_complete()
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receive_register_extract();
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data = get_received_char();
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LOGRX("%s %02x [%c]\n", FUNCNAME, isascii(data) ? data : ' ', data);
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// receive_data(data);
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if (m_rx_data_fifo.full())
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@ -706,7 +784,7 @@ READ8_MEMBER( mpcc_device::read )
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{
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case 0x00: data = do_rsr(); break;
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case 0x01: data = do_rcr(); break;
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case 0x02: data = m_rdr; logerror("MPCC: Reg RDR not implemented\n"); break;
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case 0x02: data = do_rdr(); break;
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case 0x04: data = m_rivnr; logerror("MPCC: Reg RIVNR not implemented\n"); break;
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case 0x05: data = do_rier(); break;
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case 0x08: data = m_tsr; break; logerror("MPCC: Reg TSR not implemented\n"); break;
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@ -714,7 +792,7 @@ READ8_MEMBER( mpcc_device::read )
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//case 0x0a: data = m_tdr; break; // TDR is a write only register
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case 0x0c: data = do_tivnr(); break;
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case 0x0d: data = do_tier(); break;
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case 0x10: data = m_sisr; logerror("MPCC: Reg SISR not implemented\n"); break;
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case 0x10: data = do_sisr(); break;
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case 0x11: data = do_sicr(); break;
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case 0x14: data = m_sivnr; logerror("MPCC: Reg SIVNR not implemented\n"); break;
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case 0x15: data = do_sier(); break;
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@ -750,7 +828,7 @@ WRITE8_MEMBER( mpcc_device::write )
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case 0x0a: m_tdr = data; LOGCHAR("*%c", data); do_tdr(data); break;
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case 0x0c: do_tivnr(data); break;
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case 0x0d: do_tier(data); break;
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case 0x10: m_sisr = data; logerror("MPCC: Reg SISR not implemented\n"); break;
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case 0x10: do_sisr(data); break;
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case 0x11: do_sicr(data); break;
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case 0x14: m_sivnr = data; logerror("MPCC: Reg SIVNR not implemented\n"); break;
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case 0x15: do_sier(data); break;
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@ -800,6 +878,26 @@ uint8_t mpcc_device::do_rcr()
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return data;
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}
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uint8_t mpcc_device::do_rdr()
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{
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uint8_t data = 0;
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if (!m_rx_data_fifo.empty())
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{
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// load data from the FIFO
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data = m_rx_data_fifo.dequeue();
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}
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else
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{
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LOGRX("data_read: Attempt to read out character from empty FIFO\n");
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logerror("data_read: Attempt to read out character from empty FIFO\n");
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}
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LOGRX("%s <- %02x [%c]\n", FUNCNAME, isascii(data) ? data : ' ', data);
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return data;
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}
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void mpcc_device::do_rier(uint8_t data)
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{
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LOG("%s -> %02x\n", FUNCNAME, data);
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@ -908,10 +1006,47 @@ uint8_t mpcc_device::do_tier()
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return data;
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}
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void mpcc_device::do_sisr(uint8_t data)
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{
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LOG("%s -> %02x\n", FUNCNAME, data);
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if (data & REG_SISR_CTST) m_sisr &= ~REG_SISR_CTST;
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if (data & REG_SISR_DSRT) m_sisr &= ~REG_SISR_DSRT;
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if (data & REG_SISR_DCDT) m_sisr &= ~REG_SISR_DCDT;
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LOGSETUP(" - CTS %d transitioned: %d\n", (m_sisr & REG_SISR_CTSLVL) ? 1 :0, (m_sisr & REG_SISR_CTST) ? 1 : 0);
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LOGSETUP(" - DSR %d transitioned: %d\n", (m_sisr & REG_SISR_DSRLVL) ? 1 :0, (m_sisr & REG_SISR_DSRT) ? 1 : 0);
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LOGSETUP(" - DCD %d transitioned: %d\n", (m_sisr & REG_SISR_DCDLVL) ? 1 :0, (m_sisr & REG_SISR_DCDT) ? 1 : 0);
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}
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uint8_t mpcc_device::do_sisr()
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{
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uint8_t data = m_sisr;
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LOG("%s <- %02x\n", FUNCNAME, data);
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return data;
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}
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void mpcc_device::do_sicr(uint8_t data)
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{
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LOG("%s -> %02x\n", FUNCNAME, data);
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// If RTS is activated the RTS output latch can only be reset by an empty FIFO.
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if ( !(m_sicr & REG_SICR_RTSLVL) &&
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(data & REG_SICR_RTSLVL))
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{
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m_out_rts_cb(ASSERT_LINE); // TODO: respect the RTSLV bit
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}
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m_sicr = data;
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if (m_sicr & REG_SICR_DTRLVL)
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{
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m_out_dtr_cb(ASSERT_LINE);
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}
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else
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{
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m_out_dtr_cb(CLEAR_LINE);
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}
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LOGSETUP(" - RTS level : %s\n", (m_sicr & REG_SICR_RTSLVL) ? "high" : "low");
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LOGSETUP(" - DTR level : %s\n", (m_sicr & REG_SICR_DTRLVL) ? "high" : "low");
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LOGSETUP(" - Echo Mode : %s\n", (m_sicr & REG_SICR_ECHO) ? "enabled" : "disabled");
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@ -120,9 +120,10 @@ public:
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DECLARE_READ8_MEMBER( iack );
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/* Callbacks to be called by others for signals driven by connected devices */
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DECLARE_WRITE_LINE_MEMBER( write_rx ); // bit transitions from serial device
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DECLARE_WRITE_LINE_MEMBER( cts_w ) {} // { m_chanA->cts_w(state); }
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DECLARE_WRITE_LINE_MEMBER( dcd_w ) {} // { m_chanA->dcd_w(state); }
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DECLARE_WRITE_LINE_MEMBER( write_rx );
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DECLARE_WRITE_LINE_MEMBER( cts_w );
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DECLARE_WRITE_LINE_MEMBER( dsr_w );
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DECLARE_WRITE_LINE_MEMBER( dcd_w );
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DECLARE_WRITE_LINE_MEMBER( rxc_w ) {} // { m_chanA->rxc_w(state); }
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DECLARE_WRITE_LINE_MEMBER( txc_w ) {} // { m_chanA->txc_w(state); }
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@ -249,6 +250,7 @@ protected:
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};
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uint8_t m_rdr;
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uint8_t do_rdr();
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// TODO: investigate if 4 x 16 bit wide FIFO is needed for 16 bit mode
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util::fifo<uint8_t, 8> m_rx_data_fifo;
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@ -318,7 +320,19 @@ protected:
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REG_TIER_TFERR = 0x02, // TX Frame error interrupt
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};
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// SISR - Serial Interface Status Register
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uint8_t m_sisr;
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uint8_t do_sisr();
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void do_sisr(uint8_t data);
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enum
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{
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REG_SISR_CTST = 0x80, // Clear To Send Transition Status
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REG_SISR_DSRT = 0x40, // Data Set Ready Transition Status
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REG_SISR_DCDT = 0x20, // Data Carrier Detect Transition Status
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REG_SISR_CTSLVL = 0x10, // Clear To Send Level
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REG_SISR_DSRLVL = 0x08, // Data Set Ready Level
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REG_SISR_DCDLVL = 0x04, // Data Carrier Detect Level
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};
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// SICR - Serial Interface Control Register
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uint8_t m_sicr;
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