From e0c4c04f0c6ac0f9e360bf932ba0746dfdb8ed48 Mon Sep 17 00:00:00 2001
From: Sandro Ronco <sandro.ronco@gmx.com>
Date: Tue, 1 Nov 2016 10:39:38 +0100
Subject: [PATCH] arm: fixed register-base shift with a value >= 32, this fixes
 the RISC OS graphics issues.

---
 src/devices/cpu/arm/arm.cpp | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/devices/cpu/arm/arm.cpp b/src/devices/cpu/arm/arm.cpp
index 0870d903f05..a51e1fd8882 100644
--- a/src/devices/cpu/arm/arm.cpp
+++ b/src/devices/cpu/arm/arm.cpp
@@ -1302,8 +1302,9 @@ uint32_t arm_cpu_device::decodeShift(uint32_t insn, uint32_t *pCarry)
 		if (ARM_DEBUG_CORE && (insn&0x80)==0x80)
 			logerror("%08x:  RegShift ERROR (p36)\n",R15);
 
-		//see p35 for check on this
-		k = GetRegister(k >> 1)&0x1f;
+		// Only the least significant byte of the contents of Rs is used to determine the shift amount
+		k = GetRegister(k >> 1) & 0xff;
+
 		m_icount -= S_CYCLE;
 		if( k == 0 ) /* Register shift by 0 is a no-op */
 		{
@@ -1316,7 +1317,13 @@ uint32_t arm_cpu_device::decodeShift(uint32_t insn, uint32_t *pCarry)
 	switch (t >> 1)
 	{
 	case 0:                     /* LSL */
-		if (pCarry)
+		if (k >= 32)
+		{
+			if (pCarry)
+				*pCarry = (k == 32) ? rm & 1 : 0;
+			return 0;
+		}
+		else if (pCarry)
 		{
 			*pCarry = k ? (rm & (1 << (32 - k))) : (R15 & C_MASK);
 		}