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Lucky Ball 96 updates: Banking, new sets, rebuild parent/clones,
inputs, demux, and a lot of work to get the game working properly [Roberto Fresca, Grull Osgo] New working machines -------------------- Lucky Ball 96 (Ver 4.01) [Roberto Fresca, Grull Osgo, Daniel Gallimberti] New working clones ------------------ Lucky Ball 96 (Ver 3.01) [Roberto Fresca, Grull Osgo, Daniel Gallimberti]
This commit is contained in:
Roberto Fresca
parent
d3bc15e45b
commit
e0d24d94c3
@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders: Roberto Fresca
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// copyright-holders: Roberto Fresca, Grull Osgo.
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/********************************************************************
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Lucky Ball 96.
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@ -8,14 +8,20 @@
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Copyright 1991/96 by Sielcon Games.
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Industria Argentina.
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Driver by Roberto Fresca.
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Driver by Roberto Fresca & Grull Osgo.
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Special thanks to Daniel Gallimberti (CEO of Sielcon Games, programmer
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and owner of this roulette machine) for allow the emulation, the inclu-
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sion in MAME, and the release of this game for non-profit purposes. :-)
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4 sets dumped:
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6 sets dumped:
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Version: 4.01 - Final?
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Version: 3.50 - 616
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Version: 3.50 - 623
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Version: 3.50 - 626
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Version: 3.50 - 627
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Version: 3.01
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Each set has:
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1x 64K program ROM (unknown CPU).
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@ -151,6 +157,7 @@
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D6 -> D7
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D7 -> D6
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*********************************************************************
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Notes:
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@ -164,16 +171,18 @@
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- Identified the DIL28 IC as ST6265 MCU.
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- Identified the DIL64 IC as Yamaha 9938/58 VDP.
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*********************************************************************
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Media files (27c4001)
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00000-085ff GFX
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08600-0ffff blank
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10000-7ffff samples
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00000-085ff GFX.
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08600-0ffff Blank.
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10000-7ffff Samples.
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Samples are 8-bit unsigned PCM.
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*********************************************************************
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I/O:
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@ -248,6 +257,7 @@
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| Q7 |-------> n.c.?
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'-----------'
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*********************************************************************
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Dev notes:
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@ -259,14 +269,11 @@
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written and the program keeps resetting when it can't read the
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outputs back).
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Currently the machine gets stuck polling the control register for
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the Z180's unemulated clocked serial I/O (which connects with the
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ST6265's SIN/SOUT/SCK).
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*********************************************************************/
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#define CPU_CLOCK XTAL(12'288'000)
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#define CPU_CLOCK XTAL(12'000'000)
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#define MCU_CLOCK XTAL(8'000'000)
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#define VID_CLOCK XTAL(21'477'272)
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@ -275,6 +282,7 @@
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#include "emu.h"
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#include "cpu/z180/z180.h"
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#include "machine/nvram.h"
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#include "machine/74259.h"
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#include "machine/i8255.h"
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#include "video/v9938.h"
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@ -282,6 +290,7 @@
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#include "sound/volt_reg.h"
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#include "screen.h"
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#include "speaker.h"
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#include "luckybal.lh"
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class luckybal_state : public driver_device
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@ -293,14 +302,20 @@ public:
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, m_maincpu(*this, "maincpu")
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, m_ppi(*this, "ppi")
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, m_dac(*this, "dac")
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, m_aux(*this, "AUX")
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, m_dsw(*this, "DSW")
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, m_latch(*this, "latch%u", 1)
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, m_lamps(*this, "lamp%u", 0U)
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{ }
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void luckybal(machine_config &config);
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void init_luckybal();
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void init_luckybala();
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void init_luckybalc();
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private:
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DECLARE_WRITE8_MEMBER(z180_trdr_w);
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DECLARE_WRITE8_MEMBER(port90_bitswap_w);
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DECLARE_READ8_MEMBER(ppi_bitswap_r);
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DECLARE_WRITE8_MEMBER(ppi_bitswap_w);
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@ -308,16 +323,23 @@ private:
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DECLARE_WRITE8_MEMBER(output_port_b_w);
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DECLARE_READ8_MEMBER(input_port_c_r);
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DECLARE_WRITE8_MEMBER(output_port_c_w);
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uint8_t daclatch;
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uint8_t m_trdr;
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uint8_t m_led_on = 0;
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required_device<v9938_device> m_v9938;
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required_device<cpu_device> m_maincpu;
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required_device<i8255_device> m_ppi;
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required_device<dac_byte_interface> m_dac;
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required_ioport m_aux;
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required_ioport m_dsw;
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required_device_array<cd4099_device, 3> m_latch;
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void main_io(address_map &map);
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void main_map(address_map &map);
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virtual void machine_start() override { m_lamps.resolve(); }
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output_finder<38> m_lamps;
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};
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@ -328,12 +350,23 @@ private:
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void luckybal_state::main_map(address_map &map)
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{
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map(0x0000, 0x57ff).rom();
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map(0xe000, 0xffff).ram(); // 6264 SRAM
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map(0x6000, 0x7fff).bankr("bank1"); // BANKED ROM
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map(0x8000, 0x9fff).bankr("bank1"); // BANKED ROM
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map(0xa000, 0xbfff).bankr("bank1"); // BANKED ROM
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map(0xc000, 0xdfff).bankr("bank1"); // BANKED ROM
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map(0xe000, 0xffff).ram().share("nvram"); // 6264 SRAM
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}
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void luckybal_state::main_io(address_map &map)
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{
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map.global_mask(0xff);
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map(0x00, 0x0a).nopr(); /* Z180 Internal registers */
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map(0x00, 0x0a).nopw(); /* Z180 Internal registers */
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map(0x0b, 0x0b).w(FUNC(luckybal_state::z180_trdr_w));
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map(0x0c, 0x3f).nopr(); /* Z180 Internal registers */
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map(0x0c, 0x3f).nopw(); /* Z180 Internal registers */
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map(0x90, 0x90).w(FUNC(luckybal_state::port90_bitswap_w));
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map(0xc0, 0xc3).rw(FUNC(luckybal_state::ppi_bitswap_r), FUNC(luckybal_state::ppi_bitswap_w));
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map(0xe0, 0xe3).rw(m_v9938, FUNC(v9938_device::read), FUNC(v9938_device::write));
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@ -387,11 +420,16 @@ M_MAP EQU 90H ; [A]= Bank to select (BIT6=MEM, BIT7=EN_NMI)
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/**************************************
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* R/W handlers *
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**************************************/
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WRITE8_MEMBER(luckybal_state::z180_trdr_w)
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{
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m_trdr = data;
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}
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WRITE8_MEMBER(luckybal_state::port90_bitswap_w)
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{
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data = bitswap<8>(data, 6, 7, 4, 5, 2, 3, 0, 1);
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logerror("%s: Write to port 90: %02X\n", machine().describe_context(), data);
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membank("bank1")->set_entry(data & 0x3f);
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//logerror("%s: Write to port 90: %02X\n", machine().describe_context(), data);
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}
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READ8_MEMBER(luckybal_state::ppi_bitswap_r)
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@ -406,12 +444,17 @@ WRITE8_MEMBER(luckybal_state::ppi_bitswap_w)
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WRITE8_MEMBER(luckybal_state::output_port_a_w)
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{
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daclatch = data;
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data = bitswap<8>(data, 0, 1, 2, 3, 4, 5, 6, 7);
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// DAC should be here.
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logerror("%s: Write to PPI port A: %02X\n", machine().describe_context(), data);
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if (m_trdr & 0x80)
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{
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m_trdr = m_trdr & 0x7f;
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if (m_trdr > 36) m_trdr = m_led_on; /* Prevents unexpected data */
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}
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m_lamps[m_led_on] = 0;
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m_lamps[m_trdr] = 1;
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m_led_on = m_trdr;
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m_dac->write(data);
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//logerror("%s: Write to PPI port A: %02X\n", machine().describe_context(), data);
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}
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WRITE8_MEMBER(luckybal_state::output_port_b_w)
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@ -420,14 +463,27 @@ WRITE8_MEMBER(luckybal_state::output_port_b_w)
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if (!BIT(data, n + 3))
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m_latch[n]->write_bit(data & 7, BIT(data, 6));
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if ((data & 0x80) != 0x80)
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logerror("%s: Write to PPI port B: %02X\n", machine().describe_context(), data);
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}
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READ8_MEMBER(luckybal_state::input_port_c_r)
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{
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//logerror("%s: Read from PPI port C\n", machine().describe_context());
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return 0xff;
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uint8_t mux_player, sel_line, bit5, bit6=0xff, bit7, ret;
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sel_line=m_ppi->read_pb() & 0x7f;
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mux_player = m_latch[0]->output_state();
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bit5 = (((m_aux->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xdf;
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switch(mux_player)
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{
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case 0xfe:bit6 = (((ioport("IN1")->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xbf; break;
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case 0xfd:bit6 = (((ioport("IN2")->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xbf; break;
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case 0xfb:bit6 = (((ioport("IN3")->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xbf; break;
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case 0xf7:bit6 = (((ioport("IN4")->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xbf; break;
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case 0xef:bit6 = (((ioport("IN5")->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xbf; break;
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case 0xdf:bit6 = (((ioport("IN6")->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0xbf; break;
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}
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bit7 = (((m_dsw->read() | (~(int)(pow(2, sel_line & 0x07)))) & 0xff ) == 0xff) ? 0xff : 0x7f;
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if ((sel_line & 0x07) == 6) m_lamps[37] = (bit5 == 0xff) ? 0 : 1; /* Operator lamp */
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ret = bit7 & bit6 & bit5;
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return ret;
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}
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WRITE8_MEMBER(luckybal_state::output_port_c_w)
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@ -442,79 +498,99 @@ WRITE8_MEMBER(luckybal_state::output_port_c_w)
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static INPUT_PORTS_START( luckybal )
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PORT_START("IN0")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_NAME("IN0-1")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_NAME("IN0-2")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_NAME("IN0-3")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_NAME("IN0-4")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_NAME("IN0-5")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_NAME("IN0-6")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_NAME("IN0-7")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_NAME("IN0-8")
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PORT_START("IN1")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) PORT_NAME("IN1-1")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("IN1-2")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_NAME("IN1-3")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_NAME("IN1-4")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_T) PORT_NAME("IN1-5")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("IN1-6")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("IN1-7")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_I) PORT_NAME("IN1-8")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1) PORT_NAME("Player 1 - Credits IN")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_W) PORT_NAME("Player 1 - Up")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Q) PORT_NAME("Player 1 - Bet")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) PORT_NAME("Player 1 - Credits OUT")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("Player 1 - Right")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("Player 1 - Down")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_E) PORT_NAME("Player 1 - Coin")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("Player 1 - Left")
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PORT_START("IN2")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_A) PORT_NAME("IN2-1")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("IN2-2")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_D) PORT_NAME("IN2-3")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F) PORT_NAME("IN2-4")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) PORT_NAME("IN2-5")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) PORT_NAME("IN2-6")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) PORT_NAME("IN2-7")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) PORT_NAME("IN2-8")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2) PORT_NAME("Player 2 - Credits IN")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_T) PORT_NAME("Player 2 - Up")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_R) PORT_NAME("Player 2 - Bet")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) PORT_NAME("Player 2 - Credits OUT")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_H) PORT_NAME("Player 2 - Right")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_G) PORT_NAME("Player 2 - Down")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Y) PORT_NAME("Player 2 - Coin")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_F) PORT_NAME("Player 2 - Left")
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PORT_START("IN3")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_Z) PORT_NAME("IN3-1")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_X) PORT_NAME("IN3-2")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) PORT_NAME("IN3-3")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("IN3-4")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("IN3-5")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) PORT_NAME("IN3-6")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_M) PORT_NAME("IN3-7")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) PORT_NAME("IN3-8")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3) PORT_NAME("Player 3 - Credits IN")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_S) PORT_NAME("Player 3 - Up")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_U) PORT_NAME("Player 3 - Bet")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_C) PORT_NAME("Player 3 - Credits OUT")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_L) PORT_NAME("Player 3 - Right")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_K) PORT_NAME("Player 3 - Down")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_O) PORT_NAME("Player 3 - Coin")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_J) PORT_NAME("Player 3 - Left")
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PORT_START("IN4")
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PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_1_PAD) PORT_NAME("IN4-1")
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PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("IN4-2")
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PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_3_PAD) PORT_NAME("IN4-3")
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PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("IN4-4")
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PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5_PAD) PORT_NAME("IN4-5")
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PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("IN4-6")
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PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("IN4-7")
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PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("IN4-8")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4) PORT_NAME("Player 4 - Credits IN")
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_PGUP) PORT_NAME("Player 4 - Up")
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LALT) PORT_NAME("Player 4 - Bet")
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_V) PORT_NAME("Player 4 - Credits OUT")
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7) PORT_NAME("Player 4 - Right")
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_PGDN) PORT_NAME("Player 4 - Down")
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_SPACE) PORT_NAME("Player 4 - Coin")
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8) PORT_NAME("Player 4 - Left")
|
||||
|
||||
PORT_START("DSW1")
|
||||
PORT_DIPNAME( 0x01, 0x01, "DSW1_01" )
|
||||
PORT_START("IN5")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_5) PORT_NAME("Player 5 - Credits IN")
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_DOWN) PORT_NAME("Player 5 - Up")
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LCONTROL) PORT_NAME("Player 5 - Bet")
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_B) PORT_NAME("Player 5 - Credits OUT")
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LEFT) PORT_NAME("Player 5 - Right")
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_UP) PORT_NAME("Player 5 - Down")
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_LALT) PORT_NAME("Player 5 - Coin")
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_RIGHT) PORT_NAME("Player 5 - Left")
|
||||
|
||||
PORT_START("IN6")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6) PORT_NAME("Player 6 - Credits IN")
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_8_PAD) PORT_NAME("Player 6 - Up")
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_7_PAD) PORT_NAME("Player 6 - Bet")
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_N) PORT_NAME("Player 6 - Credits OUT")
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_6_PAD) PORT_NAME("Player 6 - Right")
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_2_PAD) PORT_NAME("Player 6 - Down")
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("Player 6 - Coin")
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_4_PAD) PORT_NAME("Player 6 - Left")
|
||||
|
||||
PORT_START("AUX")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_0) PORT_NAME("Credit") PORT_TOGGLE
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_OTHER ) PORT_CODE(KEYCODE_9) PORT_NAME("Page")
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x01, 0x01, "Setting Access" )
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x02, 0x02, "DSW1_02" )
|
||||
PORT_DIPNAME( 0x02, 0x02, "Jackpot Enable" )
|
||||
PORT_DIPSETTING( 0x02, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x04, 0x04, "DSW1_04" )
|
||||
PORT_DIPNAME( 0x04, 0x04, "Partial Books Clear" )
|
||||
PORT_DIPSETTING( 0x04, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x08, 0x08, "DSW1_08" )
|
||||
PORT_DIPNAME( 0x08, 0x08, "Jackpot Mode" )
|
||||
PORT_DIPSETTING( 0x08, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x10, 0x10, "DSW1_10" )
|
||||
PORT_DIPNAME( 0x10, 0x10, "Coinage / Bet Mode" )
|
||||
PORT_DIPSETTING( 0x10, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x20, 0x20, "DSW1_20" )
|
||||
PORT_DIPNAME( 0x20, 0x20, "DSW_20" )
|
||||
PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x40, 0x40, "DSW1_40" )
|
||||
PORT_DIPNAME( 0x40, 0x40, "DSW_40" )
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
PORT_DIPNAME( 0x80, 0x80, "DSW1_80" )
|
||||
PORT_DIPNAME( 0x80, 0x80, "Full Books Clear" )
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( On ) )
|
||||
|
||||
@ -528,7 +604,7 @@ INPUT_PORTS_END
|
||||
MACHINE_CONFIG_START(luckybal_state::luckybal)
|
||||
|
||||
/* basic machine hardware */
|
||||
MCFG_DEVICE_ADD("maincpu", Z180, CPU_CLOCK)
|
||||
MCFG_DEVICE_ADD("maincpu", Z180, CPU_CLOCK / 2)
|
||||
MCFG_DEVICE_PROGRAM_MAP(main_map)
|
||||
MCFG_DEVICE_IO_MAP(main_io)
|
||||
|
||||
@ -544,6 +620,10 @@ MACHINE_CONFIG_START(luckybal_state::luckybal)
|
||||
|
||||
MCFG_DEVICE_ADD("latch3", CD4099, 0)
|
||||
|
||||
/* New: nvram added */
|
||||
//MCFG_NVRAM_ADD_0FILL("nvram")
|
||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||
|
||||
/* video hardware */
|
||||
MCFG_V9938_ADD("v9938", "screen", VDP_MEM, VID_CLOCK)
|
||||
MCFG_V99X8_INTERRUPT_CALLBACK(INPUTLINE("maincpu", 0))
|
||||
@ -562,39 +642,40 @@ MACHINE_CONFIG_END
|
||||
* ROM Load *
|
||||
**************************************/
|
||||
|
||||
ROM_START( luckybal ) // luckyball96 v350-627
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_START( luckybal ) // luckyball96 v4.01
|
||||
ROM_REGION( 0x90000, "maincpu", 0 )
|
||||
ROM_LOAD( "lb97_27c512_d2a1.u15", 0x00000, 0x10000, CRC(9bc6d417) SHA1(d414b389dca8dbebaac23c7f7c1338f57aa95c40) )
|
||||
ROM_LOAD( "lb97_27c4001_af7c.u20", 0x10000, 0x80000, CRC(de796370) SHA1(6edee4de330a65ad6b2dbe59c7ac0ddecb3ed0f1) )
|
||||
ROM_END
|
||||
|
||||
ROM_START( luckybala ) // luckyball96 v350-627
|
||||
ROM_REGION( 0x90000, "maincpu", 0 )
|
||||
ROM_LOAD( "lb97_627_m27c512.u15", 0x00000, 0x10000, CRC(c1bcffef) SHA1(da5db0ab0555cd98ff8e0206c1ee4ebd3d7447ef) )
|
||||
|
||||
ROM_REGION( 0x100000, "audiocpu", 0 )
|
||||
ROM_LOAD( "lb97_627_m27c4001.u20", 0x00000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_LOAD( "lb97_627_m27c4001.u20", 0x10000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_END
|
||||
|
||||
|
||||
ROM_START( luckybala ) // luckyball96 v350-626
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_START( luckybalb ) // luckyball96 v350-626
|
||||
ROM_REGION( 0x90000, "maincpu", 0 )
|
||||
ROM_LOAD( "lb97_626_m27c512.u15", 0x00000, 0x10000, CRC(d25588c1) SHA1(fc24b1e869d726d2e2ab8cd38ab6304fdca6dfa9) )
|
||||
|
||||
ROM_REGION( 0x100000, "audiocpu", 0 )
|
||||
ROM_LOAD( "lb96_sounds_001_m27c4001.u20", 0x00000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_LOAD( "lb96_sounds_001_m27c4001.u20", 0x10000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_END
|
||||
|
||||
|
||||
ROM_START( luckybalb ) // luckyball96 v350-623
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_START( luckybalc ) // luckyball96 v350-623
|
||||
ROM_REGION( 0x90000, "maincpu", 0 )
|
||||
ROM_LOAD( "lb96_625_m27c512.u15", 0x00000, 0x10000, CRC(2017edf7) SHA1(0208423b116aeb139c5db193b567bc79fd2a21ac) )
|
||||
|
||||
ROM_REGION( 0x100000, "audiocpu", 0 )
|
||||
ROM_LOAD( "lb96_625_m27c4001.u20", 0x00000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_LOAD( "lb96_625_m27c4001.u20", 0x10000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_END
|
||||
|
||||
|
||||
ROM_START( luckybalc ) // luckyball96 v350-616
|
||||
ROM_REGION( 0x10000, "maincpu", 0 )
|
||||
ROM_START( luckybald ) // luckyball96 v350-616
|
||||
ROM_REGION( 0x90000, "maincpu", 0 )
|
||||
ROM_LOAD( "nosticker_a18e_m27c512.u15", 0x00000, 0x10000, CRC(9bdf0243) SHA1(e353a86c4b020784d084c4fa12feb6ccd8ebd77b) )
|
||||
ROM_LOAD( "nosticker_af7c_m27c4001.u20", 0x10000, 0x80000, CRC(de796370) SHA1(6edee4de330a65ad6b2dbe59c7ac0ddecb3ed0f1) )
|
||||
ROM_END
|
||||
|
||||
ROM_REGION( 0x100000, "audiocpu", 0 )
|
||||
ROM_LOAD( "nosticker_af7c_m27c4001.u20", 0x00000, 0x80000, CRC(de796370) SHA1(6edee4de330a65ad6b2dbe59c7ac0ddecb3ed0f1) )
|
||||
ROM_START( luckybale ) // luckyball96 v3.01
|
||||
ROM_REGION( 0x90000, "maincpu", 0 )
|
||||
ROM_LOAD( "lb97_6235_f12b.u15", 0x00000, 0x10000, CRC(2d2837c0) SHA1(d42718f81fc46ed753665ba12bd4e0a8a75bff93) )
|
||||
ROM_LOAD( "lb97_6235_ac9c.u20", 0x10000, 0x80000, CRC(dbc45c4a) SHA1(720c6861fa2bfa9c9dad69d687f12bd1e0a71afb) )
|
||||
ROM_END
|
||||
|
||||
|
||||
@ -611,6 +692,58 @@ void luckybal_state::init_luckybal()
|
||||
{
|
||||
rom[i] = bitswap<8>(rom[i], 6, 7, 4, 5, 2, 3, 0, 1);
|
||||
}
|
||||
|
||||
membank("bank1")->configure_entries(0, 0x40, &rom[0x10000], 0x2000);
|
||||
}
|
||||
|
||||
void luckybal_state::init_luckybala()
|
||||
{
|
||||
uint8_t *rom = memregion("maincpu")->base();
|
||||
int size = memregion("maincpu")->bytes();
|
||||
int start = 0;
|
||||
for (int i = start; i < size; i++)
|
||||
{
|
||||
rom[i] = bitswap<8>(rom[i], 6, 7, 4, 5, 2, 3, 0, 1);
|
||||
}
|
||||
|
||||
/* HACK SECTION */
|
||||
rom[0x571] = 0x68; //31
|
||||
rom[0x572] = 0xE8; //4C
|
||||
rom[0x573] = 0x18; //42
|
||||
rom[0x574] = 0x98; //39
|
||||
rom[0x575] = 0x58; //36
|
||||
rom[0x16E1] = 0x0D; //OC
|
||||
rom[0x1D65] = 0x0E; //0C
|
||||
rom[0x4499] = 0x00; //FF <------- Checksum.
|
||||
rom[0x4AB6] = 0xAF; //B9
|
||||
/* END */
|
||||
|
||||
membank("bank1")->configure_entries(0, 0x40, &rom[0x10000], 0x2000);
|
||||
}
|
||||
|
||||
void luckybal_state::init_luckybalc()
|
||||
{
|
||||
uint8_t *rom = memregion("maincpu")->base();
|
||||
int size = memregion("maincpu")->bytes();
|
||||
int start = 0;
|
||||
for (int i = start; i < size; i++)
|
||||
{
|
||||
rom[i] = bitswap<8>(rom[i], 6, 7, 4, 5, 2, 3, 0, 1);
|
||||
}
|
||||
|
||||
/* HACK SECTION */
|
||||
rom[0x571] = 0x68; //31
|
||||
rom[0x572] = 0xE8; //4C
|
||||
rom[0x573] = 0x18; //42
|
||||
rom[0x574] = 0x98; //39
|
||||
rom[0x575] = 0x58; //36
|
||||
rom[0x16C1] = 0x0D; //OC
|
||||
rom[0x1D45] = 0x0E; //0C
|
||||
rom[0x44A9] = 0x00; //FF <------- Checksum.
|
||||
rom[0x4AC6] = 0xAF; //B9
|
||||
/* END */
|
||||
|
||||
membank("bank1")->configure_entries(0, 0x40, &rom[0x10000], 0x2000);
|
||||
}
|
||||
|
||||
|
||||
@ -618,8 +751,10 @@ void luckybal_state::init_luckybal()
|
||||
* Game Driver(s) *
|
||||
**************************************/
|
||||
|
||||
/* YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS */
|
||||
GAME( 1996, luckybal, 0, luckybal, luckybal, luckybal_state, init_luckybal, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 627)", MACHINE_NOT_WORKING )//| MACHINE_NO_SOUND )
|
||||
GAME( 1996, luckybala, luckybal, luckybal, luckybal, luckybal_state, init_luckybal, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 626)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 1996, luckybalb, luckybal, luckybal, luckybal, luckybal_state, init_luckybal, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 623)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
GAME( 1996, luckybalc, luckybal, luckybal, luckybal, luckybal_state, init_luckybal, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 616)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
// YEAR NAME PARENT MACHINE INPUT STATE INIT ROT COMPANY FULLNAME FLAGS LAYOUT
|
||||
GAMEL( 1999, luckybal, 0, luckybal, luckybal, luckybal_state, init_luckybal, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 4.01)" , MACHINE_SUPPORTS_SAVE, layout_luckybal)
|
||||
GAMEL( 1996, luckybala, luckybal, luckybal, luckybal, luckybal_state, init_luckybala, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 627)", MACHINE_SUPPORTS_SAVE, layout_luckybal)
|
||||
GAMEL( 1996, luckybalb, luckybal, luckybal, luckybal, luckybal_state, init_luckybala, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 626)", MACHINE_SUPPORTS_SAVE, layout_luckybal)
|
||||
GAMEL( 1996, luckybalc, luckybal, luckybal, luckybal, luckybal_state, init_luckybala, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 623)", MACHINE_SUPPORTS_SAVE, layout_luckybal)
|
||||
GAMEL( 1996, luckybald, luckybal, luckybal, luckybal, luckybal_state, init_luckybalc, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.50 - 616)", MACHINE_SUPPORTS_SAVE, layout_luckybal)
|
||||
GAMEL( 1996, luckybale, luckybal, luckybal, luckybal, luckybal_state, init_luckybal, ROT0, "Sielcon Games", "Lucky Ball 96 (Ver 3.01)" , MACHINE_SUPPORTS_SAVE, layout_luckybal)
|
||||
|
||||
@ -18200,10 +18200,12 @@ lucky74a // (c) 1988 Wing Co. Ltd
|
||||
lucky74b // (c) 1988 Wing Co. Ltd
|
||||
|
||||
@source:luckybal.cpp
|
||||
luckybal // (c) 1996 Sielcon Games
|
||||
luckybal // (c) 1999 Sielcon Games
|
||||
luckybala // (c) 1996 Sielcon Games
|
||||
luckybalb // (c) 1996 Sielcon Games
|
||||
luckybalc // (c) 1996 Sielcon Games
|
||||
luckybald // (c) 1996 Sielcon Games
|
||||
luckybale // (c) 1996 Sielcon Games
|
||||
|
||||
@source:lvcards.cpp
|
||||
lvcards // (c) 1985 Tehkan
|
||||
|
||||
Loading…
Reference in New Issue
Block a user