mirror of
https://github.com/holub/mame
synced 2025-07-02 16:49:22 +03:00
let's tidy up some scope (part 2 of evil plan)
This commit is contained in:
Vas Crabb
parent
dc67d94edb
commit
e0ff24b42b
@ -23,18 +23,81 @@ All rights reserved.
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#define ADDRESS_65816(A) ((A)&0xffffff)
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struct g65816_opcode_struct
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namespace {
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class g65816_opcode_struct
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{
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unsigned char name;
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public:
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const char *name() const
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{
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return s_opnames[unsigned(m_name)];
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}
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bool is_call() const
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{
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switch (m_name)
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{
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case op::JSR:
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case op::JSL:
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return true;
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default:
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return false;
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}
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}
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bool is_return() const
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{
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switch (m_name)
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{
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case op::RTI:
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case op::RTL:
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case op::RTS:
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return true;
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default:
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return false;
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}
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}
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static const g65816_opcode_struct &get(unsigned char ins)
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{
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return s_opcodes[ins];
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}
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unsigned char flag;
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unsigned char ea;
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protected:
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enum class op : unsigned
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{
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ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA ,
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BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX ,
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CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML ,
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JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA ,
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PEA , PEI , PER , PHA , PHB , PHD , PHK , PHP , PHX , PHY , PLA ,
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PLB , PLD , PLP , PLX , PLY , REP , ROL , ROR , RTI , RTL , RTS ,
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SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX ,
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TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY ,
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TYA , TYX , WAI , WDM , XBA , XCE
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};
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g65816_opcode_struct(op n, unsigned char f, unsigned char e)
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: flag(f)
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, ea(e)
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, m_name(n)
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{
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}
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op m_name;
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static const char *const s_opnames[];
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static const g65816_opcode_struct s_opcodes[256];
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};
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enum
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{
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IMP , ACC , RELB, RELW, IMM , A , AI , AL , ALX , AX , AXI ,
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AY , D , DI , DIY , DLI , DLIY, DX , DXI , DY , S , SIY ,
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SIG /*, MVN , MVP , PEA , PEI , PER */
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SIG , MVN , MVP , PEA , PEI , PER
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};
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enum
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@ -44,20 +107,7 @@ enum
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X /* check x bit */
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};
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enum
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{
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ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA ,
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BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX ,
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CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML ,
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JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA ,
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PEA , PEI , PER , PHA , PHB , PHD , PHK , PHP , PHX , PHY , PLA ,
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PLB , PLD , PLP , PLX , PLY , REP , ROL , ROR , RTI , RTL , RTS ,
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SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX ,
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TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY ,
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TYA , TYX , WAI , WDM , XBA , XCE
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};
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static const char *const g_opnames[] =
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const char *const g65816_opcode_struct::s_opnames[] =
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{
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"ADC", "AND", "ASL", "BCC", "BCS", "BEQ", "BIT", "BMI", "BNE", "BPL", "BRA",
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"BRK", "BRL", "BVC", "BVS", "CLC", "CLD", "CLI", "CLV", "CMP", "COP", "CPX",
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@ -70,74 +120,76 @@ static const char *const g_opnames[] =
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"TYA", "TYX", "WAI", "WDM", "XBA", "XCE"
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};
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static const g65816_opcode_struct g_opcodes[256] =
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const g65816_opcode_struct g65816_opcode_struct::s_opcodes[256] =
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{
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{BRK, I, SIG }, {ORA, M, DXI }, {COP, I, SIG }, {ORA, M, S },
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{TSB, M, D }, {ORA, M, D }, {ASL, M, D }, {ORA, M, DLI },
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{PHP, I, IMP }, {ORA, M, IMM }, {ASL, M, ACC }, {PHD, I, IMP },
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{TSB, M, A }, {ORA, M, A }, {ASL, M, A }, {ORA, M, AL },
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{BPL, I, RELB}, {ORA, M, DIY }, {ORA, M, DI }, {ORA, M, SIY },
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{TRB, M, D }, {ORA, M, DX }, {ASL, M, DX }, {ORA, M, DLIY},
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{CLC, I, IMP }, {ORA, M, AY }, {INA, I, IMP }, {TCS, I, IMP },
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{TRB, M, A }, {ORA, M, AX }, {ASL, M, AX }, {ORA, M, ALX },
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{JSR, I, A }, {AND, M, DXI }, {JSL, I, AL }, {AND, M, S },
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{BIT, M, D }, {AND, M, D }, {ROL, M, D }, {AND, M, DLI },
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{PLP, I, IMP }, {AND, M, IMM }, {ROL, M, ACC }, {PLD, I, IMP },
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{BIT, M, A }, {AND, M, A }, {ROL, M, A }, {AND, M, AL },
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{BMI, I, RELB}, {AND, M, DIY }, {AND, M, DI }, {AND, M, SIY },
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{BIT, M, DX }, {AND, M, DX }, {ROL, M, DX }, {AND, M, DLIY},
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{SEC, I, IMP }, {AND, M, AY }, {DEA, I, IMP }, {TSC, I, IMP },
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{BIT, M, AX }, {AND, M, AX }, {ROL, M, AX }, {AND, M, ALX },
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{RTI, I, IMP }, {EOR, M, DXI }, {WDM, I, IMP }, {EOR, M, S },
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{MVP, I, MVP }, {EOR, M, D }, {LSR, M, D }, {EOR, M, DLI },
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{PHA, I, IMP }, {EOR, M, IMM }, {LSR, M, ACC }, {PHK, I, IMP },
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{JMP, I, A }, {EOR, M, A }, {LSR, M, A }, {EOR, M, AL },
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{BVC, I, RELB}, {EOR, M, DIY }, {EOR, M, DI }, {EOR, M, SIY },
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{MVN, I, MVN }, {EOR, M, DX }, {LSR, M, DX }, {EOR, M, DLIY},
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{CLI, I, IMP }, {EOR, M, AY }, {PHY, I, IMP }, {TCD, I, IMP },
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{JMP, I, AL }, {EOR, M, AX }, {LSR, M, AX }, {EOR, M, ALX },
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{RTS, I, IMP }, {ADC, M, DXI }, {PER, I, PER }, {ADC, M, S },
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{STZ, M, D }, {ADC, M, D }, {ROR, M, D }, {ADC, M, DLI },
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{PLA, I, IMP }, {ADC, M, IMM }, {ROR, M, ACC }, {RTL, I, IMP },
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{JMP, I, AI }, {ADC, M, A }, {ROR, M, A }, {ADC, M, AL },
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{BVS, I, RELB}, {ADC, M, DIY }, {ADC, M, DI }, {ADC, M, SIY },
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{STZ, M, DX }, {ADC, M, DX }, {ROR, M, DX }, {ADC, M, DLIY},
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{SEI, I, IMP }, {ADC, M, AY }, {PLY, I, IMP }, {TDC, I, IMP },
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{JMP, I, AXI }, {ADC, M, AX }, {ROR, M, AX }, {ADC, M, ALX },
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{BRA, I, RELB}, {STA, M, DXI }, {BRL, I, RELW}, {STA, M, S },
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{STY, X, D }, {STA, M, D }, {STX, X, D }, {STA, M, DLI },
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{DEY, I, IMP }, {BIT, M, IMM }, {TXA, I, IMP }, {PHB, I, IMP },
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{STY, X, A }, {STA, M, A }, {STX, X, A }, {STA, M, AL },
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{BCC, I, RELB}, {STA, M, DIY }, {STA, M, DI }, {STA, M, SIY },
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{STY, X, DX }, {STA, M, DX }, {STX, X, DY }, {STA, M, DLIY},
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{TYA, I, IMP }, {STA, M, AY }, {TXS, I, IMP }, {TXY, I, IMP },
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{STZ, M, A }, {STA, M, AX }, {STZ, M, AX }, {STA, M, ALX },
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{LDY, X, IMM }, {LDA, M, DXI }, {LDX, X, IMM }, {LDA, M, S },
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{LDY, X, D }, {LDA, M, D }, {LDX, X, D }, {LDA, M, DLI },
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{TAY, I, IMP }, {LDA, M, IMM }, {TAX, I, IMP }, {PLB, I, IMP },
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{LDY, X, A }, {LDA, M, A }, {LDX, X, A }, {LDA, M, AL },
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{BCS, I, RELB}, {LDA, M, DIY }, {LDA, M, DI }, {LDA, M, SIY },
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{LDY, X, DX }, {LDA, M, DX }, {LDX, X, DY }, {LDA, M, DLIY},
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{CLV, I, IMP }, {LDA, M, AY }, {TSX, I, IMP }, {TYX, I, IMP },
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{LDY, X, AX }, {LDA, M, AX }, {LDX, X, AY }, {LDA, M, ALX },
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{CPY, X, IMM }, {CMP, M, DXI }, {REP, I, IMM }, {CMP, M, S },
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{CPY, X, D }, {CMP, M, D }, {DEC, M, D }, {CMP, M, DLI },
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{INY, I, IMP }, {CMP, M, IMM }, {DEX, I, IMP }, {WAI, I, IMP },
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{CPY, X, A }, {CMP, M, A }, {DEC, M, A }, {CMP, M, AL },
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{BNE, I, RELB}, {CMP, M, DIY }, {CMP, M, DI }, {CMP, M, SIY },
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{PEI, I, PEI }, {CMP, M, DX }, {DEC, M, DX }, {CMP, M, DLIY},
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{CLD, I, IMP }, {CMP, M, AY }, {PHX, I, IMP }, {STP, I, IMP },
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{JML, I, AI }, {CMP, M, AX }, {DEC, M, AX }, {CMP, M, ALX },
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{CPX, X, IMM }, {SBC, M, DXI }, {SEP, I, IMM }, {SBC, M, S },
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{CPX, X, D }, {SBC, M, D }, {INC, M, D }, {SBC, M, DLI },
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{INX, M, IMP }, {SBC, M, IMM }, {NOP, I, IMP }, {XBA, I, IMP },
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{CPX, X, A }, {SBC, M, A }, {INC, M, A }, {SBC, M, AL },
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{BEQ, I, RELB}, {SBC, M, DIY }, {SBC, M, DI }, {SBC, M, SIY },
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{PEA, I, PEA }, {SBC, M, DX }, {INC, M, DX }, {SBC, M, DLIY},
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{SED, I, IMP }, {SBC, M, AY }, {PLX, I, IMP }, {XCE, I, IMP },
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{JSR, I, AXI }, {SBC, M, AX }, {INC, M, AX }, {SBC, M, ALX }
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{op::BRK, I, SIG }, {op::ORA, M, DXI }, {op::COP, I, SIG }, {op::ORA, M, S },
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{op::TSB, M, D }, {op::ORA, M, D }, {op::ASL, M, D }, {op::ORA, M, DLI },
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{op::PHP, I, IMP }, {op::ORA, M, IMM }, {op::ASL, M, ACC }, {op::PHD, I, IMP },
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{op::TSB, M, A }, {op::ORA, M, A }, {op::ASL, M, A }, {op::ORA, M, AL },
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{op::BPL, I, RELB}, {op::ORA, M, DIY }, {op::ORA, M, DI }, {op::ORA, M, SIY },
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{op::TRB, M, D }, {op::ORA, M, DX }, {op::ASL, M, DX }, {op::ORA, M, DLIY},
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{op::CLC, I, IMP }, {op::ORA, M, AY }, {op::INA, I, IMP }, {op::TCS, I, IMP },
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{op::TRB, M, A }, {op::ORA, M, AX }, {op::ASL, M, AX }, {op::ORA, M, ALX },
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{op::JSR, I, A }, {op::AND, M, DXI }, {op::JSL, I, AL }, {op::AND, M, S },
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{op::BIT, M, D }, {op::AND, M, D }, {op::ROL, M, D }, {op::AND, M, DLI },
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{op::PLP, I, IMP }, {op::AND, M, IMM }, {op::ROL, M, ACC }, {op::PLD, I, IMP },
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{op::BIT, M, A }, {op::AND, M, A }, {op::ROL, M, A }, {op::AND, M, AL },
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{op::BMI, I, RELB}, {op::AND, M, DIY }, {op::AND, M, DI }, {op::AND, M, SIY },
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{op::BIT, M, DX }, {op::AND, M, DX }, {op::ROL, M, DX }, {op::AND, M, DLIY},
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{op::SEC, I, IMP }, {op::AND, M, AY }, {op::DEA, I, IMP }, {op::TSC, I, IMP },
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{op::BIT, M, AX }, {op::AND, M, AX }, {op::ROL, M, AX }, {op::AND, M, ALX },
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{op::RTI, I, IMP }, {op::EOR, M, DXI }, {op::WDM, I, IMP }, {op::EOR, M, S },
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{op::MVP, I, MVP }, {op::EOR, M, D }, {op::LSR, M, D }, {op::EOR, M, DLI },
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{op::PHA, I, IMP }, {op::EOR, M, IMM }, {op::LSR, M, ACC }, {op::PHK, I, IMP },
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{op::JMP, I, A }, {op::EOR, M, A }, {op::LSR, M, A }, {op::EOR, M, AL },
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{op::BVC, I, RELB}, {op::EOR, M, DIY }, {op::EOR, M, DI }, {op::EOR, M, SIY },
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{op::MVN, I, MVN }, {op::EOR, M, DX }, {op::LSR, M, DX }, {op::EOR, M, DLIY},
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{op::CLI, I, IMP }, {op::EOR, M, AY }, {op::PHY, I, IMP }, {op::TCD, I, IMP },
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{op::JMP, I, AL }, {op::EOR, M, AX }, {op::LSR, M, AX }, {op::EOR, M, ALX },
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{op::RTS, I, IMP }, {op::ADC, M, DXI }, {op::PER, I, PER }, {op::ADC, M, S },
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{op::STZ, M, D }, {op::ADC, M, D }, {op::ROR, M, D }, {op::ADC, M, DLI },
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{op::PLA, I, IMP }, {op::ADC, M, IMM }, {op::ROR, M, ACC }, {op::RTL, I, IMP },
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{op::JMP, I, AI }, {op::ADC, M, A }, {op::ROR, M, A }, {op::ADC, M, AL },
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{op::BVS, I, RELB}, {op::ADC, M, DIY }, {op::ADC, M, DI }, {op::ADC, M, SIY },
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{op::STZ, M, DX }, {op::ADC, M, DX }, {op::ROR, M, DX }, {op::ADC, M, DLIY},
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{op::SEI, I, IMP }, {op::ADC, M, AY }, {op::PLY, I, IMP }, {op::TDC, I, IMP },
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{op::JMP, I, AXI }, {op::ADC, M, AX }, {op::ROR, M, AX }, {op::ADC, M, ALX },
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{op::BRA, I, RELB}, {op::STA, M, DXI }, {op::BRL, I, RELW}, {op::STA, M, S },
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{op::STY, X, D }, {op::STA, M, D }, {op::STX, X, D }, {op::STA, M, DLI },
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{op::DEY, I, IMP }, {op::BIT, M, IMM }, {op::TXA, I, IMP }, {op::PHB, I, IMP },
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{op::STY, X, A }, {op::STA, M, A }, {op::STX, X, A }, {op::STA, M, AL },
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{op::BCC, I, RELB}, {op::STA, M, DIY }, {op::STA, M, DI }, {op::STA, M, SIY },
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{op::STY, X, DX }, {op::STA, M, DX }, {op::STX, X, DY }, {op::STA, M, DLIY},
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{op::TYA, I, IMP }, {op::STA, M, AY }, {op::TXS, I, IMP }, {op::TXY, I, IMP },
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{op::STZ, M, A }, {op::STA, M, AX }, {op::STZ, M, AX }, {op::STA, M, ALX },
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{op::LDY, X, IMM }, {op::LDA, M, DXI }, {op::LDX, X, IMM }, {op::LDA, M, S },
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{op::LDY, X, D }, {op::LDA, M, D }, {op::LDX, X, D }, {op::LDA, M, DLI },
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{op::TAY, I, IMP }, {op::LDA, M, IMM }, {op::TAX, I, IMP }, {op::PLB, I, IMP },
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{op::LDY, X, A }, {op::LDA, M, A }, {op::LDX, X, A }, {op::LDA, M, AL },
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{op::BCS, I, RELB}, {op::LDA, M, DIY }, {op::LDA, M, DI }, {op::LDA, M, SIY },
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{op::LDY, X, DX }, {op::LDA, M, DX }, {op::LDX, X, DY }, {op::LDA, M, DLIY},
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{op::CLV, I, IMP }, {op::LDA, M, AY }, {op::TSX, I, IMP }, {op::TYX, I, IMP },
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{op::LDY, X, AX }, {op::LDA, M, AX }, {op::LDX, X, AY }, {op::LDA, M, ALX },
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{op::CPY, X, IMM }, {op::CMP, M, DXI }, {op::REP, I, IMM }, {op::CMP, M, S },
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{op::CPY, X, D }, {op::CMP, M, D }, {op::DEC, M, D }, {op::CMP, M, DLI },
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{op::INY, I, IMP }, {op::CMP, M, IMM }, {op::DEX, I, IMP }, {op::WAI, I, IMP },
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{op::CPY, X, A }, {op::CMP, M, A }, {op::DEC, M, A }, {op::CMP, M, AL },
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{op::BNE, I, RELB}, {op::CMP, M, DIY }, {op::CMP, M, DI }, {op::CMP, M, SIY },
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{op::PEI, I, PEI }, {op::CMP, M, DX }, {op::DEC, M, DX }, {op::CMP, M, DLIY},
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{op::CLD, I, IMP }, {op::CMP, M, AY }, {op::PHX, I, IMP }, {op::STP, I, IMP },
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{op::JML, I, AI }, {op::CMP, M, AX }, {op::DEC, M, AX }, {op::CMP, M, ALX },
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{op::CPX, X, IMM }, {op::SBC, M, DXI }, {op::SEP, I, IMM }, {op::SBC, M, S },
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{op::CPX, X, D }, {op::SBC, M, D }, {op::INC, M, D }, {op::SBC, M, DLI },
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{op::INX, M, IMP }, {op::SBC, M, IMM }, {op::NOP, I, IMP }, {op::XBA, I, IMP },
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{op::CPX, X, A }, {op::SBC, M, A }, {op::INC, M, A }, {op::SBC, M, AL },
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{op::BEQ, I, RELB}, {op::SBC, M, DIY }, {op::SBC, M, DI }, {op::SBC, M, SIY },
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{op::PEA, I, PEA }, {op::SBC, M, DX }, {op::INC, M, DX }, {op::SBC, M, DLIY},
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{op::SED, I, IMP }, {op::SBC, M, AY }, {op::PLX, I, IMP }, {op::XCE, I, IMP },
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{op::JSR, I, AXI }, {op::SBC, M, AX }, {op::INC, M, AX }, {op::SBC, M, ALX }
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};
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} // anonymous namespace
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static const UINT8 *base_oprom;
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static UINT32 base_pc;
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@ -206,28 +258,17 @@ unsigned g65816_disassemble(char* buff, unsigned int pc, unsigned int pb, const
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base_pc = address;
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instruction = read_8(address);
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opcode = g_opcodes + instruction;
|
||||
opcode = &g65816_opcode_struct::get(instruction);
|
||||
|
||||
strcpy(buff, g_opnames[opcode->name]);
|
||||
strcpy(buff, opcode->name());
|
||||
ptr = buff + strlen(buff);
|
||||
|
||||
switch(opcode->name)
|
||||
{
|
||||
case JSR:
|
||||
case JSL:
|
||||
dasm_flags = DASMFLAG_STEP_OVER;
|
||||
break;
|
||||
|
||||
case RTI:
|
||||
case RTL:
|
||||
case RTS:
|
||||
dasm_flags = DASMFLAG_STEP_OUT;
|
||||
break;
|
||||
|
||||
default:
|
||||
dasm_flags = 0;
|
||||
break;
|
||||
}
|
||||
if (opcode->is_call())
|
||||
dasm_flags = DASMFLAG_STEP_OVER;
|
||||
else if (opcode->is_return())
|
||||
dasm_flags = DASMFLAG_STEP_OUT;
|
||||
else
|
||||
dasm_flags = 0;
|
||||
|
||||
switch(opcode->ea)
|
||||
{
|
||||
|
||||
@ -13,82 +13,100 @@
|
||||
|
||||
#include "lh5801.h"
|
||||
|
||||
enum Adr
|
||||
{
|
||||
Imp,
|
||||
Reg,
|
||||
Vec, // imm byte (vector at 0xffxx)
|
||||
Vej,
|
||||
Imm,
|
||||
RegImm,
|
||||
Imm16,
|
||||
RegImm16,
|
||||
ME0,
|
||||
ME0Imm,
|
||||
Abs,
|
||||
AbsImm,
|
||||
ME1,
|
||||
ME1Imm,
|
||||
ME1Abs,
|
||||
ME1AbsImm,
|
||||
RelP,
|
||||
RelM
|
||||
};
|
||||
|
||||
enum Regs
|
||||
{
|
||||
RegNone,
|
||||
A,
|
||||
XL, XH, X,
|
||||
YL, YH, Y,
|
||||
UL, UH, U,
|
||||
P, S
|
||||
};
|
||||
|
||||
static const char *const RegNames[]= {
|
||||
nullptr, "A", "XL", "XH", "X", "YL", "YH", "Y", "UL", "UH", "U", "P", "S"
|
||||
};
|
||||
|
||||
#if defined(SEC)
|
||||
#undef SEC
|
||||
#endif
|
||||
|
||||
enum Ins
|
||||
namespace {
|
||||
|
||||
class Entry
|
||||
{
|
||||
ILL, ILL2, PREFD, NOP,
|
||||
public:
|
||||
enum Ins
|
||||
{
|
||||
ILL, ILL2, PREFD, NOP,
|
||||
|
||||
LDA, STA, LDI, LDX, STX,
|
||||
LDE, SDE, LIN, SIN,
|
||||
TIN, // (x++)->(y++)
|
||||
ADC, ADI, ADR, SBC, SBI,
|
||||
DCA, DCS, // bcd add and sub
|
||||
CPA, CPI, CIN, // A compared with (x++)
|
||||
AND, ANI, ORA, ORI, EOR, EAI, BIT, BII,
|
||||
INC, DEC,
|
||||
DRL, DRR, // digit rotates
|
||||
ROL, ROR,
|
||||
SHL, SHR,
|
||||
AEX, // A nibble swap
|
||||
LDA, STA, LDI, LDX, STX,
|
||||
LDE, SDE, LIN, SIN,
|
||||
TIN, // (x++)->(y++)
|
||||
ADC, ADI, ADR, SBC, SBI,
|
||||
DCA, DCS, // bcd add and sub
|
||||
CPA, CPI, CIN, // A compared with (x++)
|
||||
AND, ANI, ORA, ORI, EOR, EAI, BIT, BII,
|
||||
INC, DEC,
|
||||
DRL, DRR, // digit rotates
|
||||
ROL, ROR,
|
||||
SHL, SHR,
|
||||
AEX, // A nibble swap
|
||||
|
||||
BCR, BCS, BHR, BHS, BZR, BZS, BVR, BVS,
|
||||
BCH, LOP, // loop with ul
|
||||
JMP, SJP, RTN, RTI, HLT,
|
||||
VCR, VCS, VHR, VHS, VVS, VZR, VZS,
|
||||
VMJ, VEJ,
|
||||
PSH, POP, ATT, TTA,
|
||||
REC, SEC, RIE, SIE,
|
||||
BCR, BCS, BHR, BHS, BZR, BZS, BVR, BVS,
|
||||
BCH, LOP, // loop with ul
|
||||
JMP, SJP, RTN, RTI, HLT,
|
||||
VCR, VCS, VHR, VHS, VVS, VZR, VZS,
|
||||
VMJ, VEJ,
|
||||
PSH, POP, ATT, TTA,
|
||||
REC, SEC, RIE, SIE,
|
||||
|
||||
AM0, AM1, // load timer reg
|
||||
ITA, // reads input port
|
||||
ATP, // akku send to data bus
|
||||
CDV, // clears internal divider
|
||||
OFF, // clears bf flip flop
|
||||
RDP, SDP,// reset display flip flop
|
||||
RPU, SPU,// flip flop pu off
|
||||
RPV, SPV // flip flop pv off
|
||||
AM0, AM1, // load timer reg
|
||||
ITA, // reads input port
|
||||
ATP, // akku send to data bus
|
||||
CDV, // clears internal divider
|
||||
OFF, // clears bf flip flop
|
||||
RDP, SDP,// reset display flip flop
|
||||
RPU, SPU,// flip flop pu off
|
||||
RPV, SPV // flip flop pv off
|
||||
};
|
||||
|
||||
enum Adr
|
||||
{
|
||||
Imp,
|
||||
Reg,
|
||||
Vec, // imm byte (vector at 0xffxx)
|
||||
Vej,
|
||||
Imm,
|
||||
RegImm,
|
||||
Imm16,
|
||||
RegImm16,
|
||||
ME0,
|
||||
ME0Imm,
|
||||
Abs,
|
||||
AbsImm,
|
||||
ME1,
|
||||
ME1Imm,
|
||||
ME1Abs,
|
||||
ME1AbsImm,
|
||||
RelP,
|
||||
RelM
|
||||
};
|
||||
|
||||
enum Regs
|
||||
{
|
||||
RegNone,
|
||||
A,
|
||||
XL, XH, X,
|
||||
YL, YH, Y,
|
||||
UL, UH, U,
|
||||
P, S
|
||||
};
|
||||
|
||||
const char *ins_name() const { return ins_names[ins]; }
|
||||
const char *reg_name() const { return reg_names[reg]; }
|
||||
|
||||
Ins ins;
|
||||
Adr adr;
|
||||
Regs reg;
|
||||
|
||||
static const Entry table[0x100];
|
||||
static const Entry table_fd[0x100];
|
||||
|
||||
protected:
|
||||
Entry(Ins i, Adr a = Imp, Regs r = RegNone) : ins(i), adr(a), reg(r) { }
|
||||
|
||||
static const char *const ins_names[];
|
||||
static const char *const reg_names[];
|
||||
};
|
||||
|
||||
static const char *const InsNames[]={
|
||||
const char *const Entry::ins_names[]={
|
||||
"ILL", "ILL", nullptr, "NOP",
|
||||
"LDA", "STA", "LDI", "LDX", "STX",
|
||||
"LDE", "SDE", "LIN", "SIN",
|
||||
@ -120,9 +138,11 @@ static const char *const InsNames[]={
|
||||
"RPV", "SPV",
|
||||
};
|
||||
|
||||
struct Entry { Ins ins; Adr adr; Regs reg; };
|
||||
const char *const Entry::reg_names[]= {
|
||||
nullptr, "A", "XL", "XH", "X", "YL", "YH", "Y", "UL", "UH", "U", "P", "S"
|
||||
};
|
||||
|
||||
static const Entry table[0x100]={
|
||||
const Entry Entry::table[0x100]={
|
||||
{ SBC, Reg, XL }, // 0
|
||||
{ SBC, ME0, X },
|
||||
{ ADC, Reg, XL },
|
||||
@ -380,7 +400,8 @@ static const Entry table[0x100]={
|
||||
{ ILL },
|
||||
{ ILL }
|
||||
};
|
||||
static const Entry table_fd[0x100]={
|
||||
|
||||
const Entry Entry::table_fd[0x100]={
|
||||
{ ILL2 }, // 0x00
|
||||
{ SBC, ME1, X },
|
||||
{ ILL2 },
|
||||
@ -639,6 +660,9 @@ static const Entry table_fd[0x100]={
|
||||
{ ILL2 }
|
||||
};
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
CPU_DISASSEMBLE( lh5801 )
|
||||
{
|
||||
int pos = 0;
|
||||
@ -648,75 +672,75 @@ CPU_DISASSEMBLE( lh5801 )
|
||||
int temp;
|
||||
|
||||
oper=oprom[pos++];
|
||||
entry=table+oper;
|
||||
entry=Entry::table+oper;
|
||||
|
||||
if (table[oper].ins==PREFD) {
|
||||
if (Entry::table[oper].ins==Entry::PREFD) {
|
||||
oper=oprom[pos++];
|
||||
entry=table_fd+oper;
|
||||
entry=Entry::table_fd+oper;
|
||||
}
|
||||
switch (entry->ins) {
|
||||
case ILL:
|
||||
sprintf(buffer,"%s %.2x", InsNames[entry->ins], oper);break;
|
||||
case ILL2:
|
||||
sprintf(buffer,"%s fd%.2x", InsNames[entry->ins], oper);break;
|
||||
case Entry::ILL:
|
||||
sprintf(buffer,"%s %.2x", entry->ins_name(), oper);break;
|
||||
case Entry::ILL2:
|
||||
sprintf(buffer,"%s fd%.2x", entry->ins_name(), oper);break;
|
||||
default:
|
||||
switch(entry->adr) {
|
||||
case Imp:
|
||||
sprintf(buffer,"%s", InsNames[entry->ins]);break;
|
||||
case Reg:
|
||||
sprintf(buffer,"%s %s", InsNames[entry->ins],RegNames[entry->reg]);break;
|
||||
case RegImm:
|
||||
sprintf(buffer,"%s %s,%.2x", InsNames[entry->ins],
|
||||
RegNames[entry->reg], oprom[pos++]);
|
||||
case Entry::Imp:
|
||||
sprintf(buffer,"%s", entry->ins_name());break;
|
||||
case Entry::Reg:
|
||||
sprintf(buffer,"%s %s", entry->ins_name(),entry->reg_name());break;
|
||||
case Entry::RegImm:
|
||||
sprintf(buffer,"%s %s,%.2x", entry->ins_name(),
|
||||
entry->reg_name(), oprom[pos++]);
|
||||
break;
|
||||
case RegImm16:
|
||||
case Entry::RegImm16:
|
||||
absolut=oprom[pos++]<<8;
|
||||
absolut|=oprom[pos++];
|
||||
sprintf(buffer,"%s %s,%.4x", InsNames[entry->ins],RegNames[entry->reg],absolut );
|
||||
sprintf(buffer,"%s %s,%.4x", entry->ins_name(),entry->reg_name(),absolut );
|
||||
break;
|
||||
case Vec:
|
||||
sprintf(buffer,"%s (ff%.2x)", InsNames[entry->ins],oprom[pos++]);break;
|
||||
case Vej:
|
||||
sprintf(buffer,"%s (ff%.2x)", InsNames[entry->ins], oper);break;
|
||||
case Imm:
|
||||
sprintf(buffer,"%s %.2x", InsNames[entry->ins],oprom[pos++]);break;
|
||||
case Imm16:
|
||||
case Entry::Vec:
|
||||
sprintf(buffer,"%s (ff%.2x)", entry->ins_name(),oprom[pos++]);break;
|
||||
case Entry::Vej:
|
||||
sprintf(buffer,"%s (ff%.2x)", entry->ins_name(), oper);break;
|
||||
case Entry::Imm:
|
||||
sprintf(buffer,"%s %.2x", entry->ins_name(),oprom[pos++]);break;
|
||||
case Entry::Imm16:
|
||||
absolut=oprom[pos++]<<8;
|
||||
absolut|=oprom[pos++];
|
||||
sprintf(buffer,"%s %.4x", InsNames[entry->ins],absolut );break;
|
||||
case RelP:
|
||||
sprintf(buffer,"%s %.4x", entry->ins_name(),absolut );break;
|
||||
case Entry::RelP:
|
||||
temp=oprom[pos++];
|
||||
sprintf(buffer,"%s %.4x", InsNames[entry->ins],pc+pos+temp );break;
|
||||
case RelM:
|
||||
sprintf(buffer,"%s %.4x", entry->ins_name(),pc+pos+temp );break;
|
||||
case Entry::RelM:
|
||||
temp=oprom[pos++];
|
||||
sprintf(buffer,"%s %.4x", InsNames[entry->ins],pc+pos-temp );break;
|
||||
case Abs:
|
||||
sprintf(buffer,"%s %.4x", entry->ins_name(),pc+pos-temp );break;
|
||||
case Entry::Abs:
|
||||
absolut=oprom[pos++]<<8;
|
||||
absolut|=oprom[pos++];
|
||||
sprintf(buffer,"%s (%.4x)", InsNames[entry->ins],absolut );break;
|
||||
case ME1Abs:
|
||||
sprintf(buffer,"%s (%.4x)", entry->ins_name(),absolut );break;
|
||||
case Entry::ME1Abs:
|
||||
absolut=oprom[pos++]<<8;
|
||||
absolut|=oprom[pos++];
|
||||
sprintf(buffer,"%s #(%.4x)", InsNames[entry->ins],absolut );break;
|
||||
case AbsImm:
|
||||
sprintf(buffer,"%s #(%.4x)", entry->ins_name(),absolut );break;
|
||||
case Entry::AbsImm:
|
||||
absolut=oprom[pos++]<<8;
|
||||
absolut|=oprom[pos++];
|
||||
sprintf(buffer,"%s (%.4x),%.2x", InsNames[entry->ins],absolut,
|
||||
sprintf(buffer,"%s (%.4x),%.2x", entry->ins_name(),absolut,
|
||||
oprom[pos++]);break;
|
||||
case ME1AbsImm:
|
||||
case Entry::ME1AbsImm:
|
||||
absolut=oprom[pos++]<<8;
|
||||
absolut|=oprom[pos++];
|
||||
sprintf(buffer,"%s #(%.4x),%.2x", InsNames[entry->ins],absolut,
|
||||
sprintf(buffer,"%s #(%.4x),%.2x", entry->ins_name(),absolut,
|
||||
oprom[pos++]);break;
|
||||
case ME0:
|
||||
sprintf(buffer,"%s (%s)", InsNames[entry->ins],RegNames[entry->reg] );break;
|
||||
case ME0Imm:
|
||||
sprintf(buffer,"%s (%s),%.2x", InsNames[entry->ins],RegNames[entry->reg],oprom[pos++] );
|
||||
case Entry::ME0:
|
||||
sprintf(buffer,"%s (%s)", entry->ins_name(),entry->reg_name() );break;
|
||||
case Entry::ME0Imm:
|
||||
sprintf(buffer,"%s (%s),%.2x", entry->ins_name(),entry->reg_name(),oprom[pos++] );
|
||||
break;
|
||||
case ME1:
|
||||
sprintf(buffer,"%s #(%s)", InsNames[entry->ins],RegNames[entry->reg] );break;
|
||||
case ME1Imm:
|
||||
sprintf(buffer,"%s #(%s),%.2x", InsNames[entry->ins],RegNames[entry->reg],oprom[pos++] );
|
||||
case Entry::ME1:
|
||||
sprintf(buffer,"%s #(%s)", entry->ins_name(),entry->reg_name() );break;
|
||||
case Entry::ME1Imm:
|
||||
sprintf(buffer,"%s #(%s),%.2x", entry->ins_name(),entry->reg_name(),oprom[pos++] );
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -18,18 +18,59 @@ Based on G65C816 CPU Emulator by Karl Stenerud
|
||||
|
||||
#define ADDRESS_24BIT(A) ((A)&0xffffff)
|
||||
|
||||
struct m7700_opcode_struct
|
||||
namespace {
|
||||
|
||||
class m7700_opcode_struct
|
||||
{
|
||||
unsigned char name;
|
||||
public:
|
||||
bool is_call() const { return m_name == op::JSR; }
|
||||
bool is_return() const { return (m_name == op::RTS) || (m_name == op::RTI); }
|
||||
const char *name() const { return s_opnames[unsigned(m_name)]; }
|
||||
|
||||
static const m7700_opcode_struct &get(unsigned char ins) { return s_opcodes[ins]; }
|
||||
static const m7700_opcode_struct &get_prefix42(unsigned char ins) { return s_opcodes_prefix42[ins]; }
|
||||
static const m7700_opcode_struct &get_prefix89(unsigned char ins) { return s_opcodes_prefix89[ins]; }
|
||||
|
||||
unsigned char flag;
|
||||
unsigned char ea;
|
||||
|
||||
protected:
|
||||
enum class op : unsigned
|
||||
{
|
||||
ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA ,
|
||||
BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX ,
|
||||
CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML ,
|
||||
JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA ,
|
||||
PEA , PEI , PER , PHA , PHT , PHD , PHK , PHP , PHX , PHY , PLA ,
|
||||
PLB , PLD , PLP , PLX , PLY , CLP , ROL , ROR , RTI , RTL , RTS ,
|
||||
SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX ,
|
||||
TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY ,
|
||||
TYA , TYX , WAI , WDM , XBA , XCE , MPY , DIV , MPYS, DIVS, RLA ,
|
||||
EXTS, EXTZ , LDT , LDM , UNK , SEB , SEM , CLM , STB , LDB , ADCB ,
|
||||
SBCB, EORB , TBX , CMPB, INB , DEB , TXB , TYB , LSRB, ORB , CLB ,
|
||||
BBC, BBS, TBY, ANDB, PUL , PSH , PLAB, XAB , PHB
|
||||
};
|
||||
|
||||
m7700_opcode_struct(op n, unsigned char f, unsigned char e)
|
||||
: flag(f)
|
||||
, ea(e)
|
||||
, m_name(n)
|
||||
{
|
||||
}
|
||||
|
||||
op m_name;
|
||||
|
||||
static const char *const s_opnames[];
|
||||
static const m7700_opcode_struct s_opcodes[256];
|
||||
static const m7700_opcode_struct s_opcodes_prefix42[256];
|
||||
static const m7700_opcode_struct s_opcodes_prefix89[256];
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
IMP , ACC , RELB, RELW, IMM , A , AI , AL , ALX , AX , AXI ,
|
||||
AY , D , DI , DIY , DLI , DLIY, DX , DXI , DY , S , SIY ,
|
||||
SIG /*, MVN , MVP , PEA , PEI , PER */, LDM4, LDM5, LDM4X, LDM5X,
|
||||
SIG , MVN , MVP , PEA , PEI , PER , LDM4, LDM5, LDM4X, LDM5X,
|
||||
BBCD, BBCA, ACCB
|
||||
};
|
||||
|
||||
@ -40,23 +81,7 @@ enum
|
||||
X /* check x bit */
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
ADC , AND , ASL , BCC , BCS , BEQ , BIT , BMI , BNE , BPL , BRA ,
|
||||
BRK , BRL , BVC , BVS , CLC , CLD , CLI , CLV , CMP , COP , CPX ,
|
||||
CPY , DEA , DEC , DEX , DEY , EOR , INA , INC , INX , INY , JML ,
|
||||
JMP , JSL , JSR , LDA , LDX , LDY , LSR , MVN , MVP , NOP , ORA ,
|
||||
PEA , PEI , PER , PHA , PHT , PHD , PHK , PHP , PHX , PHY , PLA ,
|
||||
PLB , PLD , PLP , PLX , PLY , CLP , ROL , ROR , RTI , RTL , RTS ,
|
||||
SBC , SEC , SED , SEI , SEP , STA , STP , STX , STY , STZ , TAX ,
|
||||
TAY , TCS , TCD , TDC , TRB , TSB , TSC , TSX , TXA , TXS , TXY ,
|
||||
TYA , TYX , WAI , WDM , XBA , XCE , MPY , DIV , MPYS, DIVS, RLA ,
|
||||
EXTS, EXTZ , LDT , LDM , UNK , SEB , SEM , CLM , STB , LDB , ADCB ,
|
||||
SBCB, EORB , TBX , CMPB, INB , DEB , TXB , TYB , LSRB, ORB , CLB ,
|
||||
BBC, BBS, TBY, ANDB, PUL , PSH , PLAB, XAB , PHB
|
||||
};
|
||||
|
||||
static const char *const g_opnames[] =
|
||||
const char *const m7700_opcode_struct::s_opnames[] =
|
||||
{
|
||||
"ADC", "AND", "ASL", "BCC", "BCS", "BEQ", "BIT", "BMI", "BNE", "BPL", "BRA",
|
||||
"BRK", "BRL", "BVC", "BVS", "CLC", "CLD", "CLI", "CLV", "CMP", "COP", "CPX",
|
||||
@ -66,261 +91,263 @@ static const char *const g_opnames[] =
|
||||
"PLT", "PLD", "PLP", "PLX", "PLY", "CLP", "ROL", "ROR", "RTI", "RTL", "RTS",
|
||||
"SBC", "SEC", "SED", "SEI", "SEP", "STA", "STP", "STX", "STY", "STZ", "TAX",
|
||||
"TAY", "TCS", "TCD", "TDC", "TRB", "TSB", "TSC", "TSX", "TXA", "TXS", "TXY",
|
||||
"TYA", "TYX", "WAI", "WDM", "XBA", "XCE", "MPY", "DIV", "MPYS", "DIVS", "RLA",
|
||||
"TYA", "TYX", "WAI", "WDM", "XBA", "XCE", "MPY", "DIV", "MPYS","DIVS","RLA",
|
||||
"EXTS","EXTZ","LDT", "LDM", "UNK", "SEB", "SEM", "CLM", "STB", "LDB", "ADCB",
|
||||
"SBCB","EORB","TBX", "CMPB","INB", "DEB", "TXB", "TYB", "LSRB", "ORB", "CLB",
|
||||
"SBCB","EORB","TBX", "CMPB","INB", "DEB", "TXB", "TYB", "LSRB","ORB", "CLB",
|
||||
"BBC", "BBS", "TBY", "ANDB","PUL", "PSH", "PLB", "XAB", "PHB",
|
||||
};
|
||||
|
||||
static const m7700_opcode_struct g_opcodes[256] =
|
||||
const m7700_opcode_struct m7700_opcode_struct::s_opcodes[256] =
|
||||
{
|
||||
{BRK, I, SIG }, {ORA, M, DXI }, {UNK, I, SIG }, {ORA, M, S },
|
||||
{SEB, M, LDM4 }, {ORA, M, D }, {ASL, M, D }, {ORA, M, DLI },
|
||||
{PHP, I, IMP }, {ORA, M, IMM }, {ASL, M, ACC }, {PHD, I, IMP },
|
||||
{SEB, M, LDM5 }, {ORA, M, A }, {ASL, M, A }, {ORA, M, AL },
|
||||
{op::BRK, I, SIG }, {op::ORA, M, DXI }, {op::UNK, I, SIG }, {op::ORA, M, S },
|
||||
{op::SEB, M, LDM4 }, {op::ORA, M, D }, {op::ASL, M, D }, {op::ORA, M, DLI },
|
||||
{op::PHP, I, IMP }, {op::ORA, M, IMM }, {op::ASL, M, ACC }, {op::PHD, I, IMP },
|
||||
{op::SEB, M, LDM5 }, {op::ORA, M, A }, {op::ASL, M, A }, {op::ORA, M, AL },
|
||||
// 0x10
|
||||
{BPL, I, RELB}, {ORA, M, DIY }, {ORA, M, DI }, {ORA, M, SIY },
|
||||
{CLB, M, LDM4}, {ORA, M, DX }, {ASL, M, DX }, {ORA, M, DLIY},
|
||||
{CLC, I, IMP }, {ORA, M, AY }, {DEA, I, IMP }, {TCS, I, IMP },
|
||||
{CLB, M, LDM5}, {ORA, M, AX }, {ASL, M, AX }, {ORA, M, ALX },
|
||||
{op::BPL, I, RELB }, {op::ORA, M, DIY }, {op::ORA, M, DI }, {op::ORA, M, SIY },
|
||||
{op::CLB, M, LDM4 }, {op::ORA, M, DX }, {op::ASL, M, DX }, {op::ORA, M, DLIY },
|
||||
{op::CLC, I, IMP }, {op::ORA, M, AY }, {op::DEA, I, IMP }, {op::TCS, I, IMP },
|
||||
{op::CLB, M, LDM5 }, {op::ORA, M, AX }, {op::ASL, M, AX }, {op::ORA, M, ALX },
|
||||
// 0x20
|
||||
{JSR, I, A }, {AND, M, DXI }, {JSL, I, AL }, {AND, M, S },
|
||||
{BBS, M, BBCD}, {AND, M, D }, {ROL, M, D }, {AND, M, DLI },
|
||||
{PLP, I, IMP }, {AND, M, IMM }, {ROL, M, ACC }, {PLD, I, IMP },
|
||||
{BBS, M, BBCA}, {AND, M, A }, {ROL, M, A }, {AND, M, AL },
|
||||
{op::JSR, I, A }, {op::AND, M, DXI }, {op::JSL, I, AL }, {op::AND, M, S },
|
||||
{op::BBS, M, BBCD }, {op::AND, M, D }, {op::ROL, M, D }, {op::AND, M, DLI },
|
||||
{op::PLP, I, IMP }, {op::AND, M, IMM }, {op::ROL, M, ACC }, {op::PLD, I, IMP },
|
||||
{op::BBS, M, BBCA }, {op::AND, M, A }, {op::ROL, M, A }, {op::AND, M, AL },
|
||||
// 0x30
|
||||
{BMI, I, RELB}, {AND, M, DIY }, {AND, M, DI }, {AND, M, SIY },
|
||||
{BBC, M, BBCD}, {AND, M, DX }, {ROL, M, DX }, {AND, M, DLIY},
|
||||
{SEC, I, IMP }, {AND, M, AY }, {INA, I, IMP }, {TSC, I, IMP },
|
||||
{BBC, M, BBCA}, {AND, M, AX }, {ROL, M, AX }, {AND, M, ALX },
|
||||
{op::BMI, I, RELB }, {op::AND, M, DIY }, {op::AND, M, DI }, {op::AND, M, SIY },
|
||||
{op::BBC, M, BBCD }, {op::AND, M, DX }, {op::ROL, M, DX }, {op::AND, M, DLIY },
|
||||
{op::SEC, I, IMP }, {op::AND, M, AY }, {op::INA, I, IMP }, {op::TSC, I, IMP },
|
||||
{op::BBC, M, BBCA }, {op::AND, M, AX }, {op::ROL, M, AX }, {op::AND, M, ALX },
|
||||
// 0x40
|
||||
{RTI, I, IMP }, {EOR, M, DXI }, {WDM, I, IMP }, {EOR, M, S },
|
||||
{MVP, I, MVP }, {EOR, M, D }, {LSR, M, D }, {EOR, M, DLI },
|
||||
{PHA, I, IMP }, {EOR, M, IMM }, {LSR, M, ACC }, {PHK, I, IMP },
|
||||
{JMP, I, A }, {EOR, M, A }, {LSR, M, A }, {EOR, M, AL },
|
||||
{op::RTI, I, IMP }, {op::EOR, M, DXI }, {op::WDM, I, IMP }, {op::EOR, M, S },
|
||||
{op::MVP, I, MVP }, {op::EOR, M, D }, {op::LSR, M, D }, {op::EOR, M, DLI },
|
||||
{op::PHA, I, IMP }, {op::EOR, M, IMM }, {op::LSR, M, ACC }, {op::PHK, I, IMP },
|
||||
{op::JMP, I, A }, {op::EOR, M, A }, {op::LSR, M, A }, {op::EOR, M, AL },
|
||||
// 0x50
|
||||
{BVC, I, RELB}, {EOR, M, DIY }, {EOR, M, DI }, {EOR, M, SIY },
|
||||
{MVN, I, MVN }, {EOR, M, DX }, {LSR, M, DX }, {EOR, M, DLIY},
|
||||
{CLI, I, IMP }, {EOR, M, AY }, {PHY, I, IMP }, {TCD, I, IMP },
|
||||
{JMP, I, AL }, {EOR, M, AX }, {LSR, M, AX }, {EOR, M, ALX },
|
||||
{op::BVC, I, RELB }, {op::EOR, M, DIY }, {op::EOR, M, DI }, {op::EOR, M, SIY },
|
||||
{op::MVN, I, MVN }, {op::EOR, M, DX }, {op::LSR, M, DX }, {op::EOR, M, DLIY },
|
||||
{op::CLI, I, IMP }, {op::EOR, M, AY }, {op::PHY, I, IMP }, {op::TCD, I, IMP },
|
||||
{op::JMP, I, AL }, {op::EOR, M, AX }, {op::LSR, M, AX }, {op::EOR, M, ALX },
|
||||
// 0x60
|
||||
{RTS, I, IMP }, {ADC, M, DXI }, {PER, I, PER }, {ADC, M, S },
|
||||
{LDM, M, LDM4 }, {ADC, M, D }, {ROR, M, D }, {ADC, M, DLI },
|
||||
{PLA, I, IMP }, {ADC, M, IMM }, {ROR, M, ACC }, {RTL, I, IMP },
|
||||
{JMP, I, AI }, {ADC, M, A }, {ROR, M, A }, {ADC, M, AL },
|
||||
{op::RTS, I, IMP }, {op::ADC, M, DXI }, {op::PER, I, PER }, {op::ADC, M, S },
|
||||
{op::LDM, M, LDM4 }, {op::ADC, M, D }, {op::ROR, M, D }, {op::ADC, M, DLI },
|
||||
{op::PLA, I, IMP }, {op::ADC, M, IMM }, {op::ROR, M, ACC }, {op::RTL, I, IMP },
|
||||
{op::JMP, I, AI }, {op::ADC, M, A }, {op::ROR, M, A }, {op::ADC, M, AL },
|
||||
// 0x70
|
||||
{BVS, I, RELB}, {ADC, M, DIY }, {ADC, M, DI }, {ADC, M, SIY },
|
||||
{LDM, M, LDM4X }, {ADC, M, DX }, {ROR, M, DX }, {ADC, M, DLIY},
|
||||
{SEI, I, IMP }, {ADC, M, AY }, {PLY, I, IMP }, {TDC, I, IMP },
|
||||
{JMP, I, AXI }, {ADC, M, AX }, {ROR, M, AX }, {ADC, M, ALX },
|
||||
{op::BVS, I, RELB }, {op::ADC, M, DIY }, {op::ADC, M, DI }, {op::ADC, M, SIY },
|
||||
{op::LDM, M, LDM4X}, {op::ADC, M, DX }, {op::ROR, M, DX }, {op::ADC, M, DLIY },
|
||||
{op::SEI, I, IMP }, {op::ADC, M, AY }, {op::PLY, I, IMP }, {op::TDC, I, IMP },
|
||||
{op::JMP, I, AXI }, {op::ADC, M, AX }, {op::ROR, M, AX }, {op::ADC, M, ALX },
|
||||
// 0x80
|
||||
{BRA, I, RELB}, {STA, M, DXI }, {BRL, I, RELW}, {STA, M, S },
|
||||
{STY, X, D }, {STA, M, D }, {STX, X, D }, {STA, M, DLI },
|
||||
{DEY, I, IMP }, {BIT, M, IMM }, {TXA, I, IMP }, {PHT, I, IMP },
|
||||
{STY, X, A }, {STA, M, A }, {STX, X, A }, {STA, M, AL },
|
||||
{op::BRA, I, RELB }, {op::STA, M, DXI }, {op::BRL, I, RELW}, {op::STA, M, S },
|
||||
{op::STY, X, D }, {op::STA, M, D }, {op::STX, X, D }, {op::STA, M, DLI },
|
||||
{op::DEY, I, IMP }, {op::BIT, M, IMM }, {op::TXA, I, IMP }, {op::PHT, I, IMP },
|
||||
{op::STY, X, A }, {op::STA, M, A }, {op::STX, X, A }, {op::STA, M, AL },
|
||||
// 0x90
|
||||
{BCC, I, RELB}, {STA, M, DIY }, {STA, M, DI }, {STA, M, SIY },
|
||||
{STY, X, DX }, {STA, M, DX }, {STX, X, DY }, {STA, M, DLIY},
|
||||
{TYA, I, IMP }, {STA, M, AY }, {TXS, I, IMP }, {TXY, I, IMP },
|
||||
{LDM, M, LDM5 }, {STA, M, AX }, {LDM, M, LDM5X }, {STA, M, ALX },
|
||||
{op::BCC, I, RELB }, {op::STA, M, DIY }, {op::STA, M, DI }, {op::STA, M, SIY },
|
||||
{op::STY, X, DX }, {op::STA, M, DX }, {op::STX, X, DY }, {op::STA, M, DLIY },
|
||||
{op::TYA, I, IMP }, {op::STA, M, AY }, {op::TXS, I, IMP }, {op::TXY, I, IMP },
|
||||
{op::LDM, M, LDM5 }, {op::STA, M, AX }, {op::LDM, M, LDM5X},{op::STA, M, ALX },
|
||||
// 0xA0
|
||||
{LDY, X, IMM }, {LDA, M, DXI }, {LDX, X, IMM }, {LDA, M, S },
|
||||
{LDY, X, D }, {LDA, M, D }, {LDX, X, D }, {LDA, M, DLI },
|
||||
{TAY, I, IMP }, {LDA, M, IMM }, {TAX, I, IMP }, {PLB, I, IMP },
|
||||
{LDY, X, A }, {LDA, M, A }, {LDX, X, A }, {LDA, M, AL },
|
||||
{op::LDY, X, IMM }, {op::LDA, M, DXI }, {op::LDX, X, IMM }, {op::LDA, M, S },
|
||||
{op::LDY, X, D }, {op::LDA, M, D }, {op::LDX, X, D }, {op::LDA, M, DLI },
|
||||
{op::TAY, I, IMP }, {op::LDA, M, IMM }, {op::TAX, I, IMP }, {op::PLB, I, IMP },
|
||||
{op::LDY, X, A }, {op::LDA, M, A }, {op::LDX, X, A }, {op::LDA, M, AL },
|
||||
// 0xB0
|
||||
{BCS, I, RELB}, {LDA, M, DIY }, {LDA, M, DI }, {LDA, M, SIY },
|
||||
{LDY, X, DX }, {LDA, M, DX }, {LDX, X, DY }, {LDA, M, DLIY},
|
||||
{CLV, I, IMP }, {LDA, M, AY }, {TSX, I, IMP }, {TYX, I, IMP },
|
||||
{LDY, X, AX }, {LDA, M, AX }, {LDX, X, AY }, {LDA, M, ALX },
|
||||
{op::BCS, I, RELB }, {op::LDA, M, DIY }, {op::LDA, M, DI }, {op::LDA, M, SIY },
|
||||
{op::LDY, X, DX }, {op::LDA, M, DX }, {op::LDX, X, DY }, {op::LDA, M, DLIY },
|
||||
{op::CLV, I, IMP }, {op::LDA, M, AY }, {op::TSX, I, IMP }, {op::TYX, I, IMP },
|
||||
{op::LDY, X, AX }, {op::LDA, M, AX }, {op::LDX, X, AY }, {op::LDA, M, ALX },
|
||||
// 0xC0
|
||||
{CPY, X, IMM }, {CMP, M, DXI }, {CLP, I, IMM }, {CMP, M, S },
|
||||
{CPY, X, D }, {CMP, M, D }, {DEC, M, D }, {CMP, M, DLI },
|
||||
{INY, I, IMP }, {CMP, M, IMM }, {DEX, I, IMP }, {WAI, I, IMP },
|
||||
{CPY, X, A }, {CMP, M, A }, {DEC, M, A }, {CMP, M, AL },
|
||||
{op::CPY, X, IMM }, {op::CMP, M, DXI }, {op::CLP, I, IMM }, {op::CMP, M, S },
|
||||
{op::CPY, X, D }, {op::CMP, M, D }, {op::DEC, M, D }, {op::CMP, M, DLI },
|
||||
{op::INY, I, IMP }, {op::CMP, M, IMM }, {op::DEX, I, IMP }, {op::WAI, I, IMP },
|
||||
{op::CPY, X, A }, {op::CMP, M, A }, {op::DEC, M, A }, {op::CMP, M, AL },
|
||||
// 0xD0
|
||||
{BNE, I, RELB}, {CMP, M, DIY }, {CMP, M, DI }, {CMP, M, SIY },
|
||||
{PEI, I, PEI }, {CMP, M, DX }, {DEC, M, DX }, {CMP, M, DLIY},
|
||||
{CLM, I, IMP }, {CMP, M, AY }, {PHX, I, IMP }, {STP, I, IMP },
|
||||
{JML, I, AI }, {CMP, M, AX }, {DEC, M, AX }, {CMP, M, ALX },
|
||||
{op::BNE, I, RELB }, {op::CMP, M, DIY }, {op::CMP, M, DI }, {op::CMP, M, SIY },
|
||||
{op::PEI, I, PEI }, {op::CMP, M, DX }, {op::DEC, M, DX }, {op::CMP, M, DLIY },
|
||||
{op::CLM, I, IMP }, {op::CMP, M, AY }, {op::PHX, I, IMP }, {op::STP, I, IMP },
|
||||
{op::JML, I, AI }, {op::CMP, M, AX }, {op::DEC, M, AX }, {op::CMP, M, ALX },
|
||||
// 0xE0
|
||||
{CPX, X, IMM }, {SBC, M, DXI }, {SEP, I, IMM }, {SBC, M, S },
|
||||
{CPX, X, D }, {SBC, M, D }, {INC, M, D }, {SBC, M, DLI },
|
||||
{INX, M, IMP }, {SBC, M, IMM }, {NOP, I, IMP }, {PSH, I, IMM },
|
||||
{CPX, X, A }, {SBC, M, A }, {INC, M, A }, {SBC, M, AL },
|
||||
{op::CPX, X, IMM }, {op::SBC, M, DXI }, {op::SEP, I, IMM }, {op::SBC, M, S },
|
||||
{op::CPX, X, D }, {op::SBC, M, D }, {op::INC, M, D }, {op::SBC, M, DLI },
|
||||
{op::INX, M, IMP }, {op::SBC, M, IMM }, {op::NOP, I, IMP }, {op::PSH, I, IMM },
|
||||
{op::CPX, X, A }, {op::SBC, M, A }, {op::INC, M, A }, {op::SBC, M, AL },
|
||||
// 0xF0
|
||||
{BEQ, I, RELB}, {SBC, M, DIY }, {SBC, M, DI }, {SBC, M, SIY },
|
||||
{PEA, I, PEA }, {SBC, M, DX }, {INC, M, DX }, {SBC, M, DLIY},
|
||||
{SEM, I, IMP }, {SBC, M, AY }, {PLX, I, IMP }, {PUL, I, IMM },
|
||||
{JSR, I, AXI }, {SBC, M, AX }, {INC, M, AX }, {SBC, M, ALX }
|
||||
{op::BEQ, I, RELB }, {op::SBC, M, DIY }, {op::SBC, M, DI }, {op::SBC, M, SIY },
|
||||
{op::PEA, I, PEA }, {op::SBC, M, DX }, {op::INC, M, DX }, {op::SBC, M, DLIY },
|
||||
{op::SEM, I, IMP }, {op::SBC, M, AY }, {op::PLX, I, IMP }, {op::PUL, I, IMM },
|
||||
{op::JSR, I, AXI }, {op::SBC, M, AX }, {op::INC, M, AX }, {op::SBC, M, ALX }
|
||||
};
|
||||
|
||||
static const m7700_opcode_struct g_opcodes_prefix42[256] =
|
||||
const m7700_opcode_struct m7700_opcode_struct::s_opcodes_prefix42[256] =
|
||||
{
|
||||
{BRK, I, SIG }, {ORB, M, DXI }, {COP, I, SIG }, {ORB, M, S },
|
||||
{TSB, M, D }, {ORB, M, D }, {ASL, M, D }, {ORB, M, DLI },
|
||||
{PHP, I, IMP }, {ORB, M, IMM }, {ASL, M, ACCB }, {PHD, I, IMP },
|
||||
{TSB, M, A }, {ORB, M, A }, {ASL, M, A }, {ORB, M, AL },
|
||||
{op::BRK, I, SIG }, {op::ORB, M, DXI }, {op::COP, I, SIG }, {op::ORB, M, S },
|
||||
{op::TSB, M, D }, {op::ORB, M, D }, {op::ASL, M, D }, {op::ORB, M, DLI },
|
||||
{op::PHP, I, IMP }, {op::ORB, M, IMM }, {op::ASL, M, ACCB}, {op::PHD, I, IMP },
|
||||
{op::TSB, M, A }, {op::ORB, M, A }, {op::ASL, M, A }, {op::ORB, M, AL },
|
||||
// 0x10
|
||||
{BPL, I, RELB}, {ORB, M, DIY }, {ORB, M, DI }, {ORB, M, SIY },
|
||||
{TRB, M, D }, {ORB, M, DX }, {ASL, M, DX }, {ORB, M, DLIY},
|
||||
{CLC, I, IMP }, {ORB, M, AY }, {DEB, I, IMP }, {TCS, I, IMP },
|
||||
{TRB, M, A }, {ORB, M, AX }, {ASL, M, AX }, {ORB, M, ALX },
|
||||
{op::BPL, I, RELB }, {op::ORB, M, DIY }, {op::ORB, M, DI }, {op::ORB, M, SIY },
|
||||
{op::TRB, M, D }, {op::ORB, M, DX }, {op::ASL, M, DX }, {op::ORB, M, DLIY},
|
||||
{op::CLC, I, IMP }, {op::ORB, M, AY }, {op::DEB, I, IMP }, {op::TCS, I, IMP },
|
||||
{op::TRB, M, A }, {op::ORB, M, AX }, {op::ASL, M, AX }, {op::ORB, M, ALX },
|
||||
// 0x20
|
||||
{JSR, I, A }, {ANDB, M, DXI }, {JSL, I, AL }, {ANDB, M, S },
|
||||
{BIT, M, D }, {ANDB, M, D }, {ROL, M, D }, {ANDB, M, DLI },
|
||||
{PLP, I, IMP }, {ANDB, M, IMM }, {ROL, M, ACCB }, {PLD, I, IMP },
|
||||
{BIT, M, A }, {ANDB, M, A }, {ROL, M, A }, {ANDB, M, AL },
|
||||
{op::JSR, I, A }, {op::ANDB,M, DXI }, {op::JSL, I, AL }, {op::ANDB, M, S },
|
||||
{op::BIT, M, D }, {op::ANDB,M, D }, {op::ROL, M, D }, {op::ANDB, M, DLI },
|
||||
{op::PLP, I, IMP }, {op::ANDB,M, IMM }, {op::ROL, M, ACCB}, {op::PLD, I, IMP },
|
||||
{op::BIT, M, A }, {op::ANDB,M, A }, {op::ROL, M, A }, {op::ANDB, M, AL },
|
||||
// 0x30
|
||||
{BMI, I, RELB}, {AND, M, DIY }, {AND, M, DI }, {AND, M, SIY },
|
||||
{BIT, M, DX }, {AND, M, DX }, {ROL, M, DX }, {AND, M, DLIY},
|
||||
{SEC, I, IMP }, {AND, M, AY }, {INB, I, IMP }, {TSC, I, IMP },
|
||||
{BIT, M, AX }, {AND, M, AX }, {ROL, M, AX }, {AND, M, ALX },
|
||||
{op::BMI, I, RELB }, {op::AND, M, DIY }, {op::AND, M, DI }, {op::AND, M, SIY },
|
||||
{op::BIT, M, DX }, {op::AND, M, DX }, {op::ROL, M, DX }, {op::AND, M, DLIY},
|
||||
{op::SEC, I, IMP }, {op::AND, M, AY }, {op::INB, I, IMP }, {op::TSC, I, IMP },
|
||||
{op::BIT, M, AX }, {op::AND, M, AX }, {op::ROL, M, AX }, {op::AND, M, ALX },
|
||||
// 0x40
|
||||
{RTI, I, IMP }, {EORB, M, DXI }, {WDM, I, IMP }, {EORB, M, S },
|
||||
{MVP, I, MVP }, {EORB, M, D }, {LSRB, M, D }, {EORB, M, DLI },
|
||||
{PHB, I, IMP }, {EORB, M, IMM }, {LSRB, M, ACC }, {PHK, I, IMP },
|
||||
{JMP, I, A }, {EORB, M, A }, {LSRB, M, A }, {EORB, M, AL },
|
||||
{op::RTI, I, IMP }, {op::EORB,M, DXI }, {op::WDM, I, IMP }, {op::EORB, M, S },
|
||||
{op::MVP, I, MVP }, {op::EORB,M, D }, {op::LSRB,M, D }, {op::EORB, M, DLI },
|
||||
{op::PHB, I, IMP }, {op::EORB,M, IMM }, {op::LSRB,M, ACC }, {op::PHK, I, IMP },
|
||||
{op::JMP, I, A }, {op::EORB,M, A }, {op::LSRB,M, A }, {op::EORB, M, AL },
|
||||
// 0x50
|
||||
{BVC, I, RELB}, {EORB, M, DIY }, {EORB, M, DI }, {EORB, M, SIY },
|
||||
{MVN, I, MVN }, {EORB, M, DX }, {LSRB, M, DX }, {EORB, M, DLIY},
|
||||
{CLI, I, IMP }, {EORB, M, AY }, {PHY, I, IMP }, {TCD, I, IMP },
|
||||
{JMP, I, AL }, {EORB, M, AX }, {LSRB, M, AX }, {EORB, M, ALX },
|
||||
{op::BVC, I, RELB }, {op::EORB,M, DIY }, {op::EORB,M, DI }, {op::EORB, M, SIY },
|
||||
{op::MVN, I, MVN }, {op::EORB,M, DX }, {op::LSRB,M, DX }, {op::EORB, M, DLIY},
|
||||
{op::CLI, I, IMP }, {op::EORB,M, AY }, {op::PHY, I, IMP }, {op::TCD, I, IMP },
|
||||
{op::JMP, I, AL }, {op::EORB,M, AX }, {op::LSRB,M, AX }, {op::EORB, M, ALX },
|
||||
// 0x60
|
||||
{RTS, I, IMP }, {ADCB, M, DXI }, {PER, I, PER }, {ADCB, M, S },
|
||||
{STZ, M, D }, {ADCB, M, D }, {ROR, M, D }, {ADCB, M, DLI },
|
||||
{PLAB,I, IMP }, {ADCB, M, IMM }, {ROR, M, ACC }, {RTL, I, IMP },
|
||||
{JMP, I, AI }, {ADCB, M, A }, {ROR, M, A }, {ADCB, M, AL },
|
||||
{op::RTS, I, IMP }, {op::ADCB,M, DXI }, {op::PER, I, PER }, {op::ADCB, M, S },
|
||||
{op::STZ, M, D }, {op::ADCB,M, D }, {op::ROR, M, D }, {op::ADCB, M, DLI },
|
||||
{op::PLAB,I, IMP }, {op::ADCB,M, IMM }, {op::ROR, M, ACC }, {op::RTL, I, IMP },
|
||||
{op::JMP, I, AI }, {op::ADCB,M, A }, {op::ROR, M, A }, {op::ADCB, M, AL },
|
||||
// 0x70
|
||||
{BVS, I, RELB}, {ADCB, M, DIY }, {ADCB, M, DI }, {ADCB, M, SIY },
|
||||
{STZ, M, DX }, {ADCB, M, DX }, {ROR, M, DX }, {ADCB, M, DLIY},
|
||||
{SEI, I, IMP }, {ADCB, M, AY }, {PLY, I, IMP }, {TDC, I, IMP },
|
||||
{JMP, I, AXI }, {ADCB, M, AX }, {ROR, M, AX }, {ADCB, M, ALX },
|
||||
{op::BVS, I, RELB }, {op::ADCB,M, DIY }, {op::ADCB,M, DI }, {op::ADCB, M, SIY },
|
||||
{op::STZ, M, DX }, {op::ADCB,M, DX }, {op::ROR, M, DX }, {op::ADCB, M, DLIY},
|
||||
{op::SEI, I, IMP }, {op::ADCB,M, AY }, {op::PLY, I, IMP }, {op::TDC, I, IMP },
|
||||
{op::JMP, I, AXI }, {op::ADCB,M, AX }, {op::ROR, M, AX }, {op::ADCB, M, ALX },
|
||||
// 0x80
|
||||
{BRA, I, RELB}, {STB, M, DXI }, {BRL, I, RELW}, {STB, M, S },
|
||||
{STY, X, D }, {STB, M, D }, {STX, X, D }, {STB, M, DLI },
|
||||
{DEY, I, IMP }, {BIT, M, IMM }, {TXB, I, IMP }, {PHB, I, IMP },
|
||||
{STY, X, A }, {STB, M, A }, {STX, X, A }, {STB, M, AL },
|
||||
{op::BRA, I, RELB }, {op::STB, M, DXI }, {op::BRL, I, RELW}, {op::STB, M, S },
|
||||
{op::STY, X, D }, {op::STB, M, D }, {op::STX, X, D }, {op::STB, M, DLI },
|
||||
{op::DEY, I, IMP }, {op::BIT, M, IMM }, {op::TXB, I, IMP }, {op::PHB, I, IMP },
|
||||
{op::STY, X, A }, {op::STB, M, A }, {op::STX, X, A }, {op::STB, M, AL },
|
||||
// 0x90
|
||||
{BCC, I, RELB}, {STB, M, DIY }, {STB, M, DI }, {STB, M, SIY },
|
||||
{STY, X, DX }, {STB, M, DX }, {STX, X, DY }, {STB, M, DLIY},
|
||||
{TYB, I, IMP }, {STB, M, AY }, {TXS, I, IMP }, {TXY, I, IMP },
|
||||
{STZ, M, A }, {STB, M, AX }, {STZ, M, AX }, {STB, M, ALX },
|
||||
{op::BCC, I, RELB }, {op::STB, M, DIY }, {op::STB, M, DI }, {op::STB, M, SIY },
|
||||
{op::STY, X, DX }, {op::STB, M, DX }, {op::STX, X, DY }, {op::STB, M, DLIY},
|
||||
{op::TYB, I, IMP }, {op::STB, M, AY }, {op::TXS, I, IMP }, {op::TXY, I, IMP },
|
||||
{op::STZ, M, A }, {op::STB, M, AX }, {op::STZ, M, AX }, {op::STB, M, ALX },
|
||||
// 0xA0
|
||||
{LDY, X, IMM }, {LDB, M, DXI }, {LDX, X, IMM }, {LDB, M, S },
|
||||
{LDY, X, D }, {LDB, M, D }, {LDX, X, D }, {LDB, M, DLI },
|
||||
{TBY, I, IMP }, {LDB, M, IMM }, {TBX, I, IMP }, {PLB, I, IMP },
|
||||
{LDY, X, A }, {LDB, M, A }, {LDX, X, A }, {LDB, M, AL },
|
||||
{op::LDY, X, IMM }, {op::LDB, M, DXI }, {op::LDX, X, IMM }, {op::LDB, M, S },
|
||||
{op::LDY, X, D }, {op::LDB, M, D }, {op::LDX, X, D }, {op::LDB, M, DLI },
|
||||
{op::TBY, I, IMP }, {op::LDB, M, IMM }, {op::TBX, I, IMP }, {op::PLB, I, IMP },
|
||||
{op::LDY, X, A }, {op::LDB, M, A }, {op::LDX, X, A }, {op::LDB, M, AL },
|
||||
// 0xB0
|
||||
{BCS, I, RELB}, {LDB, M, DIY }, {LDB, M, DI }, {LDB, M, SIY },
|
||||
{LDY, X, DX }, {LDB, M, DX }, {LDX, X, DY }, {LDB, M, DLIY},
|
||||
{CLV, I, IMP }, {LDB, M, AY }, {TSX, I, IMP }, {TYX, I, IMP },
|
||||
{LDY, X, AX }, {LDB, M, AX }, {LDX, X, AY }, {LDB, M, ALX },
|
||||
{op::BCS, I, RELB }, {op::LDB, M, DIY }, {op::LDB, M, DI }, {op::LDB, M, SIY },
|
||||
{op::LDY, X, DX }, {op::LDB, M, DX }, {op::LDX, X, DY }, {op::LDB, M, DLIY},
|
||||
{op::CLV, I, IMP }, {op::LDB, M, AY }, {op::TSX, I, IMP }, {op::TYX, I, IMP },
|
||||
{op::LDY, X, AX }, {op::LDB, M, AX }, {op::LDX, X, AY }, {op::LDB, M, ALX },
|
||||
// 0xC0
|
||||
{CPY, X, IMM }, {CMPB, M, DXI }, {CLP, I, IMM }, {CMPB, M, S },
|
||||
{CPY, X, D }, {CMPB, M, D }, {DEC, M, D }, {CMPB, M, DLI },
|
||||
{INY, I, IMP }, {CMPB, M, IMM }, {DEX, I, IMP }, {WAI, I, IMP },
|
||||
{CPY, X, A }, {CMPB, M, A }, {DEC, M, A }, {CMPB, M, AL },
|
||||
{op::CPY, X, IMM }, {op::CMPB,M, DXI }, {op::CLP, I, IMM }, {op::CMPB, M, S },
|
||||
{op::CPY, X, D }, {op::CMPB,M, D }, {op::DEC, M, D }, {op::CMPB, M, DLI },
|
||||
{op::INY, I, IMP }, {op::CMPB,M, IMM }, {op::DEX, I, IMP }, {op::WAI, I, IMP },
|
||||
{op::CPY, X, A }, {op::CMPB,M, A }, {op::DEC, M, A }, {op::CMPB, M, AL },
|
||||
// 0xD0
|
||||
{BNE, I, RELB}, {CMPB, M, DIY }, {CMPB, M, DI }, {CMPB, M, SIY },
|
||||
{PEI, I, PEI }, {CMPB, M, DX }, {DEC, M, DX }, {CMPB, M, DLIY},
|
||||
{CLD, I, IMP }, {CMPB, M, AY }, {PHX, I, IMP }, {STP, I, IMP },
|
||||
{JML, I, AI }, {CMPB, M, AX }, {DEC, M, AX }, {CMPB, M, ALX },
|
||||
{op::BNE, I, RELB }, {op::CMPB,M, DIY }, {op::CMPB,M, DI }, {op::CMPB, M, SIY },
|
||||
{op::PEI, I, PEI }, {op::CMPB,M, DX }, {op::DEC, M, DX }, {op::CMPB, M, DLIY},
|
||||
{op::CLD, I, IMP }, {op::CMPB,M, AY }, {op::PHX, I, IMP }, {op::STP, I, IMP },
|
||||
{op::JML, I, AI }, {op::CMPB,M, AX }, {op::DEC, M, AX }, {op::CMPB, M, ALX },
|
||||
// 0xE0
|
||||
{CPX, X, IMM }, {SBCB, M, DXI }, {SEP, I, IMM }, {SBCB, M, S },
|
||||
{CPX, X, D }, {SBCB, M, D }, {INC, M, D }, {SBCB, M, DLI },
|
||||
{INX, M, IMP }, {SBCB, M, IMM }, {NOP, I, IMP }, {XBA, I, IMP },
|
||||
{CPX, X, A }, {SBCB, M, A }, {INC, M, A }, {SBCB, M, AL },
|
||||
{op::CPX, X, IMM }, {op::SBCB,M, DXI }, {op::SEP, I, IMM }, {op::SBCB, M, S },
|
||||
{op::CPX, X, D }, {op::SBCB,M, D }, {op::INC, M, D }, {op::SBCB, M, DLI },
|
||||
{op::INX, M, IMP }, {op::SBCB,M, IMM }, {op::NOP, I, IMP }, {op::XBA, I, IMP },
|
||||
{op::CPX, X, A }, {op::SBCB,M, A }, {op::INC, M, A }, {op::SBCB, M, AL },
|
||||
// 0xF0
|
||||
{BEQ, I, RELB}, {SBCB, M, DIY }, {SBCB, M, DI }, {SBCB, M, SIY },
|
||||
{PEA, I, PEA }, {SBCB, M, DX }, {INC, M, DX }, {SBCB, M, DLIY},
|
||||
{SED, I, IMP }, {SBCB, M, AY }, {PLX, I, IMP }, {XCE, I, IMP },
|
||||
{JSR, I, AXI }, {SBCB, M, AX }, {INC, M, AX }, {SBCB, M, ALX }
|
||||
{op::BEQ, I, RELB }, {op::SBCB,M, DIY }, {op::SBCB,M, DI }, {op::SBCB, M, SIY },
|
||||
{op::PEA, I, PEA }, {op::SBCB,M, DX }, {op::INC, M, DX }, {op::SBCB, M, DLIY},
|
||||
{op::SED, I, IMP }, {op::SBCB,M, AY }, {op::PLX, I, IMP }, {op::XCE, I, IMP },
|
||||
{op::JSR, I, AXI }, {op::SBCB,M, AX }, {op::INC, M, AX }, {op::SBCB, M, ALX }
|
||||
};
|
||||
|
||||
static const m7700_opcode_struct g_opcodes_prefix89[256] =
|
||||
const m7700_opcode_struct m7700_opcode_struct::s_opcodes_prefix89[256] =
|
||||
{
|
||||
{BRK, I, SIG }, {MPY, M, DXI }, {COP, I, SIG }, {MPY, M, S },
|
||||
{TSB, M, D }, {MPY, M, D }, {ASL, M, D }, {MPY, M, DLI },
|
||||
{PHP, I, IMP }, {MPY, M, IMM }, {ASL, M, ACC }, {PHD, I, IMP },
|
||||
{TSB, M, A }, {MPY, M, A }, {ASL, M, A }, {MPY, M, AL },
|
||||
{op::BRK, I, SIG }, {op::MPY, M, DXI }, {op::COP, I, SIG }, {op::MPY, M, S },
|
||||
{op::TSB, M, D }, {op::MPY, M, D }, {op::ASL, M, D }, {op::MPY, M, DLI },
|
||||
{op::PHP, I, IMP }, {op::MPY, M, IMM }, {op::ASL, M, ACC }, {op::PHD, I, IMP },
|
||||
{op::TSB, M, A }, {op::MPY, M, A }, {op::ASL, M, A }, {op::MPY, M, AL },
|
||||
// 0x10
|
||||
{BPL, I, RELB}, {ORA, M, DIY }, {ORA, M, DI }, {ORA, M, SIY },
|
||||
{TRB, M, D }, {MPY, M, DX }, {ASL, M, DX }, {ORA, M, DLIY},
|
||||
{CLC, I, IMP }, {MPY, M, AY }, {INA, I, IMP }, {TCS, I, IMP },
|
||||
{TRB, M, A }, {ORA, M, AX }, {ASL, M, AX }, {ORA, M, ALX },
|
||||
{op::BPL, I, RELB }, {op::ORA, M, DIY }, {op::ORA, M, DI }, {op::ORA, M, SIY },
|
||||
{op::TRB, M, D }, {op::MPY, M, DX }, {op::ASL, M, DX }, {op::ORA, M, DLIY },
|
||||
{op::CLC, I, IMP }, {op::MPY, M, AY }, {op::INA, I, IMP }, {op::TCS, I, IMP },
|
||||
{op::TRB, M, A }, {op::ORA, M, AX }, {op::ASL, M, AX }, {op::ORA, M, ALX },
|
||||
// 0x20
|
||||
{JSR, I, A }, {AND, M, DXI }, {JSL, I, AL }, {AND, M, S },
|
||||
{BIT, M, D }, {AND, M, D }, {ROL, M, D }, {AND, M, DLI },
|
||||
{XAB, I, IMP }, {AND, M, IMM }, {ROL, M, ACC }, {PLD, I, IMP },
|
||||
{BIT, M, A }, {AND, M, A }, {ROL, M, A }, {AND, M, AL },
|
||||
{op::JSR, I, A }, {op::AND, M, DXI }, {op::JSL, I, AL }, {op::AND, M, S },
|
||||
{op::BIT, M, D }, {op::AND, M, D }, {op::ROL, M, D }, {op::AND, M, DLI },
|
||||
{op::XAB, I, IMP }, {op::AND, M, IMM }, {op::ROL, M, ACC }, {op::PLD, I, IMP },
|
||||
{op::BIT, M, A }, {op::AND, M, A }, {op::ROL, M, A }, {op::AND, M, AL },
|
||||
// 0x30
|
||||
{BMI, I, RELB}, {AND, M, DIY }, {AND, M, DI }, {AND, M, SIY },
|
||||
{BIT, M, DX }, {AND, M, DX }, {ROL, M, DX }, {AND, M, DLIY},
|
||||
{SEC, I, IMP }, {AND, M, AY }, {DEA, I, IMP }, {TSC, I, IMP },
|
||||
{BIT, M, AX }, {AND, M, AX }, {ROL, M, AX }, {AND, M, ALX },
|
||||
{op::BMI, I, RELB }, {op::AND, M, DIY }, {op::AND, M, DI }, {op::AND, M, SIY },
|
||||
{op::BIT, M, DX }, {op::AND, M, DX }, {op::ROL, M, DX }, {op::AND, M, DLIY },
|
||||
{op::SEC, I, IMP }, {op::AND, M, AY }, {op::DEA, I, IMP }, {op::TSC, I, IMP },
|
||||
{op::BIT, M, AX }, {op::AND, M, AX }, {op::ROL, M, AX }, {op::AND, M, ALX },
|
||||
// 0x40
|
||||
{RTI, I, IMP }, {EOR, M, DXI }, {WDM, I, IMP }, {EOR, M, S },
|
||||
{MVP, I, MVP }, {EOR, M, D }, {LSR, M, D }, {EOR, M, DLI },
|
||||
{PHA, I, IMP }, {RLA, M, IMM }, {LSR, M, ACC }, {PHK, I, IMP },
|
||||
{JMP, I, A }, {EOR, M, A }, {LSR, M, A }, {EOR, M, AL },
|
||||
{op::RTI, I, IMP }, {op::EOR, M, DXI }, {op::WDM, I, IMP }, {op::EOR, M, S },
|
||||
{op::MVP, I, MVP }, {op::EOR, M, D }, {op::LSR, M, D }, {op::EOR, M, DLI },
|
||||
{op::PHA, I, IMP }, {op::RLA, M, IMM }, {op::LSR, M, ACC }, {op::PHK, I, IMP },
|
||||
{op::JMP, I, A }, {op::EOR, M, A }, {op::LSR, M, A }, {op::EOR, M, AL },
|
||||
// 0x50
|
||||
{BVC, I, RELB}, {EOR, M, DIY }, {EOR, M, DI }, {EOR, M, SIY },
|
||||
{MVN, I, MVN }, {EOR, M, DX }, {LSR, M, DX }, {EOR, M, DLIY},
|
||||
{CLI, I, IMP }, {EOR, M, AY }, {PHY, I, IMP }, {TCD, I, IMP },
|
||||
{JMP, I, AL }, {EOR, M, AX }, {LSR, M, AX }, {EOR, M, ALX },
|
||||
{op::BVC, I, RELB }, {op::EOR, M, DIY }, {op::EOR, M, DI }, {op::EOR, M, SIY },
|
||||
{op::MVN, I, MVN }, {op::EOR, M, DX }, {op::LSR, M, DX }, {op::EOR, M, DLIY },
|
||||
{op::CLI, I, IMP }, {op::EOR, M, AY }, {op::PHY, I, IMP }, {op::TCD, I, IMP },
|
||||
{op::JMP, I, AL }, {op::EOR, M, AX }, {op::LSR, M, AX }, {op::EOR, M, ALX },
|
||||
// 0x60
|
||||
{RTS, I, IMP }, {ADC, M, DXI }, {PER, I, PER }, {ADC, M, S },
|
||||
{STZ, M, D }, {ADC, M, D }, {ROR, M, D }, {ADC, M, DLI },
|
||||
{PLA, I, IMP }, {ADC, M, IMM }, {ROR, M, ACC }, {RTL, I, IMP },
|
||||
{JMP, I, AI }, {ADC, M, A }, {ROR, M, A }, {ADC, M, AL },
|
||||
{op::RTS, I, IMP }, {op::ADC, M, DXI }, {op::PER, I, PER }, {op::ADC, M, S },
|
||||
{op::STZ, M, D }, {op::ADC, M, D }, {op::ROR, M, D }, {op::ADC, M, DLI },
|
||||
{op::PLA, I, IMP }, {op::ADC, M, IMM }, {op::ROR, M, ACC }, {op::RTL, I, IMP },
|
||||
{op::JMP, I, AI }, {op::ADC, M, A }, {op::ROR, M, A }, {op::ADC, M, AL },
|
||||
// 0x70
|
||||
{BVS, I, RELB}, {ADC, M, DIY }, {ADC, M, DI }, {ADC, M, SIY },
|
||||
{STZ, M, DX }, {ADC, M, DX }, {ROR, M, DX }, {ADC, M, DLIY},
|
||||
{SEI, I, IMP }, {ADC, M, AY }, {PLY, I, IMP }, {TDC, I, IMP },
|
||||
{JMP, I, AXI }, {ADC, M, AX }, {ROR, M, AX }, {ADC, M, ALX },
|
||||
{op::BVS, I, RELB }, {op::ADC, M, DIY }, {op::ADC, M, DI }, {op::ADC, M, SIY },
|
||||
{op::STZ, M, DX }, {op::ADC, M, DX }, {op::ROR, M, DX }, {op::ADC, M, DLIY },
|
||||
{op::SEI, I, IMP }, {op::ADC, M, AY }, {op::PLY, I, IMP }, {op::TDC, I, IMP },
|
||||
{op::JMP, I, AXI }, {op::ADC, M, AX }, {op::ROR, M, AX }, {op::ADC, M, ALX },
|
||||
// 0x80
|
||||
{BRA, I, RELB}, {STA, M, DXI }, {BRL, I, RELW}, {STA, M, S },
|
||||
{STY, X, D }, {STA, M, D }, {STX, X, D }, {STA, M, DLI },
|
||||
{DEY, I, IMP }, {BIT, M, IMM }, {TXA, I, IMP }, {PHB, I, IMP },
|
||||
{STY, X, A }, {STA, M, A }, {STX, X, A }, {STA, M, AL },
|
||||
{op::BRA, I, RELB }, {op::STA, M, DXI }, {op::BRL, I, RELW}, {op::STA, M, S },
|
||||
{op::STY, X, D }, {op::STA, M, D }, {op::STX, X, D }, {op::STA, M, DLI },
|
||||
{op::DEY, I, IMP }, {op::BIT, M, IMM }, {op::TXA, I, IMP }, {op::PHB, I, IMP },
|
||||
{op::STY, X, A }, {op::STA, M, A }, {op::STX, X, A }, {op::STA, M, AL },
|
||||
// 0x90
|
||||
{BCC, I, RELB}, {STA, M, DIY }, {STA, M, DI }, {STA, M, SIY },
|
||||
{STY, X, DX }, {STA, M, DX }, {STX, X, DY }, {STA, M, DLIY},
|
||||
{TYA, I, IMP }, {STA, M, AY }, {TXS, I, IMP }, {TXY, I, IMP },
|
||||
{STZ, M, A }, {STA, M, AX }, {STZ, M, AX }, {STA, M, ALX },
|
||||
{op::BCC, I, RELB }, {op::STA, M, DIY }, {op::STA, M, DI }, {op::STA, M, SIY },
|
||||
{op::STY, X, DX }, {op::STA, M, DX }, {op::STX, X, DY }, {op::STA, M, DLIY },
|
||||
{op::TYA, I, IMP }, {op::STA, M, AY }, {op::TXS, I, IMP }, {op::TXY, I, IMP },
|
||||
{op::STZ, M, A }, {op::STA, M, AX }, {op::STZ, M, AX }, {op::STA, M, ALX },
|
||||
// 0xA0
|
||||
{LDY, X, IMM }, {LDA, M, DXI }, {LDX, X, IMM }, {LDA, M, S },
|
||||
{LDY, X, D }, {LDA, M, D }, {LDX, X, D }, {LDA, M, DLI },
|
||||
{TAY, I, IMP }, {LDA, M, IMM }, {TAX, I, IMP }, {PLB, I, IMP },
|
||||
{LDY, X, A }, {LDA, M, A }, {LDX, X, A }, {LDA, M, AL },
|
||||
{op::LDY, X, IMM }, {op::LDA, M, DXI }, {op::LDX, X, IMM }, {op::LDA, M, S },
|
||||
{op::LDY, X, D }, {op::LDA, M, D }, {op::LDX, X, D }, {op::LDA, M, DLI },
|
||||
{op::TAY, I, IMP }, {op::LDA, M, IMM }, {op::TAX, I, IMP }, {op::PLB, I, IMP },
|
||||
{op::LDY, X, A }, {op::LDA, M, A }, {op::LDX, X, A }, {op::LDA, M, AL },
|
||||
// 0xB0
|
||||
{BCS, I, RELB}, {LDA, M, DIY }, {LDA, M, DI }, {LDA, M, SIY },
|
||||
{LDY, X, DX }, {LDA, M, DX }, {LDX, X, DY }, {LDA, M, DLIY},
|
||||
{CLV, I, IMP }, {LDA, M, AY }, {TSX, I, IMP }, {TYX, I, IMP },
|
||||
{LDY, X, AX }, {LDA, M, AX }, {LDX, X, AY }, {LDA, M, ALX },
|
||||
{op::BCS, I, RELB }, {op::LDA, M, DIY }, {op::LDA, M, DI }, {op::LDA, M, SIY },
|
||||
{op::LDY, X, DX }, {op::LDA, M, DX }, {op::LDX, X, DY }, {op::LDA, M, DLIY },
|
||||
{op::CLV, I, IMP }, {op::LDA, M, AY }, {op::TSX, I, IMP }, {op::TYX, I, IMP },
|
||||
{op::LDY, X, AX }, {op::LDA, M, AX }, {op::LDX, X, AY }, {op::LDA, M, ALX },
|
||||
// 0xC0
|
||||
{CPY, X, IMM }, {CMP, M, DXI }, {LDT, I, IMM }, {CMP, M, S },
|
||||
{CPY, X, D }, {CMP, M, D }, {DEC, M, D }, {CMP, M, DLI },
|
||||
{INY, I, IMP }, {CMP, M, IMM }, {DEX, I, IMP }, {WAI, I, IMP },
|
||||
{CPY, X, A }, {CMP, M, A }, {DEC, M, A }, {CMP, M, AL },
|
||||
{op::CPY, X, IMM }, {op::CMP, M, DXI }, {op::LDT, I, IMM }, {op::CMP, M, S },
|
||||
{op::CPY, X, D }, {op::CMP, M, D }, {op::DEC, M, D }, {op::CMP, M, DLI },
|
||||
{op::INY, I, IMP }, {op::CMP, M, IMM }, {op::DEX, I, IMP }, {op::WAI, I, IMP },
|
||||
{op::CPY, X, A }, {op::CMP, M, A }, {op::DEC, M, A }, {op::CMP, M, AL },
|
||||
// 0xD0
|
||||
{BNE, I, RELB}, {CMP, M, DIY }, {CMP, M, DI }, {CMP, M, SIY },
|
||||
{PEI, I, PEI }, {CMP, M, DX }, {DEC, M, DX }, {CMP, M, DLIY},
|
||||
{CLD, I, IMP }, {CMP, M, AY }, {PHX, I, IMP }, {STP, I, IMP },
|
||||
{JML, I, AI }, {CMP, M, AX }, {DEC, M, AX }, {CMP, M, ALX },
|
||||
{op::BNE, I, RELB }, {op::CMP, M, DIY }, {op::CMP, M, DI }, {op::CMP, M, SIY },
|
||||
{op::PEI, I, PEI }, {op::CMP, M, DX }, {op::DEC, M, DX }, {op::CMP, M, DLIY },
|
||||
{op::CLD, I, IMP }, {op::CMP, M, AY }, {op::PHX, I, IMP }, {op::STP, I, IMP },
|
||||
{op::JML, I, AI }, {op::CMP, M, AX }, {op::DEC, M, AX }, {op::CMP, M, ALX },
|
||||
// 0xE0
|
||||
{CPX, X, IMM }, {SBC, M, DXI }, {SEP, I, IMM }, {SBC, M, S },
|
||||
{CPX, X, D }, {SBC, M, D }, {INC, M, D }, {SBC, M, DLI },
|
||||
{INX, M, IMP }, {SBC, M, IMM }, {NOP, I, IMP }, {XBA, I, IMP },
|
||||
{CPX, X, A }, {SBC, M, A }, {INC, M, A }, {SBC, M, AL },
|
||||
{op::CPX, X, IMM }, {op::SBC, M, DXI }, {op::SEP, I, IMM }, {op::SBC, M, S },
|
||||
{op::CPX, X, D }, {op::SBC, M, D }, {op::INC, M, D }, {op::SBC, M, DLI },
|
||||
{op::INX, M, IMP }, {op::SBC, M, IMM }, {op::NOP, I, IMP }, {op::XBA, I, IMP },
|
||||
{op::CPX, X, A }, {op::SBC, M, A }, {op::INC, M, A }, {op::SBC, M, AL },
|
||||
// 0xF0
|
||||
{BEQ, I, RELB}, {SBC, M, DIY }, {SBC, M, DI }, {SBC, M, SIY },
|
||||
{PEA, I, PEA }, {SBC, M, DX }, {INC, M, DX }, {SBC, M, DLIY},
|
||||
{SEM, I, IMP }, {SBC, M, AY }, {PLX, I, IMP }, {XCE, I, IMP },
|
||||
{JSR, I, AXI }, {SBC, M, AX }, {INC, M, AX }, {SBC, M, ALX }
|
||||
{op::BEQ, I, RELB }, {op::SBC, M, DIY }, {op::SBC, M, DI }, {op::SBC, M, SIY },
|
||||
{op::PEA, I, PEA }, {op::SBC, M, DX }, {op::INC, M, DX }, {op::SBC, M, DLIY },
|
||||
{op::SEM, I, IMP }, {op::SBC, M, AY }, {op::PLX, I, IMP }, {op::XCE, I, IMP },
|
||||
{op::JSR, I, AXI }, {op::SBC, M, AX }, {op::INC, M, AX }, {op::SBC, M, ALX }
|
||||
};
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
static inline unsigned int read_8(const UINT8 *oprom, unsigned int offset)
|
||||
{
|
||||
return oprom[offset];
|
||||
@ -389,33 +416,33 @@ int m7700_disassemble(char* buff, unsigned int pc, unsigned int pb, const UINT8
|
||||
// check for prefixes
|
||||
switch (instruction)
|
||||
{
|
||||
case 0x42:
|
||||
address++;
|
||||
length++;
|
||||
oprom++;
|
||||
instruction = read_8(oprom,0);
|
||||
opcode = g_opcodes_prefix42 + instruction;
|
||||
break;
|
||||
case 0x42:
|
||||
address++;
|
||||
length++;
|
||||
oprom++;
|
||||
instruction = read_8(oprom,0);
|
||||
opcode = &m7700_opcode_struct::get_prefix42(instruction);
|
||||
break;
|
||||
|
||||
case 0x89:
|
||||
address++;
|
||||
length++;
|
||||
oprom++;
|
||||
instruction = read_8(oprom,0);
|
||||
opcode = g_opcodes_prefix89 + instruction;
|
||||
break;
|
||||
case 0x89:
|
||||
address++;
|
||||
length++;
|
||||
oprom++;
|
||||
instruction = read_8(oprom,0);
|
||||
opcode = &m7700_opcode_struct::get_prefix89(instruction);
|
||||
break;
|
||||
|
||||
default:
|
||||
opcode = g_opcodes + instruction;
|
||||
break;
|
||||
default:
|
||||
opcode = &m7700_opcode_struct::get(instruction);
|
||||
break;
|
||||
}
|
||||
|
||||
if (opcode->name == JSR)
|
||||
if (opcode->is_call())
|
||||
flags = DASMFLAG_STEP_OVER;
|
||||
else if (opcode->name == RTS || opcode->name == RTI)
|
||||
else if (opcode->is_return())
|
||||
flags = DASMFLAG_STEP_OUT;
|
||||
|
||||
sprintf(buff, "%s", g_opnames[opcode->name]);
|
||||
sprintf(buff, "%s", opcode->name());
|
||||
ptr = buff + strlen(buff);
|
||||
|
||||
switch(opcode->ea)
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user