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https://github.com/holub/mame
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Retiring my original NCR5380 implementation. [R. Belmont, AJR]
This commit is contained in:
arbee
parent
3ee1c18a65
commit
e13ea1cd39
@ -3788,18 +3788,6 @@ if (MACHINES["I8255"]~=null) then
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/ncr5380.h,MACHINES["NCR5380"] = true
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---------------------------------------------------
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if (MACHINES["NCR5380"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/ncr5380.cpp",
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MAME_DIR .. "src/devices/machine/ncr5380.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/ncr5380n.h,MACHINES["NCR5380N"] = true
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@ -589,7 +589,6 @@ MACHINES["MSM5832"] = true
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MACHINES["MSM58321"] = true
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MACHINES["MSM6242"] = true
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MACHINES["MSM6253"] = true
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--MACHINES["NCR5380"] = true
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MACHINES["NCR5380N"] = true
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MACHINES["NCR5390"] = true
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MACHINES["NCR539x"] = true
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@ -620,7 +620,6 @@ MACHINES["MSM58321"] = true
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MACHINES["MSM6242"] = true
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--MACHINES["MSM6253"] = true
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MACHINES["MYB3K_KEYBOARD"] = true
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MACHINES["NCR5380"] = true
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MACHINES["NCR5380N"] = true
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MACHINES["NCR5385"] = true
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MACHINES["NCR5390"] = true
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@ -1,420 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:R. Belmont
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/*
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* ncr5380.c
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*
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* NCR 5380 SCSI controller, as seen in many 680x0 Macs,
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* official Apple add-on cards for the Apple II series,
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* and probably some PC and Amiga cards as well.
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*
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* Emulation by R. Belmont.
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*
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* References:
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* Zilog 5380 manual
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* "Inside Macintosh: Devices" (formerly online at http://www.manolium.org/dev/techsupport/insidemac/Devices/Devices-2.html )
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*
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* NOTES:
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* This implementation is tied closely to the drivers found in the Mac Plus ROM and the routines in Mac
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* System 6 and 7 that it patches out the ROM traps with. While attempts have been made to
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* have the behavior work according to the manual and not the specific Apple driver code,
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* there are almost certainly areas where that is true.
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*
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*/
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#include "emu.h"
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#include "ncr5380.h"
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//#define VERBOSE 1
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#include "logmacro.h"
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static const char *const rnames[] =
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{
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"Current data",
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"Initiator cmd",
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"Mode",
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"Target cmd",
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"Bus status",
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"Bus and status",
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"Input data",
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"Reset parity"
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};
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static const char *const wnames[] =
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{
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"Output data",
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"Initiator cmd",
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"Mode",
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"Target cmd",
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"Select enable",
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"Start DMA",
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"DMA target",
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"DMA initiator rec"
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};
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// get the length of a SCSI command based on it's command byte type
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static int get_cmd_len(int cbyte)
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{
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int group;
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group = (cbyte>>5) & 7;
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if (group == 0) return 6;
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if (group == 1 || group == 2) return 10;
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if (group == 5) return 12;
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fatalerror("NCR5380: Unknown SCSI command group %d\n", group);
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// never executed
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//return 6;
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}
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//**************************************************************************
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// LIVE DEVICE
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//**************************************************************************
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DEFINE_DEVICE_TYPE(NCR5380, ncr5380_device, "ncr5380", "NCR 5380 SCSI")
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//-------------------------------------------------
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// ncr5380_device - constructor/destructor
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//-------------------------------------------------
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ncr5380_device::ncr5380_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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legacy_scsi_host_adapter(mconfig, NCR5380, tag, owner, clock),
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m_irq_cb(*this)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void ncr5380_device::device_start()
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{
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legacy_scsi_host_adapter::device_start();
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memset(m_5380_Registers, 0, sizeof(m_5380_Registers));
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memset(m_5380_Data, 0, sizeof(m_5380_Data));
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m_next_req_flag = 0;
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m_irq_cb.resolve_safe();
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save_item(NAME(m_5380_Registers));
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save_item(NAME(m_5380_Command));
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save_item(NAME(m_5380_Data));
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save_item(NAME(m_last_id));
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save_item(NAME(m_cmd_ptr));
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save_item(NAME(m_d_ptr));
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save_item(NAME(m_d_limit));
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save_item(NAME(m_next_req_flag));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void ncr5380_device::device_reset()
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{
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memset(m_5380_Registers, 0, sizeof(m_5380_Registers));
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memset(m_5380_Data, 0, sizeof(m_5380_Data));
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m_next_req_flag = 0;
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m_cmd_ptr = 0;
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m_d_ptr = 0;
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m_d_limit = 0;
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m_last_id = 0;
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}
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//-------------------------------------------------
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// device_stop - device-specific stop/shutdown
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//-------------------------------------------------
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void ncr5380_device::device_stop()
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{
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}
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//-------------------------------------------------
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// Public API
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//-------------------------------------------------
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uint8_t ncr5380_device::ncr5380_read_reg(uint32_t offset)
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{
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int reg = offset & 7;
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uint8_t rv;
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switch( reg )
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{
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case R5380_CURDATA:
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case R5380_INPUTDATA:
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rv = m_5380_Registers[reg];
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// if we're in the data transfer phase or DMA, readback device data instead
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if (((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x04) || (m_5380_Registers[R5380_BUSSTATUS] & 0x40))
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{
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rv = m_5380_Data[m_d_ptr];
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// if the limit's less than 512, only read "limit" bytes
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if (m_d_limit < 512)
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{
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if (m_d_ptr < (m_d_limit-1))
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{
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m_d_ptr++;
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}
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else
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{
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m_next_req_flag = 1;
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}
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}
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else
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{
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if (m_d_ptr < 511)
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{
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m_d_ptr++;
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}
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else
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{
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m_d_limit -= 512;
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m_d_ptr = 0;
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m_next_req_flag = 1;
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// don't issue a "false" read
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if (m_d_limit > 0)
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{
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read_data(m_5380_Data, (m_d_limit < 512) ? m_d_limit : 512);
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}
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else
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{
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// if this is DMA, signal DMA end
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if (m_5380_Registers[R5380_BUSSTATUS] & 0x40)
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{
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m_5380_Registers[R5380_BUSSTATUS] |= 0x80;
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}
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// drop /REQ
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m_5380_Registers[R5380_BUSSTATUS] &= ~0x20;
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// clear phase match
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m_5380_Registers[R5380_BUSANDSTAT] &= ~0x08;
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}
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}
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}
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}
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break;
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default:
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rv = m_5380_Registers[reg];
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// temporarily drop /REQ
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if ((reg == R5380_BUSSTATUS) && (m_next_req_flag))
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{
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rv &= ~0x20;
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m_next_req_flag = 0;
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}
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break;
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}
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LOG("%s NCR5380: read %s (reg %d) = %02x\n", machine().describe_context(), rnames[reg], reg, rv);
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return rv;
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}
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void ncr5380_device::ncr5380_write_reg(uint32_t offset, uint8_t data)
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{
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int reg = offset & 7;
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LOG("%s NCR5380: %02x to %s (reg %d)\n", machine().describe_context(), data, wnames[reg], reg);
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switch( reg )
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{
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case R5380_OUTDATA:
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// if we're in the command phase, collect the command bytes
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if ((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x08)
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{
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m_5380_Command[m_cmd_ptr++] = data;
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}
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// if we're in the select phase, this is the target id
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if (m_5380_Registers[R5380_INICOMMAND] == 0x04)
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{
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data &= 0x7f; // clear the high bit
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if (data == 0x40)
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{
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m_last_id = 6;
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}
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else if (data == 0x20)
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{
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m_last_id = 5;
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}
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else if (data == 0x10)
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{
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m_last_id = 4;
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}
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else if (data == 0x08)
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{
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m_last_id = 3;
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}
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else if (data == 0x04)
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{
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m_last_id = 2;
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}
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else if (data == 0x02)
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{
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m_last_id = 1;
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}
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else if (data == 0x01)
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{
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m_last_id = 0;
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}
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}
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// if this is a write, accumulate accordingly
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if (((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x00) && (m_5380_Registers[R5380_INICOMMAND] == 1))
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{
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m_5380_Data[m_d_ptr] = data;
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// if we've hit a sector, flush
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if (m_d_ptr == 511)
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{
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write_data(&m_5380_Data[0], 512);
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m_d_limit -= 512;
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m_d_ptr = 0;
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// no more data? set DMA END flag
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if (m_d_limit <= 0)
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{
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m_5380_Registers[R5380_BUSANDSTAT] = 0xc8;
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}
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}
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else
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{
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m_d_ptr++;
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}
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// make sure we don't upset the status readback
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data = 0;
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}
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break;
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case R5380_INICOMMAND:
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if (data == 0) // dropping the bus
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{
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// make sure it's not busy
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m_5380_Registers[R5380_BUSSTATUS] &= ~0x40;
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// are we in the command phase?
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if ((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x08)
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{
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// is the current command complete?
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if (get_cmd_len(m_5380_Command[0]) == m_cmd_ptr)
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{
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LOG("%s NCR5380: Command (to ID %d): %x %x %x %x %x %x %x %x %x %x\n", machine().describe_context(), m_last_id, m_5380_Command[0], m_5380_Command[1], m_5380_Command[2], m_5380_Command[3], m_5380_Command[4], m_5380_Command[5], m_5380_Command[6], m_5380_Command[7], m_5380_Command[8], m_5380_Command[9]);
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send_command(&m_5380_Command[0], 16);
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m_d_limit = get_length();
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LOG("NCR5380: Command returned %d bytes\n", m_d_limit);
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m_d_ptr = 0;
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// is data available?
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if (m_d_limit > 0)
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{
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// make sure for transfers under 512 bytes that we always pad with a zero
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if (m_d_limit < 512)
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{
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m_5380_Data[m_d_limit] = 0;
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}
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// read back the amount available, or 512 bytes, whichever is smaller
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read_data(m_5380_Data, (m_d_limit < 512) ? m_d_limit : 512);
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// raise REQ to indicate data is available
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m_5380_Registers[R5380_BUSSTATUS] |= 0x20;
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}
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}
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}
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}
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if (data == 5) // want the bus?
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{
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// if the device exists, make the bus busy.
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// otherwise don't.
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if (select(m_last_id))
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{
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LOG("NCR5380: Giving the bus for ID %d\n", m_last_id);
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m_5380_Registers[R5380_BUSSTATUS] |= 0x40;
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}
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else
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{
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LOG("NCR5380: Rejecting the bus for ID %d\n", m_last_id);
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m_5380_Registers[R5380_BUSSTATUS] &= ~0x40;
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}
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}
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if (data == 1) // data bus (prelude to command?)
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{
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// raise REQ
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m_5380_Registers[R5380_BUSSTATUS] |= 0x20;
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}
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if (data & 0x10) // ACK drops REQ
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{
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// drop REQ
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m_5380_Registers[R5380_BUSSTATUS] &= ~0x20;
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}
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break;
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case R5380_MODE:
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if (data == 2) // DMA
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{
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// put us in DMA mode
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m_5380_Registers[R5380_BUSANDSTAT] |= 0x40;
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}
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if (data == 1) // arbitrate?
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{
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m_5380_Registers[R5380_INICOMMAND] |= 0x40; // set arbitration in progress
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m_5380_Registers[R5380_INICOMMAND] &= ~0x20; // clear "lost arbitration"
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}
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if (data == 0)
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{
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// drop DMA mode
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m_5380_Registers[R5380_BUSANDSTAT] &= ~0x40;
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}
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break;
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case R5380_TARGETCMD:
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// sync the bus phase with what was just written
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m_5380_Registers[R5380_BUSSTATUS] &= ~0x1c;
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m_5380_Registers[R5380_BUSSTATUS] |= (data & 7)<<2;
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// and set the "phase match" flag
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m_5380_Registers[R5380_BUSANDSTAT] |= 0x08;
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// and set /REQ
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m_5380_Registers[R5380_BUSSTATUS] |= 0x20;
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// if we're entering the command phase, start accumulating the data
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if ((m_5380_Registers[R5380_BUSSTATUS] & 0x1c) == 0x08)
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{
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m_cmd_ptr = 0;
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}
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break;
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default:
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break;
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}
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m_5380_Registers[reg] = data;
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// note: busandstat overlaps startdma, so we need to do this here!
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if (reg == R5380_STARTDMA)
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{
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m_5380_Registers[R5380_BUSANDSTAT] = 0x48;
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}
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}
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@ -1,70 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:R. Belmont
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/*
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* ncr5380.h SCSI controller
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*
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*/
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#ifndef MAME_MACHINE_NCR5380_H
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#define MAME_MACHINE_NCR5380_H
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#pragma once
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#include "legscsi.h"
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// 5380 registers
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enum
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{
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R5380_CURDATA = 0, // current SCSI data (read only)
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R5380_OUTDATA = 0, // output data (write only)
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R5380_INICOMMAND, // initiator command
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R5380_MODE, // mode
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R5380_TARGETCMD, // target command
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R5380_SELENABLE, // select enable (write only)
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R5380_BUSSTATUS = R5380_SELENABLE, // bus status (read only)
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R5380_STARTDMA, // start DMA send (write only)
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R5380_BUSANDSTAT = R5380_STARTDMA, // bus and status (read only)
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R5380_DMATARGET, // DMA target (write only)
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R5380_INPUTDATA = R5380_DMATARGET, // input data (read only)
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R5380_DMAINIRECV, // DMA initiator receive (write only)
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R5380_RESETPARITY = R5380_DMAINIRECV // reset parity/interrupt (read only)
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};
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// special Mac Plus registers - they implemented it weird
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#define R5380_OUTDATA_DTACK (R5380_OUTDATA | 0x10)
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#define R5380_CURDATA_DTACK (R5380_CURDATA | 0x10)
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|
||||
// device stuff
|
||||
|
||||
|
||||
class ncr5380_device : public legacy_scsi_host_adapter
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
ncr5380_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
auto irq_callback() { return m_irq_cb.bind(); }
|
||||
|
||||
// our API
|
||||
uint8_t ncr5380_read_reg(uint32_t offset);
|
||||
void ncr5380_write_reg(uint32_t offset, uint8_t data);
|
||||
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
virtual void device_stop() override;
|
||||
|
||||
private:
|
||||
uint8_t m_5380_Registers[8];
|
||||
uint8_t m_last_id;
|
||||
uint8_t m_5380_Command[32];
|
||||
int32_t m_cmd_ptr, m_d_ptr, m_d_limit, m_next_req_flag;
|
||||
uint8_t m_5380_Data[512];
|
||||
devcb_write_line m_irq_cb; /* irq callback */
|
||||
};
|
||||
|
||||
// device type definition
|
||||
DECLARE_DEVICE_TYPE(NCR5380, ncr5380_device)
|
||||
|
||||
#endif // MAME_MACHINE_NCR5380_H
|
||||
Loading…
Reference in New Issue
Block a user