mirror of
https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
David Haywood
commit
e147f99abe
@ -188,7 +188,19 @@ end
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---------------------------------------------------
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--
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--@src/emu/machine/68561mpcc.h,MACHINES["68561MPCC"] = true
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--@src/emu/machine/68230pit.h,MACHINES["PIT68230"] = true
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---------------------------------------------------
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if (MACHINES["PIT68230"]~=null) then
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files {
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MAME_DIR .. "src/emu/machine/68230pit.c",
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MAME_DIR .. "src/emu/machine/68230pit.h",
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}
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end
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---------------------------------------------------
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--
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--@src/emu/machine/68561mpcc.h,MACHINES += 68561MPCC
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---------------------------------------------------
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if (MACHINES["68561MPCC"]~=null) then
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@ -485,6 +485,7 @@ MACHINES["PCCARD"] = true
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MACHINES["PCF8593"] = true
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MACHINES["PCKEYBRD"] = true
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MACHINES["PIC8259"] = true
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MACHINES["PIT68230"] = true
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MACHINES["PIT8253"] = true
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MACHINES["PLA"] = true
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--MACHINES["PROFILE"] = true
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@ -722,6 +723,7 @@ function linkProjects_mame_mess(_target, _subtarget)
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"exidy",
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"fairch",
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"fidelity",
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"force",
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"fujitsu",
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"funtech",
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"galaxy",
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@ -1509,6 +1511,11 @@ files {
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MAME_DIR .. "src/mess/drivers/fidelz80.c",
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}
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createMESSProjects(_target, _subtarget, "force")
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files {
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MAME_DIR .. "src/mess/drivers/force68k.c",
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}
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createMESSProjects(_target, _subtarget, "fujitsu")
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files {
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MAME_DIR .. "src/mess/drivers/fmtowns.c",
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175
src/emu/machine/68230pit.c
Normal file
175
src/emu/machine/68230pit.c
Normal file
@ -0,0 +1,175 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edström
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/**********************************************************************
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Motorola MC68230 PI/T Parallell Interface and Timer
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Revisions
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2015-07-15 JLE initial
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Todo
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- Add clock and timers
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- Add all missing registers
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- Add configuration
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**********************************************************************/
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/*
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Force CPU-1 init sequence
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0801EA 0E0000 W 0000 PGCR data_w: 0000 -> 0000 & 00ff
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0801EA 0E0002 W 0000 PSRR data_w: 0000 -> 0001 & 00ff
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0801EA 0E0004 W FFFF PADDR data_w: 00ff -> 0002 & 00ff
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0801EA 0E0006 W 0000 PBDDR data_w: 0000 -> 0003 & 00ff
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0801F0 0E000C W 6060 PACR data_w: 0060 -> 0006 & 00ff
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0801F6 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
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0801FC 0E0000 W 3030 PGCR data_w: 0030 -> 0000 & 00ff
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080202 0E000E W A8A8 PBCR data_w: 00a8 -> 0007 & 00ff
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080210 0E000E W A0A0 PBCR data_w: 00a0 -> 0007 & 00ff
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Force CPU-1 after one keypress in terminal
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081DC0 0E000C W 6868 PACR
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081DC8 0E000C W 6060 PACR
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*/
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#include "emu.h"
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#include "68230pit.h"
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/***************************************************************************
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IMPLEMENTATION
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***************************************************************************/
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// device type definition
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const device_type PIT68230 = &device_creator<pit68230_device>;
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//-------------------------------------------------
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// pit68230_device - constructor
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//-------------------------------------------------
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pit68230_device::pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, PIT68230, "Motorola 68230 PI/T", tag, owner, clock, "pit68230", __FILE__)
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{
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}
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void pit68230_device::device_start()
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{
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printf("PIT68230 device started\n");
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}
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void pit68230_device::device_reset()
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{
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printf("PIT68230 device reseted\n");
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m_pgcr = 0;
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m_psrr = 0;
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m_paddr = 0;
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m_pbddr = 0;
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m_pcddr = 0;
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m_pacr = 0;
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m_pbcr = 0;
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m_padr = 0;
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m_pbdr = 0;
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m_psr = 0;
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}
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WRITE8_MEMBER( pit68230_device::data_w )
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{
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printf("data_w: %04x -> ", data);
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switch (offset)
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{
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case PIT_68230_PGCR:
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printf("PGCR");
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m_pgcr = data;
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break;
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case PIT_68230_PSRR:
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printf("PSRR");
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m_psrr = data;
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break;
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case PIT_68230_PADDR:
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printf("PADDR");
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m_paddr = data;
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break;
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case PIT_68230_PBDDR:
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printf("PBDDR");
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m_pbddr = data;
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break;
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case PIT_68230_PACR:
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printf("PACR");
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m_pacr = data;
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break;
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case PIT_68230_PBCR:
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printf("PBCR");
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m_pbcr = data;
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break;
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case PIT_68230_PADR:
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printf("PADR");
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m_padr = data;
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break;
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case PIT_68230_PSR:
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printf("PSR");
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m_padr = data;
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break;
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default:
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printf("unhandled register %02x", offset);
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}
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printf("\n");
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}
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READ8_MEMBER( pit68230_device::data_r )
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{
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UINT8 data = 0;
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printf("data_r: ");
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switch (offset)
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{
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case PIT_68230_PGCR:
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printf("PGCR");
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data = m_pgcr;
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break;
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case PIT_68230_PSRR:
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printf("PSRR");
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data = m_psrr;
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break;
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case PIT_68230_PADDR:
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printf("PADDR");
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data = m_paddr;
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break;
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case PIT_68230_PBDDR:
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printf("PBDDR");
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data = m_pbddr;
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break;
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case PIT_68230_PACR:
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printf("PACR");
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data = m_pacr;
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break;
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case PIT_68230_PBCR:
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printf("PBCR");
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data = m_pbcr;
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break;
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case PIT_68230_PADR:
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printf("PADR");
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data = m_padr;
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break;
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case PIT_68230_PBDR:
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/* 4.6.2. PORT B DATA REGISTER (PBDR). The port B data register is a holding register for moving data
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to and from port B pins. The port B data direction register determines whether each pin is an input (zero)
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or an output (one). This register is readable and writable at all times. Depending on the chosen mode/submode,
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reading or writing may affect the double-buffered handshake mechanism. The port B data register is not affected
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by the assertion of the RESET pin. PB0-PB7 sits on pins 17-24 on a 48 pin DIP package */
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printf("PBDR");
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data = m_pbdr;
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// data = (m_pbdr & 0xfc) | 1; // CPU-1 centronics interface expects to see 2 lowest bits equal 1 for printer
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break;
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case PIT_68230_PSR:
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printf("PSR");
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data = m_psr;
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// data = m_psr | 1; // CPU-1 centronics interface expects status to be non zero
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break;
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default:
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printf("unhandled register %02x", offset);
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data = 0;
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}
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printf("\n");
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return data;
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}
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75
src/emu/machine/68230pit.h
Normal file
75
src/emu/machine/68230pit.h
Normal file
@ -0,0 +1,75 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edström
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/**********************************************************************
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Motorola MC68230 PI/T Parallell Interface and Timer
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**********************************************************************/
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#pragma once
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#ifndef __68230PIT_H__
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#define __68230PIT_H__
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#include "emu.h"
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/*-----------------------------------------------------------------------
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Registers RS1-RS5 R/W Description
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-------------------------------------------------------------------------*/
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#define PIT_68230_PGCR 0x00 /* RW Port General Control register */
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#define PIT_68230_PSRR 0x01 /* RW Port Service Request register */
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#define PIT_68230_PADDR 0x02 /* RW Port A Data Direction register */
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#define PIT_68230_PBDDR 0x03 /* RW Port B Data Direction register */
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#define PIT_68230_PCDDR 0x04 /* RW Port C Data Direction register */
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#define PIT_68230_PIVR 0x05 /* RW Port Interrupt vector register */
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#define PIT_68230_PACR 0x06 /* RW Port A Control register */
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#define PIT_68230_PBCR 0x07 /* RW Port B Control register */
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#define PIT_68230_PADR 0x08 /* RW Port A Data register */
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#define PIT_68230_PBDR 0x09 /* RW Port B Data register */
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#define PIT_68230_PAAR 0x0a /* RO Port A Alternate register */
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#define PIT_68230_PBAR 0x0b /* RO Port B Alternate register */
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#define PIT_68230_PCDR 0x0c /* RW Port C Data register */
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#define PIT_68230_PSR 0x0d /* RW Port Status register */
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#define PIT_68230_TCR 0x10 /* RW Timer Control Register */
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#define PIT_68230_TIVR 0x11 /* RW Timer Interrupt Vector Register */
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#define PIT_68230_CPRH 0x13 /* RW Counter Preload Register High */
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#define PIT_68230_CPRM 0x14 /* RW Counter Preload Register Middle */
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#define PIT_68230_CPRL 0x15 /* RW Counter Preload Register Low */
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#define PIT_68230_CNTRH 0x17 /* RO Counter Register High */
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#define PIT_68230_CNTRM 0x18 /* RO Counter Register Middle */
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#define PIT_68230_CNTRL 0x19 /* RO Counter Register Low */
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#define PIT_68230_TSR 0x1A /* RW Timer Status Register */
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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class pit68230_device : public device_t
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{
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public:
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// construction/destruction
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pit68230_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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DECLARE_WRITE8_MEMBER( data_w );
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DECLARE_READ8_MEMBER( data_r );
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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private:
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UINT8 m_pgcr; // Port General Control register
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UINT8 m_psrr; // Port Service Request register
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UINT8 m_paddr; // Port A Data Direction register
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UINT8 m_pbddr; // Port B Data Direction register
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UINT8 m_pcddr; // Port C Data Direction register
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UINT8 m_pacr; // Port A Control register
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UINT8 m_pbcr; // Port B Control register
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UINT8 m_padr; // Port A Data register
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UINT8 m_pbdr; // Port B Data register
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UINT8 m_psr; // Port Status Register
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};
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// device type definition
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extern const device_type PIT68230;
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#endif // __68230PIT__
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@ -2585,6 +2585,7 @@ prose2ko
|
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eacc
|
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argo
|
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applix
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fccpu1
|
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68ksbc
|
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lcmate2
|
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cm1800
|
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|
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369
src/mess/drivers/force68k.c
Normal file
369
src/mess/drivers/force68k.c
Normal file
@ -0,0 +1,369 @@
|
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// license:BSD-3-Clause
|
||||
// copyright-holders:Joakim Larsson Edström
|
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/***************************************************************************
|
||||
|
||||
Force SYS68K CPU-1/CPU-6 VME SBC drivers, initially based on the 68ksbc.c
|
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|
||||
13/06/2015
|
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|
||||
The info found on the links below is for a later revisions of the board I have
|
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but I hope it is somewhat compatible so I can get it up and running at least.
|
||||
My CPU-1 board has proms from 1983 and no rev markings so probably the original.
|
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|
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http://bitsavers.trailing-edge.com/pdf/forceComputers/1988_Force_VMEbus_Products.pdf
|
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http://www.artisantg.com/info/P_wUovN.pdf
|
||||
|
||||
Some info from those documents:
|
||||
|
||||
Address Map
|
||||
----------------------------------------------------------
|
||||
Address Range Description
|
||||
----------------------------------------------------------
|
||||
000 000 - 000 007 Initialisation vectors from system EPROM
|
||||
000 008 - 01F FFF Dynamic RAM on CPU-1 B
|
||||
000 008 - 07F FFF Dynamic RAM on CPU-1 D
|
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080 008 - 09F FFF SYSTEM EPROM Area
|
||||
OAO 000 - OBF FFF USER EPROMArea
|
||||
0C0 041 - 0C0 043 ACIA (P3) Host
|
||||
0C0 080 - 0C0 082 ACIA (P4) Terminal
|
||||
0C0 101 - 0C0 103 ACIA (P5) Remote device (eg serial printer)
|
||||
0C0 401 - 0C0 42F RTC
|
||||
OEO 001 - 0E0 035 PI/T (eg centronics printer)
|
||||
OEO 200 - 0E0 2FF FPU
|
||||
OEO 300 - 0E0 300 Reset Off
|
||||
OEO 380 - 0E0 380 Reset On
|
||||
100 000 - FEF FFF VMEbus addresses (A24)
|
||||
FFO 000 - FFF FFF VMEbus Short I/O (A16)
|
||||
----------------------------------------------------------
|
||||
|
||||
Interrupt sources
|
||||
----------------------------------------------------------
|
||||
Description Device Lvl IRQ VME board
|
||||
/Board Vector Address
|
||||
----------------------------------------------------------
|
||||
On board Sources
|
||||
ABORT Switch 7 31
|
||||
Real Time Clock (RTC) 58167A 6 30
|
||||
Parallel/Timer (PI/T) 68230 5 29
|
||||
Terminal ACIA 6850 4 28
|
||||
Remote ACIA 6850 3 27
|
||||
Host ACIA 6850 2 26
|
||||
ACFAIL, SYSFAIL VME 5 29
|
||||
Off board Sources (other VME boards)
|
||||
6 Port Serial I/O board SIO 4 64-75 0xb00000
|
||||
8 Port Serial I/O board ISIO 4 76-83 0x960000
|
||||
Disk Controller WFC 3 119 0xb01000
|
||||
SCSI Controller ISCSI 4 119 0xa00000
|
||||
Slot 1 Controller Board ASCU 7 31 0xb02000
|
||||
----------------------------------------------------------
|
||||
|
||||
10. The VMEbus
|
||||
---------------
|
||||
The implemented VMEbus Interface includes 24 address, 16 data,
|
||||
6 address modifier and the asynchronous control signals.
|
||||
A single level bus arbiter is provided to build multi master
|
||||
systems. In addition to the bus arbiter, a separate slave bus
|
||||
arbitration allows selection of the arbitration level (0-3).
|
||||
|
||||
The address modifier range .,Short 110 Access« can be selected
|
||||
via a jumper for variable system generation. The 7 interrupt
|
||||
request levels of the VMEbus are fully supported from the
|
||||
SYS68K1CPU-1 B/D. For multi-processing, each IRQ signal can be
|
||||
enabled/disabled via a jumper field.
|
||||
|
||||
Additionally, the SYS68K1CPU-1 B/D supports the ACFAIL, SYSRESET,
|
||||
SYSFAIL and SYSCLK signal (16 MHz).
|
||||
|
||||
|
||||
TODO:
|
||||
- Finish 2 x ACIA6850, host and remote interface left, terminal works
|
||||
- Finish 1 x 68230 Motorola, Parallel Interface / Timer
|
||||
- Connect Port B to a Centronics printer interface
|
||||
- Add 1 x Abort Switch
|
||||
- Add configurable serial connector between ACIA:s and
|
||||
- Real terminal emulator, ie rs232 "socket"
|
||||
- Debug console
|
||||
- Add VME bus driver
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "machine/mm58167.h"
|
||||
#include "machine/68230pit.h"
|
||||
#include "machine/6850acia.h"
|
||||
#include "machine/clock.h"
|
||||
|
||||
#define BAUDGEN_CLOCK XTAL_1_8432MHz
|
||||
/*
|
||||
The baudrate on the Force68k CPU-1 to CPU-6 is generated by a
|
||||
Motorola 14411 bitrate generator, the CPU-6 documents matches the circuits
|
||||
that I could find on the CPU-1 board. Here how I calculated the clock for
|
||||
the factory settings. No need to add selectors until terminal.c supports
|
||||
configurable baudrates. Fortunality CPU-1 was shipped with 9600N8!
|
||||
|
||||
From the documents:
|
||||
|
||||
3 RS232C interfaces, strap selectable baud rate from 110-9600 or 600-19200 baud
|
||||
|
||||
Default Jumper Settings of B7:
|
||||
--------------------------------
|
||||
GND 10 - 11 RSA input on 14411
|
||||
F1 on 14411 1 - 20 Baud selector of the terminal port
|
||||
F1 on 14411 3 - 18 Baud selector of the host port
|
||||
F1 on 14411 5 - 16 Baud selector of the remote port
|
||||
|
||||
The RSB input on the 14411 is kept high always so RSA=0, RSB=1 and a 1.8432MHz crystal
|
||||
generates 153600 on the F1 output pin which by default strapping is connected to all
|
||||
three 6850 acias on the board. These can be strapped separatelly to speedup downloads.
|
||||
|
||||
The selectable outputs from 14411, F1-F16:
|
||||
X16 RSA=0,RSB=1: 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 3200, 2153.3, 1758.8, 1200, 921600, 1843000
|
||||
X64 RSA=1,RSB=1: 614400, 460800, 307200, 230400, 153600, 115200, 76800, 57600, 38400, 28800, 19200, 9600, 4800, 921600, 1843000
|
||||
|
||||
However, the datasheet says baudrate is strapable for 110-9600 but the output is 153600
|
||||
so the system rom MUST setup the acia to divide by 16 to generate the correct baudrate.
|
||||
|
||||
*/
|
||||
#define ACIA_CLOCK (BAUDGEN_CLOCK / 12)
|
||||
|
||||
class force68k_state : public driver_device
|
||||
{
|
||||
public:
|
||||
force68k_state(const machine_config &mconfig, device_type type, const char *tag) :
|
||||
driver_device(mconfig, type, tag),
|
||||
// m_rtc(*this, "rtc")
|
||||
m_maincpu(*this, "maincpu"),
|
||||
m_rtc(*this, "rtc"),
|
||||
m_pit(*this, "pit"),
|
||||
m_aciahost(*this, "aciahost"),
|
||||
m_aciaterm(*this, "aciaterm"),
|
||||
m_aciaremt(*this, "aciaremt")
|
||||
{
|
||||
}
|
||||
|
||||
DECLARE_READ16_MEMBER(bootvect_r);
|
||||
virtual void machine_start();
|
||||
DECLARE_WRITE_LINE_MEMBER(write_aciahost_clock);
|
||||
DECLARE_WRITE_LINE_MEMBER(write_aciaterm_clock);
|
||||
DECLARE_WRITE_LINE_MEMBER(write_aciaremt_clock);
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<mm58167_device> m_rtc;
|
||||
required_device<pit68230_device> m_pit;
|
||||
required_device<acia6850_device> m_aciahost;
|
||||
required_device<acia6850_device> m_aciaterm;
|
||||
required_device<acia6850_device> m_aciaremt;
|
||||
|
||||
// Pointer to System ROMs needed by bootvect_r
|
||||
UINT16 *m_sysrom;
|
||||
};
|
||||
|
||||
static ADDRESS_MAP_START(force68k_mem, AS_PROGRAM, 16, force68k_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x000000, 0x000007) AM_ROM AM_READ(bootvect_r) /* Vectors mapped from System EPROM */
|
||||
AM_RANGE(0x000008, 0x01ffff) AM_RAM /* DRAM */
|
||||
AM_RANGE(0x080000, 0x09ffff) AM_ROM /* System EPROM Area */
|
||||
// AM_RANGE(0x0a0000, 0x0bffff) AM_ROM /* User EPROM Area */
|
||||
AM_RANGE(0x0c0040, 0x0c0041) AM_DEVREADWRITE8("aciahost", acia6850_device, status_r, control_w, 0x00ff)
|
||||
AM_RANGE(0x0c0042, 0x0c0043) AM_DEVREADWRITE8("aciahost", acia6850_device, data_r, data_w, 0x00ff)
|
||||
AM_RANGE(0x0c0080, 0x0c0081) AM_DEVREADWRITE8("aciaterm", acia6850_device, status_r, control_w, 0xff00)
|
||||
AM_RANGE(0x0c0082, 0x0c0083) AM_DEVREADWRITE8("aciaterm", acia6850_device, data_r, data_w, 0xff00)
|
||||
AM_RANGE(0x0c0100, 0x0c0101) AM_DEVREADWRITE8("aciaremt", acia6850_device, status_r, control_w, 0x00ff)
|
||||
AM_RANGE(0x0c0102, 0x0c0103) AM_DEVREADWRITE8("aciaremt", acia6850_device, data_r, data_w, 0x00ff)
|
||||
AM_RANGE(0x0c0400, 0x0c042f) AM_DEVREADWRITE8("rtc", mm58167_device, read, write, 0x00ff)
|
||||
AM_RANGE(0x0e0000, 0x0e0035) AM_DEVREADWRITE8("pit", pit68230_device, data_r, data_w, 0x00ff)
|
||||
// AM_RANGE(0x0e0200, 0x0e0380) AM_READWRITE(fpu_r, fpu_w) /* optional FPCP 68881 FPU interface */
|
||||
// AM_RANGE(0x100000, 0xfeffff) /* VMEbus Rev B addresses (24 bits) */
|
||||
// AM_RANGE(0xff0000, 0xffffff) /* VMEbus Rev B addresses (16 bits) */
|
||||
ADDRESS_MAP_END
|
||||
|
||||
/* Input ports */
|
||||
static INPUT_PORTS_START( force68k )
|
||||
INPUT_PORTS_END
|
||||
|
||||
void force68k_state::machine_start()
|
||||
{
|
||||
m_sysrom = (UINT16*)(memregion("maincpu")->base() + 0x080000);
|
||||
}
|
||||
|
||||
READ16_MEMBER(force68k_state::bootvect_r)
|
||||
{
|
||||
return m_sysrom[offset];
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(force68k_state::write_aciahost_clock)
|
||||
{
|
||||
m_aciahost->write_txc(state);
|
||||
m_aciahost->write_rxc(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(force68k_state::write_aciaterm_clock)
|
||||
{
|
||||
m_aciaterm->write_txc(state);
|
||||
m_aciaterm->write_rxc(state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(force68k_state::write_aciaremt_clock)
|
||||
{
|
||||
m_aciaremt->write_txc(state);
|
||||
m_aciaremt->write_rxc(state);
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_START( fccpu1, force68k_state )
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD("maincpu", M68000, XTAL_16MHz / 2)
|
||||
MCFG_CPU_PROGRAM_MAP(force68k_mem)
|
||||
|
||||
/* P3/Host Port config */
|
||||
MCFG_DEVICE_ADD("aciahost", ACIA6850, 0)
|
||||
MCFG_DEVICE_ADD("aciahost_clock", CLOCK, ACIA_CLOCK)
|
||||
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciahost_clock))
|
||||
|
||||
/* P4/Terminal Port config */
|
||||
MCFG_DEVICE_ADD("aciaterm", ACIA6850, 0)
|
||||
|
||||
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_txd))
|
||||
MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232trm", rs232_port_device, write_rts))
|
||||
|
||||
MCFG_RS232_PORT_ADD("rs232trm", default_rs232_devices, "terminal")
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_rxd))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaterm", acia6850_device, write_cts))
|
||||
|
||||
MCFG_DEVICE_ADD("aciaterm_clock", CLOCK, ACIA_CLOCK)
|
||||
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
|
||||
|
||||
/* P5/Remote Port config */
|
||||
MCFG_DEVICE_ADD("aciaremt", ACIA6850, 0)
|
||||
|
||||
#define PRINTER 0
|
||||
#if PRINTER
|
||||
MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("rs232rmt", rs232_port_device, write_txd))
|
||||
MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("rs232rmt", rs232_port_device, write_rts))
|
||||
|
||||
MCFG_RS232_PORT_ADD("rs232rmt", default_rs232_devices, "printer")
|
||||
MCFG_RS232_RXD_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_rxd))
|
||||
MCFG_RS232_CTS_HANDLER(DEVWRITELINE("aciaremt", acia6850_device, write_cts))
|
||||
#endif
|
||||
|
||||
MCFG_DEVICE_ADD("aciaremt_clock", CLOCK, ACIA_CLOCK)
|
||||
MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(force68k_state, write_aciaterm_clock))
|
||||
|
||||
/* RTC Real Time Clock device */
|
||||
MCFG_DEVICE_ADD("rtc", MM58167, XTAL_32_768kHz)
|
||||
|
||||
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
|
||||
MCFG_DEVICE_ADD("pit", PIT68230, XTAL_16MHz / 2)
|
||||
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
#if 0
|
||||
|
||||
static MACHINE_CONFIG_START( fccpu6, force68k_state )
|
||||
MCFG_CPU_ADD("maincpu", M68000, XTAL_8MHz) /* Jumper B10 Mode B */
|
||||
MCFG_CPU_PROGRAM_MAP(force68k_mem)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( fccpu6a, force68k_state )
|
||||
MCFG_CPU_ADD("maincpu", M68000, XTAL_12_5MHz) /* Jumper B10 Mode A */
|
||||
MCFG_CPU_PROGRAM_MAP(force68k_mem)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( fccpu6v, force68k_state )
|
||||
MCFG_CPU_ADD("maincpu", M68010, XTAL_8MHz) /* Jumper B10 Mode B */
|
||||
MCFG_CPU_PROGRAM_MAP(force68k_mem)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( fccpu6va, force68k_state )
|
||||
MCFG_CPU_ADD("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
|
||||
MCFG_CPU_PROGRAM_MAP(force68k_mem)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_START( fccpu6vb, force68k_state )
|
||||
MCFG_CPU_ADD("maincpu", M68010, XTAL_12_5MHz) /* Jumper B10 Mode A */
|
||||
MCFG_CPU_PROGRAM_MAP(force68k_mem)
|
||||
MACHINE_CONFIG_END
|
||||
#endif
|
||||
|
||||
/* ROM definitions */
|
||||
ROM_START( fccpu1 )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
|
||||
ROM_LOAD16_BYTE( "fccpu1V1.0L.j8.bin", 0x080001, 0x2000, CRC(3ac6f08f) SHA1(502f6547b508d8732bd68bbbb2402d8c30fefc3b) )
|
||||
ROM_LOAD16_BYTE( "fccpu1V1.0L.j9.bin", 0x080000, 0x2000, CRC(035315fb) SHA1(90dc44d9c25d28428233e6846da6edce2d69e440) )
|
||||
/* COMMAND SUMMARY DESCRIPTION (From CPU-1B datasheet, ROMs were dumped
|
||||
from a CPU-1 board so some features might be missing or different)
|
||||
---------------------------------------------------------------------------
|
||||
BF <address1> <address2> <data> <CR> Block Fill memory - from addr1 through addr2 with data
|
||||
BM <address1> <address2> <address 3> <CR> Block Move - move from addr1 through addr2to addr3
|
||||
BR [<address> [; <count>] ... ] <CR> Set/display Breakpoint
|
||||
BS <address1> <address2> <data> <CR> Block Search - search addr1 through addr2 for data
|
||||
BT <address1> <address2> <CR> Block Test of memory
|
||||
DC <expression> <CR> Data Conversion
|
||||
DF <CR> Display Formatted registers
|
||||
DU [n] <address1> <address2>[<string>] <CR> Dump memory to object file
|
||||
GO [<address] <CR> Execute program
|
||||
GD [<address] <CR> Go Direct
|
||||
GT <address> <CR> Exec prog: temporary breakpoint
|
||||
HE<CR> Help; display monitor commands
|
||||
LO [n] [;<options] <CR> Load Object file
|
||||
MD <address> [<count» <CR> Memory Display
|
||||
MM <address> [<data» [;<options» <CR> Memory Modify
|
||||
MS <address> <data1 > <data2> < ... <CR> Memory Set - starting at addr with data 1. data 2 ...
|
||||
NOBR [<address> ... ] <CR> Remove Breakpoint
|
||||
NOPA <CR> Printer Detach (Centronics on PIT/P2)
|
||||
OF <CR> Offset
|
||||
PA <CR> Printer Attach (Centronics on PIT/P2)
|
||||
PF[n] <CR> Set/display Port Format
|
||||
RM <CR> Register Modify
|
||||
TM [<exit character» <CR> Transparent Mode
|
||||
TR [<count] <CR> Trace
|
||||
TT <address> <CR> Trace: temporary breakpoint
|
||||
VE [n] [<string] <CR> Verify memory/object file
|
||||
----------------------------------------------------------------------------
|
||||
.AO - .A7 [<expression] <CR> Display/set address register
|
||||
.00 - .07 [<expression] <CR> Display/set data register
|
||||
.RO - .R6 [<expression] <CR> Display/set offset register
|
||||
.PC [<expression] <CR> Display/set program counter
|
||||
.SR [<expression] <CR> Display/set status register
|
||||
.SS [<expression] <CR> Display/set supervisor stack
|
||||
.US [<expression] <CR> Display/set user stack
|
||||
----------------------------------------------------------------------------
|
||||
MD <address> [<count>]; D1 <CR> Disassemble memory location
|
||||
MM <address>; DI <CR> Disassemble/Assemble memory location
|
||||
----------------------------------------------------------------------------
|
||||
*/
|
||||
ROM_END
|
||||
|
||||
#if 0
|
||||
ROM_START( fccpu6 )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
ROM_END
|
||||
|
||||
ROM_START( fccpu6a )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
ROM_END
|
||||
|
||||
ROM_START( fccpu6v )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
ROM_END
|
||||
|
||||
ROM_START( fccpu6va )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
ROM_END
|
||||
|
||||
ROM_START( fccpu6vb )
|
||||
ROM_REGION(0x1000000, "maincpu", 0)
|
||||
ROM_END
|
||||
#endif
|
||||
|
||||
/* Driver */
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||
COMP( 1983, fccpu1, 0, 0, fccpu1, force68k, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-1", GAME_NO_SOUND_HW | GAME_TYPE_COMPUTER )
|
||||
//COMP( 1989, fccpu6, 0, 0, fccpu6, force68k, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-6", GAME_IS_SKELETON )
|
||||
//COMP( 1989, fccpu6a, 0, 0, fccpu6a, force68k, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-6a", GAME_IS_SKELETON )
|
||||
//COMP( 1989, fccpu6v, 0, 0, fccpu6v, force68k, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-6v", GAME_IS_SKELETON )
|
||||
//COMP( 1989, fccpu6va, 0, 0, fccpu6va, force68k, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-6va", GAME_IS_SKELETON )
|
||||
//COMP( 1989, fccpu6vb, 0, 0, fccpu6vb, force68k, driver_device, 0, "Force Computers Gmbh", "SYS68K/CPU-6vb", GAME_IS_SKELETON )
|
||||
Loading…
Reference in New Issue
Block a user