mirror of
https://github.com/holub/mame
synced 2025-06-04 20:06:28 +03:00
-hal2: Various changes. [Ryan Holtz]
* Added handling for different frequency rates. * Moved DAC devices into HAL2 from HPC3. * Added readback of DAC parameters. * Fixed stereo DAC playback.
This commit is contained in:
mooglyguy
MooglyGuy
parent
e72d1130fe
commit
e15b2b50ad
@ -21,8 +21,8 @@ DEFINE_DEVICE_TYPE(SGI_HAL2, hal2_device, "hal2", "SGI HAL2")
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hal2_device::hal2_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: device_t(mconfig, SGI_HAL2, tag, owner, clock)
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, m_iar(0)
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, m_idr{0, 0, 0, 0}
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, m_ldac(*this, "ldac")
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, m_rdac(*this, "rdac")
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{
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}
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@ -31,6 +31,19 @@ void hal2_device::device_start()
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save_item(NAME(m_isr));
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save_item(NAME(m_iar));
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save_item(NAME(m_idr));
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save_item(NAME(m_codeca_ctrl));
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save_item(NAME(m_codeca_channel));
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save_item(NAME(m_codeca_clock));
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save_item(NAME(m_codeca_channel_count));
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save_item(NAME(m_codecb_ctrl));
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save_item(NAME(m_codecb_channel));
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save_item(NAME(m_codecb_clock));
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save_item(NAME(m_codecb_channel_count));
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save_item(NAME(m_bres_clock_sel));
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save_item(NAME(m_bres_clock_inc));
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save_item(NAME(m_bres_clock_modctrl));
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save_item(NAME(m_bres_clock_freq));
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save_item(NAME(m_curr_dac));
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}
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void hal2_device::device_reset()
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@ -38,6 +51,23 @@ void hal2_device::device_reset()
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m_isr = 0;
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m_iar = 0;
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memset(m_idr, 0, sizeof(uint32_t) * 4);
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memset(m_codeca_ctrl, 0, sizeof(uint32_t) * 2);
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m_codeca_channel = 0;
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m_codeca_clock = 0;
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m_codeca_channel_count = 0;
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memset(m_codecb_ctrl, 0, sizeof(uint32_t) * 2);
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m_codecb_channel = 0;
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m_codecb_clock = 0;
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m_codecb_channel_count = 0;
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memset(m_bres_clock_sel, 0, sizeof(uint32_t) * 3);
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memset(m_bres_clock_inc, 0, sizeof(uint32_t) * 3);
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memset(m_bres_clock_modctrl, 0, sizeof(uint32_t) * 3);
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memset(m_bres_clock_freq, 0, sizeof(uint32_t) * 3);
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for (int i = 0; i < 3; i++)
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{
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m_bres_clock_rate[i] = attotime::zero;
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}
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m_curr_dac = 0;
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}
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READ32_MEMBER(hal2_device::read)
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@ -50,6 +80,22 @@ READ32_MEMBER(hal2_device::read)
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case REVISION_REG:
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LOGMASKED(LOG_READS, "%s: HAL2 Revision Read: 0x4011\n", machine().describe_context());
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return 0x4011;
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case INDIRECT_DATA0_REG:
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LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 0 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask);
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return m_idr[0];
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case INDIRECT_DATA1_REG:
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LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 1 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask);
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return m_idr[1];
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case INDIRECT_DATA2_REG:
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LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 2 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask);
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return m_idr[2];
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case INDIRECT_DATA3_REG:
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LOGMASKED(LOG_WRITES, "%s: HAL2 Indirect Data Register 3 Read: %08x & %08x\n", machine().describe_context(), m_idr[3], mem_mask);
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return m_idr[3];
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}
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LOGMASKED(LOG_READS | LOG_UNKNOWN, "%s: Unknown HAL2 read: %08x & %08x\n", machine().describe_context(), 0x1fbd8000 + offset*4, mem_mask);
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return 0;
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@ -85,31 +131,143 @@ WRITE32_MEMBER(hal2_device::write)
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LOGMASKED(LOG_WRITES, " AES Out\n");
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break;
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case 0x0400:
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LOGMASKED(LOG_WRITES, " DAC Out\n");
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{
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LOGMASKED(LOG_WRITES, " Codec A (DAC) Out\n");
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const uint32_t param = (data & IAR_PARAM) >> IAR_PARAM_SHIFT;
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switch (param)
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{
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case 1:
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LOGMASKED(LOG_WRITES, " Control 1\n");
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if (data & IAR_ACCESS_SEL)
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{
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m_idr[0] = m_codeca_ctrl[0];
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}
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else
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{
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m_codeca_ctrl[0] = m_idr[0];
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m_codeca_channel = m_idr[0] & 3;
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m_codeca_clock = (m_idr[0] >> 3) & 3;
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m_codeca_channel_count = (m_idr[0] >> 8) & 3;
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}
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break;
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case 2:
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LOGMASKED(LOG_WRITES, " Control 2\n");
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if (data & IAR_ACCESS_SEL)
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{
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m_idr[0] = m_codeca_ctrl[1];
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}
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else
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{
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m_codeca_ctrl[1] = m_idr[0];
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}
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break;
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default:
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LOGMASKED(LOG_WRITES, " Unknown Register\n");
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break;
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}
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break;
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}
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case 0x0500:
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LOGMASKED(LOG_WRITES, " ADC Out\n");
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{
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LOGMASKED(LOG_WRITES, " Codec B (ADC) Out\n");
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const uint32_t param = (data & IAR_PARAM) >> IAR_PARAM_SHIFT;
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switch (param)
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{
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case 1:
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LOGMASKED(LOG_WRITES, " Control 1\n");
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if (data & IAR_ACCESS_SEL)
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{
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m_idr[0] = m_codecb_ctrl[0];
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}
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else
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{
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m_codecb_ctrl[0] = m_idr[0];
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m_codecb_channel = m_idr[0] & 3;
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m_codecb_clock = (m_idr[0] >> 3) & 3;
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m_codecb_channel_count = (m_idr[0] >> 8) & 3;
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}
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break;
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case 2:
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LOGMASKED(LOG_WRITES, " Control 2\n");
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if (data & IAR_ACCESS_SEL)
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{
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m_idr[0] = m_codecb_ctrl[1];
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}
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else
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{
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m_codecb_ctrl[1] = m_idr[0];
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}
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break;
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default:
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LOGMASKED(LOG_WRITES, " Unknown Register\n");
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break;
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}
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break;
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}
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case 0x0600:
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LOGMASKED(LOG_WRITES, " Synth Control\n");
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break;
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default:
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LOGMASKED(LOG_WRITES, " Unknown\n");
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break;
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}
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break;
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case 0x2000:
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{
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LOGMASKED(LOG_WRITES, " Bresenham\n");
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switch (data & IAR_NUM)
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uint32_t clock_gen = (data & IAR_NUM) >> IAR_NUM_SHIFT;
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if (clock_gen >= 1 && clock_gen <= 3)
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{
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case 0x0100:
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LOGMASKED(LOG_WRITES, " Bresenham Clock Gen 1\n");
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break;
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case 0x0200:
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LOGMASKED(LOG_WRITES, " Bresenham Clock Gen 2\n");
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break;
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case 0x0300:
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LOGMASKED(LOG_WRITES, " Bresenham Clock Gen 3\n");
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break;
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LOGMASKED(LOG_WRITES, " Bresenham Clock Gen %d\n", clock_gen);
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clock_gen--;
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const uint32_t param = (data & IAR_PARAM) >> IAR_PARAM_SHIFT;
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if (param == 1)
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{
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LOGMASKED(LOG_WRITES, " Control 1 (Clock Select)\n");
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if (data & IAR_ACCESS_SEL)
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{
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m_idr[0] = m_bres_clock_sel[clock_gen];
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}
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else
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{
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m_bres_clock_sel[clock_gen] = m_idr[0];
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switch (m_idr[0])
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{
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case 0: LOGMASKED(LOG_WRITES, " 48kHz\n"); break;
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case 1: LOGMASKED(LOG_WRITES, " 44.1kHz\n"); break;
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case 2: LOGMASKED(LOG_WRITES, " Off\n"); break;
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default: LOGMASKED(LOG_WRITES, " Unknown (%d)\n", m_idr[0]); break;
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}
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update_clock_freq(clock_gen);
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}
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}
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else if (param == 2)
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{
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LOGMASKED(LOG_WRITES, " Control 2 (Inc/Mod Ctrl)\n");
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if (data & IAR_ACCESS_SEL)
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{
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m_idr[0] = m_bres_clock_inc[clock_gen];
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m_idr[1] = m_bres_clock_modctrl[clock_gen];
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}
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else
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{
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m_bres_clock_inc[clock_gen] = m_idr[0];
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m_bres_clock_modctrl[clock_gen] = m_idr[1];
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LOGMASKED(LOG_WRITES, " Inc:%04x, ModCtrl:%04x\n", (uint16_t)m_idr[0], (uint16_t)m_idr[1]);
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update_clock_freq(clock_gen);
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}
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}
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else
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{
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LOGMASKED(LOG_WRITES, " Unknown Param\n");
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}
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}
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else
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{
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LOGMASKED(LOG_WRITES, " Unknown\n");
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}
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break;
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}
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case 0x3000:
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LOGMASKED(LOG_WRITES, " Unix Timer\n");
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@ -118,6 +276,9 @@ WRITE32_MEMBER(hal2_device::write)
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case 0x0100:
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LOGMASKED(LOG_WRITES, " Unix Timer\n");
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break;
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default:
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LOGMASKED(LOG_WRITES, " Unknown\n");
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break;
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}
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break;
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@ -128,19 +289,18 @@ WRITE32_MEMBER(hal2_device::write)
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case 0x0100:
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LOGMASKED(LOG_WRITES, " DMA Control\n");
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break;
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default:
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LOGMASKED(LOG_WRITES, " Unknown\n");
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break;
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}
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break;
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}
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switch (data & IAR_ACCESS_SEL)
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{
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case 0x0000:
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LOGMASKED(LOG_WRITES, " Write\n");
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break;
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case 0x0080:
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if (data & IAR_ACCESS_SEL)
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LOGMASKED(LOG_WRITES, " Read\n");
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break;
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}
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else
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LOGMASKED(LOG_WRITES, " Write\n");
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LOGMASKED(LOG_WRITES, " Parameter: %01x\n", (data & IAR_PARAM) >> 2);
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return;
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@ -169,3 +329,68 @@ WRITE32_MEMBER(hal2_device::write)
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break;
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}
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}
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void hal2_device::update_clock_freq(int clock_gen)
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{
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switch (m_bres_clock_sel[clock_gen])
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{
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case 0: // 48kHz
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m_bres_clock_freq[clock_gen] = 48000;
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break;
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case 1: // 44.1kHz
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m_bres_clock_freq[clock_gen] = 44100;
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break;
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default:
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m_bres_clock_freq[clock_gen] = 0;
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m_bres_clock_rate[clock_gen] = attotime::zero;
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return;
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}
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const uint32_t mod = 0x10000 - (((uint16_t)m_bres_clock_modctrl[clock_gen] + 1) - m_bres_clock_inc[clock_gen]);
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if (mod == 0)
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m_bres_clock_rate[clock_gen] = attotime::from_ticks(1, m_bres_clock_freq[clock_gen] * m_bres_clock_inc[clock_gen]);
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else
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m_bres_clock_rate[clock_gen] = attotime::from_ticks(mod, m_bres_clock_freq[clock_gen] * m_bres_clock_inc[clock_gen]);
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}
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attotime hal2_device::get_rate(const uint32_t channel)
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{
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if ((channel == m_codeca_channel || channel == (3 - m_codeca_channel)) && m_codeca_clock > 0 && m_codeca_channel_count > 0)
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return m_bres_clock_rate[m_codeca_clock - 1] / m_codeca_channel_count;
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if ((channel == m_codecb_channel || channel == (3 - m_codecb_channel)) && m_codecb_clock > 0 && m_codecb_channel_count > 0)
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return m_bres_clock_rate[m_codecb_clock - 1] / m_codecb_channel_count;
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return attotime::zero;
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}
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void hal2_device::dma_write(uint32_t channel, int16_t data)
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{
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if (channel >= 2)
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return;
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if (m_curr_dac)
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m_rdac->write(data);
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else
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m_ldac->write(data);
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m_curr_dac++;
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if (m_curr_dac == m_codeca_channel_count)
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m_curr_dac = 0;
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}
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void hal2_device::device_add_mconfig(machine_config &config)
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{
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SPEAKER(config, "lspeaker").front_left();
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SPEAKER(config, "rspeaker").front_right();
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DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_ldac, 0);
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m_ldac->add_route(ALL_OUTPUTS, "lspeaker", 0.25);
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DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_rdac, 0);
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m_rdac->add_route(ALL_OUTPUTS, "rspeaker", 0.25);
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voltage_regulator_device &vreg = VOLTAGE_REGULATOR(config, "vref");
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vreg.add_route(0, "ldac", 1.0, DAC_VREF_POS_INPUT);
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vreg.add_route(0, "rdac", 1.0, DAC_VREF_POS_INPUT);
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vreg.add_route(0, "ldac", -1.0, DAC_VREF_NEG_INPUT);
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vreg.add_route(0, "rdac", -1.0, DAC_VREF_NEG_INPUT);
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}
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@ -11,6 +11,10 @@
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#pragma once
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#include "sound/dac.h"
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#include "sound/volt_reg.h"
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#include "speaker.h"
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class hal2_device : public device_t
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{
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public:
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@ -24,17 +28,30 @@ public:
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DECLARE_WRITE32_MEMBER(write);
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DECLARE_READ32_MEMBER(read);
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attotime get_rate(const uint32_t channel);
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void set_right_volume(uint8_t vol) { m_rdac->set_output_gain(ALL_OUTPUTS, vol / 255.0f); }
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void set_left_volume(uint8_t vol) { m_ldac->set_output_gain(ALL_OUTPUTS, vol / 255.0f); }
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void dma_write(uint32_t channel, int16_t data);
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protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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virtual void device_add_mconfig(machine_config &config) override;
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void update_clock_freq(int clock_gen);
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enum
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{
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IAR_TYPE = 0xf000,
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IAR_NUM = 0x0f00,
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IAR_ACCESS_SEL = 0x0080,
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IAR_PARAM = 0x000c,
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IAR_RB_INDEX = 0x0003,
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IAR_TYPE = 0xf000,
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IAR_TYPE_SHIFT = 12,
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IAR_NUM = 0x0f00,
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IAR_NUM_SHIFT = 8,
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IAR_ACCESS_SEL = 0x0080,
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IAR_PARAM = 0x000c,
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IAR_PARAM_SHIFT = 2,
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IAR_RB_INDEX = 0x0003
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};
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enum
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@ -57,9 +74,38 @@ protected:
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INDIRECT_DATA3_REG = 0x0070/4,
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};
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enum
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{
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DAC_L,
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DAC_R
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};
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required_device<dac_16bit_r2r_twos_complement_device> m_ldac;
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required_device<dac_16bit_r2r_twos_complement_device> m_rdac;
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uint32_t m_isr;
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uint32_t m_iar;
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uint32_t m_idr[4];
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uint32_t m_codeca_ctrl[2];
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uint32_t m_codeca_channel;
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uint32_t m_codeca_clock;
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uint32_t m_codeca_channel_count;
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uint32_t m_codecb_ctrl[2];
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uint32_t m_codecb_channel;
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uint32_t m_codecb_clock;
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uint32_t m_codecb_channel_count;
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uint32_t m_bres_clock_sel[3];
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uint32_t m_bres_clock_inc[3];
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uint32_t m_bres_clock_modctrl[3];
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uint32_t m_bres_clock_freq[3];
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attotime m_bres_clock_rate[3];
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uint32_t m_curr_dac;
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static const uint32_t s_channel_pair[4];
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};
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DECLARE_DEVICE_TYPE(SGI_HAL2, hal2_device)
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@ -45,8 +45,6 @@ hpc3_base_device::hpc3_base_device(const machine_config &mconfig, device_type ty
|
||||
, m_rtc(*this, "rtc")
|
||||
, m_ioc2(*this, "ioc2")
|
||||
, m_hal2(*this, "hal2")
|
||||
, m_ldac(*this, "ldac")
|
||||
, m_rdac(*this, "rdac")
|
||||
{
|
||||
}
|
||||
|
||||
@ -148,21 +146,6 @@ void hpc3_base_device::device_reset()
|
||||
|
||||
void hpc3_base_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
SPEAKER(config, "lspeaker").front_left();
|
||||
SPEAKER(config, "rspeaker").front_right();
|
||||
|
||||
DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_ldac, 0);
|
||||
m_ldac->add_route(ALL_OUTPUTS, "lspeaker", 0.25);
|
||||
|
||||
DAC_16BIT_R2R_TWOS_COMPLEMENT(config, m_rdac, 0);
|
||||
m_rdac->add_route(ALL_OUTPUTS, "rspeaker", 0.25);
|
||||
|
||||
voltage_regulator_device &vreg = VOLTAGE_REGULATOR(config, "vref");
|
||||
vreg.add_route(0, "ldac", 1.0, DAC_VREF_POS_INPUT);
|
||||
vreg.add_route(0, "rdac", 1.0, DAC_VREF_POS_INPUT);
|
||||
vreg.add_route(0, "ldac", -1.0, DAC_VREF_NEG_INPUT);
|
||||
vreg.add_route(0, "rdac", -1.0, DAC_VREF_NEG_INPUT);
|
||||
|
||||
SGI_HAL2(config, m_hal2);
|
||||
|
||||
DS1386_8K(config, m_rtc, 32768);
|
||||
@ -237,10 +220,7 @@ void hpc3_base_device::do_pbus_dma(uint32_t channel)
|
||||
uint16_t temp16 = m_cpu_space->read_dword(dma.m_cur_ptr) >> 16;
|
||||
int16_t stemp16 = (int16_t)((temp16 >> 8) | (temp16 << 8));
|
||||
|
||||
if (channel == 1)
|
||||
m_ldac->write(stemp16);
|
||||
else if (channel == 2)
|
||||
m_rdac->write(stemp16);
|
||||
m_hal2->dma_write(channel, stemp16);
|
||||
|
||||
dma.m_cur_ptr += 4;
|
||||
dma.m_bytes_left -= 4;
|
||||
@ -266,7 +246,7 @@ void hpc3_base_device::do_pbus_dma(uint32_t channel)
|
||||
return;
|
||||
}
|
||||
}
|
||||
dma.m_timer->adjust(attotime::from_hz(44100));
|
||||
dma.m_timer->adjust(m_hal2->get_rate(channel));
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -646,12 +626,12 @@ WRITE32_MEMBER(hpc3_base_device::volume_w)
|
||||
if (offset == 0)
|
||||
{
|
||||
m_volume_r = (uint8_t)data;
|
||||
m_rdac->set_output_gain(ALL_OUTPUTS, m_volume_r / 255.0f);
|
||||
m_hal2->set_right_volume((uint8_t)data);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_volume_l = (uint8_t)data;
|
||||
m_ldac->set_output_gain(ALL_OUTPUTS, m_volume_l / 255.0f);
|
||||
m_hal2->set_left_volume((uint8_t)data);
|
||||
}
|
||||
}
|
||||
|
||||
@ -765,7 +745,6 @@ WRITE32_MEMBER(hpc3_base_device::pbus4_w)
|
||||
READ32_MEMBER(hpc3_base_device::pbusdma_r)
|
||||
{
|
||||
uint32_t channel = offset / (0x2000/4);
|
||||
LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Read: %08x & %08x\n", machine().describe_context(), channel, 0x1fb80000 + offset*4, mem_mask);
|
||||
pbus_dma_t &dma = m_pbus_dma[channel];
|
||||
|
||||
uint32_t ret = 0;
|
||||
@ -836,8 +815,12 @@ WRITE32_MEMBER(hpc3_base_device::pbusdma_w)
|
||||
if (((data & PBUS_CTRL_DMASTART) && (data & PBUS_CTRL_LOAD_EN)) && channel < 4)
|
||||
{
|
||||
LOGMASKED(LOG_PBUS_DMA, " Starting DMA\n");
|
||||
dma.m_timer->adjust(attotime::from_hz(44100));
|
||||
dma.m_active = true;
|
||||
attotime rate = m_hal2->get_rate(channel);
|
||||
if (rate != attotime::zero)
|
||||
{
|
||||
dma.m_timer->adjust(rate);
|
||||
dma.m_active = true;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
|
||||
@ -16,9 +16,6 @@
|
||||
#include "machine/hal2.h"
|
||||
#include "machine/ioc2.h"
|
||||
#include "machine/wd33c9x.h"
|
||||
#include "sound/dac.h"
|
||||
#include "sound/volt_reg.h"
|
||||
#include "speaker.h"
|
||||
|
||||
class hpc3_base_device : public device_t
|
||||
{
|
||||
@ -149,8 +146,6 @@ protected:
|
||||
required_device<ds1386_device> m_rtc;
|
||||
required_device<ioc2_device> m_ioc2;
|
||||
required_device<hal2_device> m_hal2;
|
||||
required_device<dac_16bit_r2r_twos_complement_device> m_ldac;
|
||||
required_device<dac_16bit_r2r_twos_complement_device> m_rdac;
|
||||
|
||||
uint32_t m_intstat;
|
||||
uint32_t m_cpu_aux_ctrl;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user