From e187bc4a43cbfa7da8b03d12df6d92e461db666c Mon Sep 17 00:00:00 2001 From: Curt Coder Date: Sun, 9 Feb 2014 21:52:06 +0000 Subject: [PATCH] (MESS) c2040: Fixed READY signal. (nw) --- src/emu/bus/ieee488/c2040fdc.c | 48 ++++++++++++++++++---------------- src/emu/bus/ieee488/c2040fdc.h | 1 + 2 files changed, 27 insertions(+), 22 deletions(-) diff --git a/src/emu/bus/ieee488/c2040fdc.c b/src/emu/bus/ieee488/c2040fdc.c index 85a9df1b387..49b06f6a9c3 100644 --- a/src/emu/bus/ieee488/c2040fdc.c +++ b/src/emu/bus/ieee488/c2040fdc.c @@ -14,8 +14,6 @@ TODO: - writing starts in the middle of a byte - - READY output is actually low when (CNT=9 QB=0), but since we latch the read - byte on syncpoints, READY is low when (prevCNT=9 CNT=0) as seen below - 8050 PLL */ @@ -90,6 +88,8 @@ c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, device_type type, const cur_live.tm = attotime::never; cur_live.state = IDLE; cur_live.next_state = -1; + cur_live.write_position = 0; + cur_live.write_start_time = attotime::never; } c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : @@ -113,6 +113,8 @@ c2040_fdc_t::c2040_fdc_t(const machine_config &mconfig, const char *tag, device_ cur_live.tm = attotime::never; cur_live.state = IDLE; cur_live.next_state = -1; + cur_live.write_position = 0; + cur_live.write_start_time = attotime::never; } c8050_fdc_t::c8050_fdc_t(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) : @@ -133,6 +135,16 @@ void c2040_fdc_t::device_start() // allocate timer t_gen = timer_alloc(0); + + // register for state saving + save_item(NAME(m_mtr0)); + save_item(NAME(m_mtr1)); + save_item(NAME(m_stp0)); + save_item(NAME(m_stp1)); + save_item(NAME(m_ds)); + save_item(NAME(m_drv_sel)); + save_item(NAME(m_mode_sel)); + save_item(NAME(m_rw_sel)); } @@ -327,8 +339,6 @@ void c2040_fdc_t::live_run(attotime limit) cur_live.cell_counter &= 0xf; } - int ready = cur_live.ready; - if (!BIT(cell_counter, 1) && BIT(cur_live.cell_counter, 1)) { // read bit cur_live.shift_reg <<= 1; @@ -343,22 +353,20 @@ void c2040_fdc_t::live_run(attotime limit) write_next_bit(BIT(cur_live.shift_reg_write, 9), limit); } - // update bit counter - if ((cur_live.shift_reg == 0x3ff) && cur_live.rw_sel) { - cur_live.bit_counter = 0; - } else { - cur_live.bit_counter++; - if (cur_live.bit_counter == 10) { - cur_live.bit_counter = 0; - ready = 0; - } else { - ready = 1; - } - } - syncpoint = true; } + int sync = !((cur_live.shift_reg == 0x3ff) && cur_live.rw_sel); + + if (!sync) { + cur_live.bit_counter = 0; + } else if (!BIT(cell_counter, 1) && BIT(cur_live.cell_counter, 1) && cur_live.sync) { + cur_live.bit_counter++; + if (cur_live.bit_counter == 10) { + cur_live.bit_counter = 0; + } + } + // update GCR if (cur_live.rw_sel) { cur_live.i = (cur_live.rw_sel << 10) | cur_live.shift_reg; @@ -368,9 +376,7 @@ void c2040_fdc_t::live_run(attotime limit) cur_live.e = m_gcr_rom->base()[cur_live.i]; - if (BIT(cell_counter, 1) && !BIT(cur_live.cell_counter, 1) && cur_live.bit_counter == 9) { - //ready = 0; - } + int ready = !(BIT(cell_counter, 1) && !BIT(cur_live.cell_counter, 1) && (cur_live.bit_counter == 9)); if (!ready) { // load write shift register @@ -389,8 +395,6 @@ void c2040_fdc_t::live_run(attotime limit) if (LOG) logerror("%s write shift << %03x\n",cur_live.tm.as_string(),cur_live.shift_reg_write); } - // update signals - int sync = !((cur_live.shift_reg == 0x3ff) && cur_live.rw_sel); int error = !(BIT(cur_live.e, 3) || ready); if (ready != cur_live.ready) { diff --git a/src/emu/bus/ieee488/c2040fdc.h b/src/emu/bus/ieee488/c2040fdc.h index bb67ea92657..c72b0fad426 100644 --- a/src/emu/bus/ieee488/c2040fdc.h +++ b/src/emu/bus/ieee488/c2040fdc.h @@ -64,6 +64,7 @@ public: DECLARE_WRITE_LINE_MEMBER( mtr1_w ); DECLARE_WRITE_LINE_MEMBER( odd_hd_w ); DECLARE_WRITE_LINE_MEMBER( pull_sync_w ); + DECLARE_READ_LINE_MEMBER( wps_r ) { return checkpoint_live.drv_sel ? m_floppy1->wpt_r() : m_floppy0->wpt_r(); } DECLARE_READ_LINE_MEMBER( sync_r ) { return checkpoint_live.sync; } DECLARE_READ_LINE_MEMBER( ready_r ) { return checkpoint_live.ready; }