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https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
r4000: tweak address calculation (nw)
This commit is contained in:
Patrick Mackinlay
parent
e0325a8174
commit
e1bed57f7d
@ -78,7 +78,7 @@
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#define ODD_REGS 0x00010840U
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// address computation
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#define ADDR(r, o) (m_64 ? (r + s16(o)) : s64(s32(u32(r) + s16(o))))
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#define ADDR(r, o) (m_64 ? ((r) + (o)) : s64(s32((r) + (o))))
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#define SR m_cp0[CP0_Status]
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#define CAUSE m_cp0[CP0_Cause]
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@ -668,21 +668,21 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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break;
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case 0x01: // BGEZ
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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break;
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case 0x02: // BLTZL
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -691,7 +691,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -730,7 +730,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_r[31] = ADDR(m_pc, 8);
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break;
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@ -738,7 +738,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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m_r[31] = ADDR(m_pc, 8);
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break;
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@ -746,7 +746,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) < 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -756,7 +756,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) >= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -796,28 +796,28 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (m_r[RSREG] == m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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break;
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case 0x05: // BNE
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if (m_r[RSREG] != m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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break;
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case 0x06: // BLEZ
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if (s64(m_r[RSREG]) <= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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break;
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case 0x07: // BGTZ
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if (s64(m_r[RSREG]) > 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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break;
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case 0x08: // ADDI
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@ -866,7 +866,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (m_r[RSREG] == m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -875,7 +875,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (m_r[RSREG] != m_r[RTREG])
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -884,7 +884,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) <= 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -893,7 +893,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (s64(m_r[RSREG]) > 0)
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{
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m_branch_state = BRANCH;
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m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
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m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
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}
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else
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m_branch_state = NULLIFY;
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@ -929,14 +929,14 @@ void r4000_base_device::cpu_execute(u32 const op)
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//case 0x1e: // *
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//case 0x1f: // *
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case 0x20: // LB
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load<s8>(ADDR(m_r[RSREG], op),
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load<s8>(ADDR(m_r[RSREG], s16(op)),
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[this, op](s8 data)
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{
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m_r[RTREG] = data;
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});
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break;
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case 0x21: // LH
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load<s16>(ADDR(m_r[RSREG], op),
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load<s16>(ADDR(m_r[RSREG], s16(op)),
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[this, op](s16 data)
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{
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m_r[RTREG] = data;
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@ -946,21 +946,21 @@ void r4000_base_device::cpu_execute(u32 const op)
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cpu_lwl(op);
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break;
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case 0x23: // LW
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load<s32>(ADDR(m_r[RSREG], op),
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load<s32>(ADDR(m_r[RSREG], s16(op)),
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[this, op](s32 data)
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{
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m_r[RTREG] = data;
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});
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break;
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case 0x24: // LBU
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load<s8>(ADDR(m_r[RSREG], op),
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load<s8>(ADDR(m_r[RSREG], s16(op)),
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[this, op](u8 data)
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{
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m_r[RTREG] = data;
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});
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break;
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case 0x25: // LHU
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load<u16>(ADDR(m_r[RSREG], op),
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load<u16>(ADDR(m_r[RSREG], s16(op)),
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[this, op](u16 data)
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{
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m_r[RTREG] = data;
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@ -970,23 +970,23 @@ void r4000_base_device::cpu_execute(u32 const op)
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cpu_lwr(op);
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break;
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case 0x27: // LWU
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load<u32>(ADDR(m_r[RSREG], op),
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load<u32>(ADDR(m_r[RSREG], s16(op)),
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[this, op](u32 data)
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{
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m_r[RTREG] = data;
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});
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break;
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case 0x28: // SB
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store<u8>(ADDR(m_r[RSREG], op), u8(m_r[RTREG]));
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store<u8>(ADDR(m_r[RSREG], s16(op)), u8(m_r[RTREG]));
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break;
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case 0x29: // SH
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store<u16>(ADDR(m_r[RSREG], op), u16(m_r[RTREG]));
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store<u16>(ADDR(m_r[RSREG], s16(op)), u16(m_r[RTREG]));
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break;
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case 0x2a: // SWL
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cpu_swl(op);
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break;
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case 0x2b: // SW
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store<u32>(ADDR(m_r[RSREG], op), u32(m_r[RTREG]));
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store<u32>(ADDR(m_r[RSREG], s16(op)), u32(m_r[RTREG]));
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break;
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case 0x2c: // SDL
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if (m_64 || !(SR & SR_KSU) || (SR & SR_EXL) || (SR & SR_ERL))
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@ -1015,14 +1015,14 @@ void r4000_base_device::cpu_execute(u32 const op)
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case 0x00: // index invalidate (I)
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if (ICACHE)
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{
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m_icache_tag[(ADDR(m_r[RSREG], op) & m_icache_mask_hi) >> m_icache_shift] &= ~ICACHE_V;
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m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift] &= ~ICACHE_V;
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break;
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}
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case 0x04: // index load tag (I)
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if (ICACHE)
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{
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u32 const tag = m_icache_tag[(ADDR(m_r[RSREG], op) & m_icache_mask_hi) >> m_icache_shift];
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u32 const tag = m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift];
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m_cp0[CP0_TagLo] = ((tag & ICACHE_PTAG) << 8) | ((tag & ICACHE_V) >> 18) | ((tag & ICACHE_P) >> 25);
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m_cp0[CP0_ECC] = 0; // data ecc or parity
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@ -1034,7 +1034,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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if (ICACHE)
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{
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// FIXME: compute parity
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m_icache_tag[(ADDR(m_r[RSREG], op) & m_icache_mask_hi) >> m_icache_shift] =
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m_icache_tag[(ADDR(m_r[RSREG], s16(op)) & m_icache_mask_hi) >> m_icache_shift] =
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(m_cp0[CP0_TagLo] & TAGLO_PTAGLO) >> 8 | (m_cp0[CP0_TagLo] & TAGLO_PSTATE) << 18;
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break;
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@ -1075,7 +1075,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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}
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break;
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case 0x30: // LL
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load_linked<s32>(ADDR(m_r[RSREG], op),
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load_linked<s32>(ADDR(m_r[RSREG], s16(op)),
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[this, op](u64 address, s32 data)
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{
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// remove existing tap
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@ -1106,7 +1106,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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break;
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//case 0x33: // *
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case 0x34: // LLD
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load_linked<u64>(ADDR(m_r[RSREG], op),
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load_linked<u64>(ADDR(m_r[RSREG], s16(op)),
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[this, op](u64 address, u64 data)
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{
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// remove existing tap
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@ -1133,7 +1133,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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cp2_execute(op);
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break;
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case 0x37: // LD
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load<u64>(ADDR(m_r[RSREG], op),
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load<u64>(ADDR(m_r[RSREG], s16(op)),
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[this, op](u64 data)
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{
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m_r[RTREG] = data;
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@ -1145,7 +1145,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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m_ll_watch->remove();
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m_ll_watch = nullptr;
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store<u32>(ADDR(m_r[RSREG], op), u32(m_r[RTREG]));
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store<u32>(ADDR(m_r[RSREG], s16(op)), u32(m_r[RTREG]));
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m_r[RTREG] = 1;
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}
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else
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@ -1164,7 +1164,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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m_ll_watch->remove();
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m_ll_watch = nullptr;
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store<u64>(ADDR(m_r[RSREG], op), m_r[RTREG]);
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store<u64>(ADDR(m_r[RSREG], s16(op)), m_r[RTREG]);
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m_r[RTREG] = 1;
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}
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else
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@ -1177,7 +1177,7 @@ void r4000_base_device::cpu_execute(u32 const op)
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cp2_execute(op);
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break;
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case 0x3f: // SD
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store<u64>(ADDR(m_r[RSREG], op), m_r[RTREG]);
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store<u64>(ADDR(m_r[RSREG], s16(op)), m_r[RTREG]);
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break;
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default:
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@ -1224,7 +1224,7 @@ void r4000_base_device::cpu_exception(u32 exception, u16 const vector)
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void r4000_base_device::cpu_lwl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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unsigned const shift = ((offset & 3) ^ R4000_ENDIAN_LE_BE(3, 0)) << 3;
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load<u32>(offset & ~3,
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@ -1237,7 +1237,7 @@ void r4000_base_device::cpu_lwl(u32 const op)
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void r4000_base_device::cpu_lwr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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unsigned const shift = ((offset & 0x3) ^ R4000_ENDIAN_LE_BE(0, 3)) << 3;
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load<u32>(offset & ~3,
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@ -1250,7 +1250,7 @@ void r4000_base_device::cpu_lwr(u32 const op)
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void r4000_base_device::cpu_swl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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unsigned const shift = ((offset & 3) ^ R4000_ENDIAN_LE_BE(3, 0)) << 3;
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store<u32>(offset & ~3, u32(m_r[RTREG]) >> shift, ~u32(0) >> shift);
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@ -1259,7 +1259,7 @@ void r4000_base_device::cpu_swl(u32 const op)
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void r4000_base_device::cpu_swr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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unsigned const shift = ((offset & 3) ^ R4000_ENDIAN_LE_BE(0, 3)) << 3;
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store<u32>(offset & ~3, u32(m_r[RTREG]) << shift, ~u32(0) << shift);
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@ -1268,7 +1268,7 @@ void r4000_base_device::cpu_swr(u32 const op)
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void r4000_base_device::cpu_ldl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(7, 0)) << 3;
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load<u64>(offset & ~7,
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@ -1281,7 +1281,7 @@ void r4000_base_device::cpu_ldl(u32 const op)
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void r4000_base_device::cpu_ldr(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(0, 7)) << 3;
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load<u64>(offset & ~7,
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@ -1294,7 +1294,7 @@ void r4000_base_device::cpu_ldr(u32 const op)
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void r4000_base_device::cpu_sdl(u32 const op)
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{
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unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
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u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
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u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
|
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unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(7, 0)) << 3;
|
||||
|
||||
store<u64>(offset & ~7, m_r[RTREG] >> shift, ~u64(0) >> shift);
|
||||
@ -1303,7 +1303,7 @@ void r4000_base_device::cpu_sdl(u32 const op)
|
||||
void r4000_base_device::cpu_sdr(u32 const op)
|
||||
{
|
||||
unsigned const reverse = (SR & SR_RE) && ((SR & SR_KSU) == SR_KSU_U) ? 7 : 0;
|
||||
u64 const offset = u64(ADDR(m_r[RSREG], op)) ^ reverse;
|
||||
u64 const offset = u64(ADDR(m_r[RSREG], s16(op))) ^ reverse;
|
||||
unsigned const shift = ((offset & 7) ^ R4000_ENDIAN_LE_BE(0, 7)) << 3;
|
||||
|
||||
store<u64>(offset & ~7, m_r[RTREG] << shift, ~u64(0) << shift);
|
||||
@ -1727,21 +1727,21 @@ void r4000_base_device::cp1_execute(u32 const op)
|
||||
if (!(m_fcr31 & FCR31_C))
|
||||
{
|
||||
m_branch_state = BRANCH;
|
||||
m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
|
||||
m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
|
||||
}
|
||||
break;
|
||||
case 0x01: // BC1T
|
||||
if (m_fcr31 & FCR31_C)
|
||||
{
|
||||
m_branch_state = BRANCH;
|
||||
m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
|
||||
m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
|
||||
}
|
||||
break;
|
||||
case 0x02: // BC1FL
|
||||
if (!(m_fcr31 & FCR31_C))
|
||||
{
|
||||
m_branch_state = BRANCH;
|
||||
m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
|
||||
m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
|
||||
}
|
||||
else
|
||||
m_branch_state = NULLIFY;
|
||||
@ -1750,7 +1750,7 @@ void r4000_base_device::cp1_execute(u32 const op)
|
||||
if (m_fcr31 & FCR31_C)
|
||||
{
|
||||
m_branch_state = BRANCH;
|
||||
m_branch_target = ADDR(m_pc, (s16(op) << 2) + 4);
|
||||
m_branch_target = ADDR(m_pc + 4, s32(s16(op)) << 2);
|
||||
}
|
||||
else
|
||||
m_branch_state = NULLIFY;
|
||||
@ -2377,7 +2377,7 @@ void r4000_base_device::cp1_execute(u32 const op)
|
||||
break;
|
||||
|
||||
case 0x31: // LWC1
|
||||
load<u32>(ADDR(m_r[RSREG], op),
|
||||
load<u32>(ADDR(m_r[RSREG], s16(op)),
|
||||
[this, op](u32 data)
|
||||
{
|
||||
if (SR & SR_FR)
|
||||
@ -2393,7 +2393,7 @@ void r4000_base_device::cp1_execute(u32 const op)
|
||||
break;
|
||||
|
||||
case 0x35: // LDC1
|
||||
load<u64>(ADDR(m_r[RSREG], op),
|
||||
load<u64>(ADDR(m_r[RSREG], s16(op)),
|
||||
[this, op](u64 data)
|
||||
{
|
||||
if ((SR & SR_FR) || !(RTREG & 1))
|
||||
@ -2403,19 +2403,19 @@ void r4000_base_device::cp1_execute(u32 const op)
|
||||
|
||||
case 0x39: // SWC1
|
||||
if (SR & SR_FR)
|
||||
store<u32>(ADDR(m_r[RSREG], op), u32(m_f[RTREG]));
|
||||
store<u32>(ADDR(m_r[RSREG], s16(op)), u32(m_f[RTREG]));
|
||||
else
|
||||
if (RTREG & 1)
|
||||
// store the high half of the even floating point register
|
||||
store<u32>(ADDR(m_r[RSREG], op), u32(m_f[RTREG & ~1] >> 32));
|
||||
store<u32>(ADDR(m_r[RSREG], s16(op)), u32(m_f[RTREG & ~1] >> 32));
|
||||
else
|
||||
// store the low half of the even floating point register
|
||||
store<u32>(ADDR(m_r[RSREG], op), u32(m_f[RTREG & ~1]));
|
||||
store<u32>(ADDR(m_r[RSREG], s16(op)), u32(m_f[RTREG & ~1]));
|
||||
break;
|
||||
|
||||
case 0x3d: // SDC1
|
||||
if ((SR & SR_FR) || !(RTREG & 1))
|
||||
store<u64>(ADDR(m_r[RSREG], op), m_f[RTREG]);
|
||||
store<u64>(ADDR(m_r[RSREG], s16(op)), m_f[RTREG]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
@ -2588,8 +2588,62 @@ r4000_base_device::translate_t r4000_base_device::translate(int intention, u64 &
|
||||
|
||||
bool extended = false;
|
||||
|
||||
if (!(SR & SR_KSU) || (SR & SR_EXL) || (SR & SR_ERL))
|
||||
switch (SR & (SR_KSU | SR_ERL | SR_EXL))
|
||||
{
|
||||
case SR_KSU_U:
|
||||
// user mode
|
||||
if (SR & SR_UX)
|
||||
{
|
||||
// 64-bit user mode
|
||||
if (address & 0xffff'ff00'0000'0000)
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = true; // xuseg
|
||||
}
|
||||
else
|
||||
{
|
||||
// 32-bit user mode
|
||||
if (address & 0xffff'ffff'8000'0000)
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = false; // useg
|
||||
}
|
||||
break;
|
||||
|
||||
case SR_KSU_S:
|
||||
// supervisor mode
|
||||
if (SR & SR_SX)
|
||||
{
|
||||
// 64-bit supervisor mode
|
||||
if (address & 0xffff'ff00'0000'0000)
|
||||
if ((address & 0xffff'ff00'0000'0000) == 0x4000'0000'0000'0000)
|
||||
extended = true; // xsseg
|
||||
else
|
||||
if ((address & 0xffff'ffff'e000'0000) == 0xffff'ffff'c000'0000)
|
||||
extended = true; // csseg
|
||||
else
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = true; // xsuseg
|
||||
}
|
||||
else
|
||||
{
|
||||
// 32-bit supervisor mode
|
||||
if (address & 0xffff'ffff'8000'0000)
|
||||
if ((address & 0xffff'ffff'e000'0000) == 0xffff'ffff'c000'0000)
|
||||
extended = false; // sseg
|
||||
else
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = false; // suseg
|
||||
}
|
||||
break;
|
||||
|
||||
case SR_KSU_U | SR_KSU_S:
|
||||
fatalerror("invalid ksu bits 0x%08x (%s)\n", u32(SR), machine().describe_context().c_str());
|
||||
break;
|
||||
|
||||
default:
|
||||
// kernel mode
|
||||
if (SR & SR_KX)
|
||||
{
|
||||
@ -2646,55 +2700,7 @@ r4000_base_device::translate_t r4000_base_device::translate(int intention, u64 &
|
||||
else
|
||||
extended = false; // kuseg
|
||||
}
|
||||
}
|
||||
else if ((SR & SR_KSU) == SR_KSU_S)
|
||||
{
|
||||
// supervisor mode
|
||||
if (SR & SR_SX)
|
||||
{
|
||||
// 64-bit supervisor mode
|
||||
if (address & 0xffff'ff00'0000'0000)
|
||||
if ((address & 0xffff'ff00'0000'0000) == 0x4000'0000'0000'0000)
|
||||
extended = true; // xsseg
|
||||
else
|
||||
if ((address & 0xffff'ffff'e000'0000) == 0xffff'ffff'c000'0000)
|
||||
extended = true; // csseg
|
||||
else
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = true; // xsuseg
|
||||
}
|
||||
else
|
||||
{
|
||||
// 32-bit supervisor mode
|
||||
if (address & 0xffff'ffff'8000'0000)
|
||||
if ((address & 0xffff'ffff'e000'0000) == 0xffff'ffff'c000'0000)
|
||||
extended = false; // sseg
|
||||
else
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = false; // suseg
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// user mode
|
||||
if (SR & SR_UX)
|
||||
{
|
||||
// 64-bit user mode
|
||||
if (address & 0xffff'ff00'0000'0000)
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = true; // xuseg
|
||||
}
|
||||
else
|
||||
{
|
||||
// 32-bit user mode
|
||||
if (address & 0xffff'ffff'8000'0000)
|
||||
return ERROR; // exception
|
||||
else
|
||||
extended = false; // useg
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
// address needs translation, using a combination of VPN2 and ASID
|
||||
|
||||
Loading…
Reference in New Issue
Block a user