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r9751: Fix race condition in PDC device. Multi disk load now possible.

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This commit is contained in:
Brandon Munger 2016-05-08 15:41:24 -04:00
parent 1243bb8d96
commit e1c13a3f5e
1 changed files with 21 additions and 19 deletions
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40
src/devices/machine/pdc.cpp
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@ -119,8 +119,8 @@ const device_type PDC = &device_creator<pdc_device>;
//-------------------------------------------------
ROM_START( pdc )
ROM_REGION( 0x4000, "rom", 0 )
ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17
ROM_REGION( 0x4000, "rom", 0 )
ROM_LOAD( "97d9988.27128.pdc.u17", 0x0000, 0x4000, CRC(d96ccaa6) SHA1(e1a465c2274a63e81dba7a71fc8b30f10c03baf0) ) // Label: "97D9988" 27128 @U17
ROM_END
//-------------------------------------------------
@ -129,7 +129,7 @@ ROM_END
const rom_entry *pdc_device::device_rom_region() const
{
return ROM_NAME( pdc );
return ROM_NAME( pdc );
}
//-------------------------------------------------
@ -232,10 +232,10 @@ SLOT_INTERFACE_END
//-------------------------------------------------
static SLOT_INTERFACE_START( pdc_harddisks )
SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image)
SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB)
SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB)
SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB)
SLOT_INTERFACE( "generic", MFMHD_GENERIC ) // Generic hard disk (self-adapting to image)
SLOT_INTERFACE( "st213", MFMHD_ST213 ) // Seagate ST-213 (10 MB)
SLOT_INTERFACE( "st225", MFMHD_ST225 ) // Seagate ST-225 (20 MB)
SLOT_INTERFACE( "st251", MFMHD_ST251 ) // Seagate ST-251 (40 MB)
SLOT_INTERFACE_END
//-------------------------------------------------
@ -243,7 +243,7 @@ SLOT_INTERFACE_END
//-------------------------------------------------
FLOPPY_FORMATS_MEMBER( pdc_device::floppy_formats )
FLOPPY_PC_FORMAT
FLOPPY_PC_FORMAT
FLOPPY_FORMATS_END
//-------------------------------------------------
@ -252,8 +252,8 @@ FLOPPY_FORMATS_END
static MACHINE_CONFIG_FRAGMENT( pdc )
/* CPU - Zilog Z0840006PSC */
MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2)
MCFG_CPU_PROGRAM_MAP(pdc_mem)
MCFG_CPU_ADD(Z80_TAG, Z80, XTAL_10MHz / 2)
MCFG_CPU_PROGRAM_MAP(pdc_mem)
MCFG_CPU_IO_MAP(pdc_io)
//MCFG_QUANTUM_PERFECT_CPU(M6502_TAG)
@ -290,7 +290,7 @@ MACHINE_CONFIG_END
machine_config_constructor pdc_device::device_mconfig_additions() const
{
return MACHINE_CONFIG_NAME( pdc );
return MACHINE_CONFIG_NAME( pdc );
}
ioport_constructor pdc_device::device_input_ports() const
@ -308,7 +308,7 @@ ioport_constructor pdc_device::device_input_ports() const
pdc_device::pdc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
device_t(mconfig, PDC, "ROLM PDC", tag, owner, clock, "pdc", __FILE__),
m_pdccpu(*this, Z80_TAG),
m_pdccpu(*this, Z80_TAG),
m_dma8237(*this, FDCDMA_TAG),
m_fdc(*this, FDC_TAG),
m_hdc9224(*this, HDC_TAG),
@ -338,7 +338,7 @@ void pdc_device::device_reset()
//reg_p38 |= 0x20; // no idea at all - bit 5 (32)
/* Reset CPU */
m_pdccpu->reset();
m_pdccpu->reset();
/* Resolve callbacks */
m_m68k_r_cb.resolve_safe(0);
@ -449,6 +449,8 @@ WRITE8_MEMBER(pdc_device::p0_7_w)
case 4: /* Port 4: FDD command completion status low byte [0x5FF030B0] */
if(TRACE_PDC_FDC) logerror("PDC: Port 0x04 WRITE: %02X\n", data);
reg_p4 = data;
if(TRACE_PDC_FDC) logerror("PDC: Resetting 0x38 bit 1. This causes the PDC to stop looking for a command.\n");
reg_p38 &= ~2; // Clear bit 1
break;
case 5: /* Port 5: FDD command completion status high byte [0x5FF030B0] */
if(TRACE_PDC_FDC) logerror("PDC: Port 0x05 WRITE: %02X\n", data);
@ -477,8 +479,8 @@ WRITE8_MEMBER(pdc_device::fdd_68k_w)
{
case 0x21: /* Port 21: ?? */
if(TRACE_PDC_FDC) logerror("PDC: Port 0x21 WRITE: %02X\n", data);
if(TRACE_PDC_FDC) logerror("PDC: Resetting 0x38 bit 1\n");
reg_p38 &= ~2; // Clear bit 1
//if(TRACE_PDC_FDC) logerror("PDC: Resetting 0x38 bit 1\n");
//reg_p38 &= ~2; // Clear bit 1
reg_p21 = data;
break;
case 0x23: /* Port 23: FDD 68k DMA high byte */
@ -547,15 +549,15 @@ WRITE8_MEMBER(pdc_device::p50_5f_w)
switch(data)
{
case 0x00:
if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor off.\n");
if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor off. PC: %X\n", space.device().safe_pc());
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
break;
case 0x80:
if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor on.\n");
if(TRACE_PDC_FDC) logerror("PDC: FDD (all) Motor on. PC: %X\n", space.device().safe_pc());
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(0);
break;
default:
if(TRACE_PDC_FDC) logerror("PDC: Port 0x52 WRITE: %x\n", data);
if(TRACE_PDC_FDC) logerror("PDC: Port 0x52 WRITE: %x\n PC: %X\n", data, space.device().safe_pc());
}
break;
case 0x53: /* Probably set_rate here */
@ -565,7 +567,7 @@ WRITE8_MEMBER(pdc_device::p50_5f_w)
switch(data)
{
case 0x00:
if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor off.\n");
if(TRACE_PDC_FDC) logerror("PDC: FDD 1 Motor off. PC: %X\n", space.device().safe_pc());
m_fdc->subdevice<floppy_connector>("0")->get_device()->mon_w(1);
break;
case 0x80: