mirror of
https://github.com/holub/mame
synced 2025-04-26 18:23:08 +03:00
mc6854: WIP added support for external clocks and DMA
This commit is contained in:
Joakim Larsson Edstrom
parent
e9cb27c22c
commit
e1c7a3b69b
@ -22,7 +22,6 @@
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TODO:
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- CRC
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- DMA mode
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- loop mode
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- status prioritization
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- NRZI vs. NRZ coding
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@ -34,9 +33,20 @@
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#include "emu.h"
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#include "mc6854.h"
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//#define VERBOSE 1
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#define LOG_SETUP (1U << 1)
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#define LOG_BITS (1U << 2)
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//#define VERBOSE (LOG_BITS|LOG_GENERAL | LOG_SETUP)
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//#define LOG_OUTPUT_STREAM std::cout
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#include "logmacro.h"
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#define LOGSETUP(...) LOGMASKED(LOG_SETUP, __VA_ARGS__)
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#define LOGBITS(...) LOGMASKED(LOG_BITS, __VA_ARGS__)
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//#define VERBOSE 1
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//#include "logmacro.h"
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/******************* parameters ******************/
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@ -66,6 +76,9 @@ constexpr unsigned mc6854_device::MAX_FRAME_LENGTH;
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#define RIE ( m_cr1 & 2 ) /* interrupt enable */
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#define TIE ( m_cr1 & 4 )
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#define RDSR ( m_cr1 & 8 ) /* DMA mode */
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#define TDSR ( m_cr1 & 0x10 )
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#define DISCONTINUE ( m_cr1 & 0x20 ) /* discontinue received frame */
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@ -131,6 +144,8 @@ DEFINE_DEVICE_TYPE(MC6854, mc6854_device, "mc6854", "Motorola MC6854 ADLC")
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mc6854_device::mc6854_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, MC6854, tag, owner, clock),
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m_out_irq_cb(*this),
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m_out_rdsr_cb(*this),
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m_out_tdsr_cb(*this),
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m_out_txd_cb(*this),
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m_out_frame_cb(*this),
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m_out_rts_cb(*this),
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@ -150,6 +165,8 @@ mc6854_device::mc6854_device(const machine_config &mconfig, const char *tag, dev
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m_rreg(0),
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m_rones(0),
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m_rsize(0),
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m_rxd(0),
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m_rxc(0),
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m_flen(0),
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m_fpos(0)
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{
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@ -172,6 +189,8 @@ mc6854_device::mc6854_device(const machine_config &mconfig, const char *tag, dev
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void mc6854_device::device_start()
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{
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m_out_irq_cb.resolve_safe();
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m_out_rdsr_cb.resolve_safe();
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m_out_tdsr_cb.resolve_safe();
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m_out_txd_cb.resolve();
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m_out_frame_cb.resolve();
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m_out_rts_cb.resolve_safe();
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@ -391,6 +410,7 @@ TIMER_CALLBACK_MEMBER(mc6854_device::tfifo_cb)
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/* data underrun => abort */
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logerror( "%f mc6854_tfifo_cb: FIFO underrun\n", machine().time().as_double() );
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m_sr1 |= TU;
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update_sr1();
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m_tstate = 0;
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send_bits( 0xffff, ABTEX ? 16 : 8, 0 );
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m_flen = 0;
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@ -514,10 +534,10 @@ void mc6854_device::rfifo_push( uint8_t d )
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}
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m_rsize -= blen;
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update_sr1( );
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}
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void mc6854_device::rfifo_terminate( )
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{
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/* mark most recently pushed byte as the last one of the frame */
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@ -537,7 +557,6 @@ void mc6854_device::rfifo_terminate( )
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}
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/* CPU pops the FIFO */
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uint8_t mc6854_device::rfifo_pop( )
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{
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@ -566,70 +585,9 @@ uint8_t mc6854_device::rfifo_pop( )
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}
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/* MC6854 makes fields from bits */
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WRITE_LINE_MEMBER( mc6854_device::set_rx )
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{
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int fieldlen = ( m_rstate < 6 ) ? 8 : RWL;
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if ( RRESET || (m_sr2 & DCD) )
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return;
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if ( state )
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{
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m_rones++;
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m_rreg = (m_rreg >> 1) | 0x80000000;
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if ( m_rones >= 8 )
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{
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/* abort */
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m_rstate = 0;
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m_rsize = 0;
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if ( m_rstate > 1 )
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{
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/* only in-frame abort */
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m_sr2 |= RABT;
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LOG( "%f mc6854_receive_bit: abort\n", machine().time().as_double() );
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}
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}
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else
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{
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m_rsize++;
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if ( m_rstate && m_rsize >= fieldlen + 24 )
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rfifo_push( m_rreg );
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}
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}
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else if ( m_rones == 5 )
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{
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/* discards '0' inserted after 5 '1' */
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m_rones = 0;
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return;
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}
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else if ( m_rones == 6 )
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{
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/* flag */
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if ( FDSE )
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m_sr1 |= FD;
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if ( m_rstate > 1 )
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{
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/* end of frame */
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m_rreg >>= 1;
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m_rsize++;
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if ( m_rsize >= fieldlen + 24 ) /* last field */
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rfifo_push( m_rreg );
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rfifo_terminate( );
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LOG( "%f mc6854_receive_bit: end of frame\n", machine().time().as_double() );
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}
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m_rones = 0;
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m_rstate = 1;
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m_rsize = 0;
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} else
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{
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m_rones = 0;
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m_rreg >>= 1;
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m_rsize++;
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if ( m_rstate && m_rsize >= fieldlen + 24 )
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rfifo_push( m_rreg );
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}
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m_rxd = state;
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}
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@ -663,7 +621,10 @@ int mc6854_device::send_frame( uint8_t* data, int len )
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}
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memcpy( m_frame, data, len );
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if ( FDSE )
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{
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m_sr1 |= FD;
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update_sr1();
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}
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m_flen = len;
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m_fpos = 0;
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rfifo_push( m_frame[ m_fpos++ ] );
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@ -689,6 +650,7 @@ WRITE_LINE_MEMBER( mc6854_device::set_cts )
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m_sr1 |= CTS;
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else
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m_sr1 &= ~CTS;
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update_sr1();
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}
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@ -737,7 +699,7 @@ void mc6854_device::update_sr1( )
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else
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m_sr1 &= ~S2RQ;
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/* update TRDA (always prioritized by CTS) */
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/* update TDRA (always prioritized by CTS) */
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if ( TRESET || ( m_sr1 & CTS ) )
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m_sr1 &= ~TDRA;
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else
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@ -757,9 +719,9 @@ void mc6854_device::update_sr1( )
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/* update IRQ */
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m_sr1 &= ~IRQ;
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if ( RIE && (m_sr1 & (TU | TDRA) ) )
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if ( TIE && (m_sr1 & (TU | TDRA)) && !TDSR )
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m_sr1 |= IRQ;
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if ( TIE )
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if ( RIE && !RDSR )
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{
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if ( m_sr1 & (S2RQ | RDA | CTS) )
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m_sr1 |= IRQ;
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@ -768,6 +730,8 @@ void mc6854_device::update_sr1( )
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}
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m_out_irq_cb((m_sr1 & IRQ) ? ASSERT_LINE : CLEAR_LINE);
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m_out_rdsr_cb((m_sr1 & RDA) ? ASSERT_LINE : CLEAR_LINE);
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m_out_tdsr_cb((m_sr1 & TDRA) ? ASSERT_LINE : CLEAR_LINE);
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}
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@ -802,6 +766,7 @@ uint8_t mc6854_device::read(offs_t offset)
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uint8_t data = rfifo_pop( );
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LOG( "%f %s mc6854_r: get data $%02X\n",
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machine().time().as_double(), machine().describe_context(), data );
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m_out_rdsr_cb(CLEAR_LINE); // Deactive DMA request line regardless of mode
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return data;
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}
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@ -819,15 +784,13 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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{
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case 0: /* control register 1 */
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m_cr1 = data;
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LOG( "%f %s mc6854_w: set CR1=$%02X (ac=%i,irq=%c%c,%sreset=%c%c)\n",
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LOGSETUP( "%f %s mc6854_w: set CR1=$%02X (ac=%i,irq=%c%c,%sreset=%c%c)\n",
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machine().time().as_double(), machine().describe_context(), m_cr1,
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AC ? 1 : 0,
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RIE ? 'r' : '-', TIE ? 't' : '-',
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DISCONTINUE ? "discontinue," : "",
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RRESET ? 'r' : '-', TRESET ? 't' : '-' );
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if ( m_cr1 & 0xc )
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logerror( "%s mc6854 DMA not handled (CR1=$%02X)\n",
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machine().describe_context(), m_cr1 );
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if ( DISCONTINUE )
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{
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/* abort receive FIFO but keeps shift register & synchro */
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@ -841,12 +804,14 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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m_sr1 &= ~FD;
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m_sr2 &= ~(AP | FV | RIDLE | RABT | ERR | OVRN | DCD);
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if ( m_dcd ) m_sr2 |= DCD;
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update_sr1( );
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}
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if ( TRESET )
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{
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tfifo_clear( );
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m_sr1 &= ~(TU | TDRA | CTS);
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if ( m_cts ) m_sr1 |= CTS;
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update_sr1( );
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}
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break;
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@ -855,7 +820,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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{
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/* control register 3 */
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m_cr3 = data;
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LOG( "%f %s mc6854_w: set CR3=$%02X (lcf=%i,aex=%i,idl=%i,fdse=%i,loop=%i,tst=%i,dtr=%i)\n",
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LOGSETUP( "%f %s mc6854_w: set CR3=$%02X (lcf=%i,aex=%i,idl=%i,fdse=%i,loop=%i,tst=%i,dtr=%i)\n",
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machine().time().as_double(), machine().describe_context(), m_cr3,
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LCF ? (CEX ? 16 : 8) : 0, AEX ? 1 : 0,
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IDL0 ? 0 : 1, FDSE ? 1 : 0, LOOP ? 1 : 0,
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@ -872,7 +837,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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{
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/* control register 2 */
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m_cr2 = data;
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LOG( "%f %s mc6854_w: set CR2=$%02X (pse=%i,bytes=%i,fmidle=%i,%s,tlast=%i,clr=%c%c,rts=%i)\n",
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LOGSETUP( "%f %s mc6854_w: set CR2=$%02X (pse=%i,bytes=%i,fmidle=%i,%s,tlast=%i,clr=%c%c,rts=%i)\n",
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machine().time().as_double(), machine().describe_context(), m_cr2,
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PSE ? 1 : 0, TWOBYTES ? 2 : 1, FMIDLE ? 1 : 0,
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FCTDRA ? "fc" : "tdra", TLAST ? 1 : 0,
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@ -889,6 +854,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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m_sr2 &= ~(AP | FV | RIDLE | RABT | ERR | OVRN | DCD);
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if ( m_dcd )
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m_sr2 |= DCD;
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update_sr1( );
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}
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if ( data & 0x40 )
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{
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@ -896,6 +862,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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m_sr1 &= ~(TU | TDRA | CTS);
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if ( m_cts )
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m_sr1 |= CTS;
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update_sr1( );
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}
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m_out_rts_cb( RTS ? 1 : 0 );
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@ -903,7 +870,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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break;
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case 2: /* transmitter data: continue data */
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LOG( "%f %smc6854_w: push data=$%02X\n", machine().time().as_double(), machine().describe_context(), data );
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LOGSETUP( "%f %smc6854_w: push data=$%02X\n", machine().time().as_double(), machine().describe_context(), data );
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tfifo_push( data );
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break;
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@ -912,7 +879,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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{
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/* control register 4 */
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m_cr4 = data;
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LOG( "%f %s mc6854_w: set CR4=$%02X (interframe=%i,tlen=%i,rlen=%i,%s%s)\n", machine().time().as_double(), machine().describe_context(), m_cr4,
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LOGSETUP( "%f %s mc6854_w: set CR4=$%02X (interframe=%i,tlen=%i,rlen=%i,%s%s)\n", machine().time().as_double(), machine().describe_context(), m_cr4,
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TWOINTER ? 2 : 1,
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TWL, RWL,
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ABT ? ( ABTEX ? "abort-ext," : "abort,") : "",
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@ -927,7 +894,7 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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else
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{
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/* transmitter data: last data */
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LOG( "%f %s mc6854_w: push last-data=$%02X\n", machine().time().as_double(), machine().describe_context(), data );
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LOGSETUP( "%f %s mc6854_w: push last-data=$%02X\n", machine().time().as_double(), machine().describe_context(), data );
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tfifo_push( data );
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tfifo_terminate( );
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}
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@ -938,9 +905,82 @@ void mc6854_device::write(offs_t offset, uint8_t data)
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}
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}
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inline bool mc6854_device::receive_allowed() const
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{
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return (!RRESET && !(m_sr2 & DCD));
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}
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/* MC6854 makes fields from bits */
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WRITE_LINE_MEMBER( mc6854_device::rxc_w )
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{
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// TODO
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if (receive_allowed() && state && !m_rxc)
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{
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int fieldlen = ( m_rstate < 6 ) ? 8 : RWL;
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if ( m_rxd )
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{
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LOGBITS("I ");
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m_rones++;
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m_rreg = (m_rreg >> 1) | 0x80000000;
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if ( m_rones >= 8 )
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{
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/* abort */
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m_rstate = 0;
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m_rsize = 0;
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if ( m_rstate > 1 )
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{
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/* only in-frame abort */
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m_sr2 |= RABT;
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LOG( "%f mc6854_receive_bit: abort\n", machine().time().as_double() );
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}
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}
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else
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{
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m_rsize++;
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if ( m_rstate && m_rsize >= fieldlen + 24 )
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rfifo_push( m_rreg );
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}
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}
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else if ( m_rones == 5 )
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{
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/* discards '0' inserted after 5 '1' */
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LOGBITS("A zero is discarded\n");
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m_rones = 0;
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return;
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}
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else if ( m_rones == 6 )
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{
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/* flag */
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if ( FDSE )
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{
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m_sr1 |= FD;
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update_sr1( );
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}
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if ( m_rstate > 1 )
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{
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/* end of frame */
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m_rreg >>= 1;
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m_rsize++;
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if ( m_rsize >= fieldlen + 24 ) /* last field */
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rfifo_push( m_rreg );
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rfifo_terminate( );
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LOG( "%f mc6854_receive_bit: end of frame\n", machine().time().as_double() );
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}
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m_rones = 0;
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m_rstate = 1;
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m_rsize = 0;
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} else
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{
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LOGBITS("O ");
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m_rones = 0;
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m_rreg >>= 1;
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m_rsize++;
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if ( m_rstate && m_rsize >= fieldlen + 24 )
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rfifo_push( m_rreg );
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}
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}
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m_rxc = state;
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}
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WRITE_LINE_MEMBER( mc6854_device::txc_w )
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@ -23,16 +23,19 @@ public:
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mc6854_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
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auto out_irq_cb() { return m_out_irq_cb.bind(); }
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auto out_txd_cb() { return m_out_txd_cb.bind(); }
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auto out_rts_cb() { return m_out_rts_cb.bind(); }
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auto out_dtr_cb() { return m_out_dtr_cb.bind(); }
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auto out_irq_cb() { return m_out_irq_cb.bind(); }
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auto out_rdsr_cb() { return m_out_rdsr_cb.bind(); }
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auto out_tdsr_cb() { return m_out_tdsr_cb.bind(); }
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auto out_txd_cb() { return m_out_txd_cb.bind(); }
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auto out_rts_cb() { return m_out_rts_cb.bind(); }
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auto out_dtr_cb() { return m_out_dtr_cb.bind(); }
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template <typename... T> void set_out_frame_callback(T &&... args) { m_out_frame_cb.set(std::forward<T>(args)...); }
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/* interface to CPU via address/data bus*/
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uint8_t read(offs_t offset);
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void write(offs_t offset, uint8_t data);
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uint8_t dma_r(){ return read(2); }
|
||||
|
||||
/* low-level, bit-based interface */
|
||||
DECLARE_WRITE_LINE_MEMBER( set_rx );
|
||||
@ -52,12 +55,15 @@ protected:
|
||||
// device-level overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
bool receive_allowed() const;
|
||||
|
||||
private:
|
||||
static constexpr unsigned FIFO_SIZE = 3; // hardcoded size of the 6854 FIFO (this is a hardware limit)
|
||||
|
||||
// internal state
|
||||
devcb_write_line m_out_irq_cb; /* interrupt request */
|
||||
devcb_write_line m_out_rdsr_cb; /* Rx fifo DMA request */
|
||||
devcb_write_line m_out_tdsr_cb; /* Tx fifo DMA request */
|
||||
|
||||
/* low-level, bit-based interface */
|
||||
devcb_write_line m_out_txd_cb; /* transmit bit */
|
||||
@ -87,6 +93,8 @@ private:
|
||||
uint8_t m_rones; /* count '1 bits */
|
||||
uint8_t m_rsize; /* bits in the shift register */
|
||||
uint16_t m_rfifo[FIFO_SIZE]; /* X x 8-bit FIFO + full & addr marker bits */
|
||||
bool m_rxd;
|
||||
bool m_rxc;
|
||||
|
||||
/* frame-based interface*/
|
||||
uint8_t m_frame[MAX_FRAME_LENGTH];
|
||||
@ -132,6 +140,7 @@ DECLARE_DEVICE_TYPE(MC6854, mc6854_device)
|
||||
The frame-based interface is higher-level and faster.
|
||||
It passes bytes directly from one end to the other without bothering with
|
||||
the actual bit-encoding, synchronization, and CRC.
|
||||
|
||||
Once completed, a frame is sent through out_frame. Aborted frames are not
|
||||
transmitted at all. No start flag, stop flag, or crc bits are transmitted.
|
||||
send_frame makes a frame available to the CPU through the 6854 (it may
|
||||
|
||||
Loading…
Reference in New Issue
Block a user