diff --git a/hash/dc.xml b/hash/dc.xml
index c0f900bd82c..5ab072ec93e 100644
--- a/hash/dc.xml
+++ b/hash/dc.xml
@@ -23,8 +23,8 @@ http://segaretro.org/
@@ -260,152 +260,152 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -420,14 +420,14 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -567,15 +567,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -941,16 +941,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -1106,17 +1106,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -1165,15 +1165,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -1224,15 +1224,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -1428,28 +1428,28 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -1475,15 +1475,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -1495,157 +1495,157 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -1834,37 +1834,37 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -1913,23 +1913,23 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -2066,15 +2066,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -2146,46 +2146,46 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -2613,22 +2613,22 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -2790,37 +2790,37 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -2865,56 +2865,56 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -3037,31 +3037,31 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -3312,24 +3312,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -3355,16 +3355,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -3476,16 +3476,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -3826,16 +3826,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -3961,16 +3961,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4017,17 +4017,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4166,16 +4166,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4187,15 +4187,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -4255,14 +4255,14 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4364,16 +4364,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4502,59 +4502,59 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4582,24 +4582,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4754,14 +4754,14 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4789,17 +4789,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -4861,32 +4861,32 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -5101,32 +5101,32 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -5257,15 +5257,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -5377,15 +5377,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -5478,31 +5478,31 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -5638,15 +5638,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -5713,16 +5713,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -5901,32 +5901,32 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -6159,24 +6159,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -6507,130 +6507,130 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -6744,44 +6744,44 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -6846,17 +6846,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7251,16 +7251,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7331,16 +7331,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7386,16 +7386,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7463,16 +7463,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7580,16 +7580,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7794,15 +7794,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -7984,16 +7984,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -8042,165 +8042,165 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -8911,16 +8911,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9389,32 +9389,32 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9462,46 +9462,46 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9549,16 +9549,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9665,32 +9665,32 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9737,17 +9737,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9772,121 +9772,121 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -9912,15 +9912,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10199,15 +10199,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10255,15 +10255,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10311,15 +10311,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10332,15 +10332,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -10408,75 +10408,75 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10546,30 +10546,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10595,44 +10595,44 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10726,133 +10726,133 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10939,16 +10939,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -10960,15 +10960,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -11073,15 +11073,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -11377,23 +11377,23 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -11668,15 +11668,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -11838,24 +11838,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -11948,16 +11948,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12195,17 +12195,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12256,16 +12256,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12420,15 +12420,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12556,16 +12556,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12695,16 +12695,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12716,15 +12716,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -12768,38 +12768,38 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12849,15 +12849,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -12870,15 +12870,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -12999,15 +12999,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -13344,30 +13344,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -13408,15 +13408,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -13546,30 +13546,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -13596,15 +13596,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -13872,125 +13872,125 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14043,28 +14043,28 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14076,15 +14076,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -14350,85 +14350,85 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14440,14 +14440,14 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -14516,16 +14516,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14805,16 +14805,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14884,17 +14884,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14939,17 +14939,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -14975,16 +14975,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -15050,29 +15050,29 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -15197,15 +15197,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -15318,33 +15318,33 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -15412,24 +15412,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -15672,16 +15672,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -15692,23 +15692,23 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -15760,15 +15760,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -15794,32 +15794,32 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -15940,16 +15940,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16059,15 +16059,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -16161,31 +16161,31 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16234,17 +16234,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16271,15 +16271,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16328,17 +16328,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16503,15 +16503,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16657,24 +16657,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16740,33 +16740,33 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -16964,30 +16964,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17015,17 +17015,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17054,53 +17054,53 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17128,17 +17128,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17328,15 +17328,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -17489,46 +17489,46 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17729,30 +17729,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17777,15 +17777,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -17857,15 +17857,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -18198,16 +18198,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18269,29 +18269,29 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18418,17 +18418,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18455,17 +18455,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18524,16 +18524,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18583,17 +18583,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18618,15 +18618,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18658,85 +18658,85 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18897,73 +18897,73 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -18990,15 +18990,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19141,16 +19141,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19223,16 +19223,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19259,16 +19259,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19367,30 +19367,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
-->
@@ -19416,41 +19416,41 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19533,39 +19533,39 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19647,17 +19647,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19681,17 +19681,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19757,16 +19757,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -19831,16 +19831,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20076,17 +20076,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20138,24 +20138,24 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20182,34 +20182,34 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20235,30 +20235,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20351,17 +20351,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20457,17 +20457,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20497,17 +20497,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20674,30 +20674,30 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -20762,16 +20762,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21004,15 +21004,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21109,35 +21109,35 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21234,17 +21234,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21369,15 +21369,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21484,56 +21484,56 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21580,17 +21580,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21683,15 +21683,15 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21762,16 +21762,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21821,16 +21821,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -21943,109 +21943,109 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -22174,17 +22174,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -22250,17 +22250,17 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -22486,16 +22486,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -22570,16 +22570,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -22884,16 +22884,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -23322,97 +23322,97 @@ P830-****-** : Appears to be a Sega part number for promo discs.
@@ -23438,16 +23438,16 @@ P830-****-** : Appears to be a Sega part number for promo discs.
diff --git a/hash/gameboy.xml b/hash/gameboy.xml
index a6ec614ed8b..e294b44267f 100644
--- a/hash/gameboy.xml
+++ b/hash/gameboy.xml
@@ -25073,7 +25073,7 @@
Sachen
-
+
diff --git a/hash/pc98.xml b/hash/pc98.xml
index 7afe456f1b1..9569ac4e042 100644
--- a/hash/pc98.xml
+++ b/hash/pc98.xml
@@ -2312,9 +2312,9 @@ only have some part of Windows file and a Video driver(CLGD?).
-
5 Jikanme no Venus
@@ -3291,7 +3291,7 @@ only have some part of Windows file and a Video driver(CLGD?).
-
+
Air Combat - Yuugeki Ou II
1989
@@ -3650,11 +3650,11 @@ only have some part of Windows file and a Video driver(CLGD?).
-
@@ -4118,11 +4118,11 @@ only have some part of Windows file and a Video driver(CLGD?).
-
@@ -4162,9 +4162,9 @@ only have some part of Windows file and a Video driver(CLGD?).
-
Amaranth - Phantasie RPG
@@ -4430,9 +4430,9 @@ only have some part of Windows file and a Video driver(CLGD?).
-
diff --git a/hash/uzebox.xml b/hash/uzebox.xml
index e45399fa97e..2a74e9870ae 100644
--- a/hash/uzebox.xml
+++ b/hash/uzebox.xml
@@ -1120,7 +1120,7 @@
-
+
Fireman Rescue
2013
@@ -1132,7 +1132,7 @@
-
+
Flight of a Dragon
2017
@@ -1169,7 +1169,7 @@
-
+
Pipes
2012
@@ -1181,7 +1181,7 @@
-
+
Stormforce
2016
@@ -1194,7 +1194,7 @@
-
+
Air Hockey
2013
diff --git a/src/devices/bus/ti99/peb/evpc.cpp b/src/devices/bus/ti99/peb/evpc.cpp
index 254b1d08a27..fc5591112d5 100644
--- a/src/devices/bus/ti99/peb/evpc.cpp
+++ b/src/devices/bus/ti99/peb/evpc.cpp
@@ -490,12 +490,12 @@ void snug_enhanced_video_device::device_add_mconfig(machine_config& config)
m_video->int_cb().set(FUNC(snug_enhanced_video_device::video_interrupt_in));
m_video->set_screen(TI_SCREEN_TAG);
screen_device& screen(SCREEN(config, TI_SCREEN_TAG, SCREEN_TYPE_RASTER));
- screen.set_raw(XTAL(21'477'272), \
- v99x8_device::HTOTAL, \
- 0, \
- v99x8_device::HVISIBLE - 1, \
- v99x8_device::VTOTAL_NTSC * 2, \
- v99x8_device::VERTICAL_ADJUST * 2, \
+ screen.set_raw(XTAL(21'477'272),
+ v99x8_device::HTOTAL,
+ 0,
+ v99x8_device::HVISIBLE - 1,
+ v99x8_device::VTOTAL_NTSC * 2,
+ v99x8_device::VERTICAL_ADJUST * 2,
v99x8_device::VVISIBLE_NTSC * 2 - 1 - v99x8_device::VERTICAL_ADJUST * 2);
screen.set_screen_update(TI_VDP_TAG, FUNC(v99x8_device::screen_update));
diff --git a/src/devices/cpu/st62xx/st62xx.cpp b/src/devices/cpu/st62xx/st62xx.cpp
index 6848844b918..6aa7b94be84 100644
--- a/src/devices/cpu/st62xx/st62xx.cpp
+++ b/src/devices/cpu/st62xx/st62xx.cpp
@@ -4,10 +4,10 @@
STmicro ST6-series microcontroller emulation skeleton
- To Do:
- - Cycle counts
- - STOP, WAIT opcodes
- - Peripherals
+ To Do:
+ - Cycle counts
+ - STOP, WAIT opcodes
+ - Peripherals
**********************************************************************/
@@ -510,7 +510,7 @@ void st6228_device::execute_run()
case 0x00: case 0x10: case 0x20: case 0x30: case 0x40: case 0x50: case 0x60: case 0x70:
case 0x80: case 0xa0: case 0xb0: case 0xc0: case 0xd0: case 0xe0: case 0xf0:
case 0x08: case 0x18: case 0x28: case 0x38: case 0x48: case 0x58: case 0x68: case 0x78:
- case 0x88: case 0xa8: case 0xb8: case 0xc8: case 0xd8: case 0xe8: case 0xf8: // JRNZ e
+ case 0x88: case 0xa8: case 0xb8: case 0xc8: case 0xd8: case 0xe8: case 0xf8: // JRNZ e
{
const int8_t e = ((int8_t)op) >> 3;
if (!(m_flags[m_mode] & FLAG_Z))
@@ -538,7 +538,7 @@ void st6228_device::execute_run()
break;
}
case 0x09: case 0x19: case 0x29: case 0x39: case 0x49: case 0x59: case 0x69: case 0x79:
- case 0x89: case 0x99: case 0xa9: case 0xb9: case 0xc9: case 0xd9: case 0xe9: case 0xf9: // JP abc
+ case 0x89: case 0x99: case 0xa9: case 0xb9: case 0xc9: case 0xd9: case 0xe9: case 0xf9: // JP abc
{
const uint8_t ab = m_program->read_byte(m_pc+1);
const uint16_t abc = ((op & 0xf0) >> 4) | (ab << 4);
@@ -548,14 +548,14 @@ void st6228_device::execute_run()
case 0x02: case 0x12: case 0x22: case 0x32: case 0x42: case 0x52: case 0x62: case 0x72:
case 0x82: case 0x92: case 0xa2: case 0xb2: case 0xc2: case 0xd2: case 0xe2: case 0xf2:
case 0x0a: case 0x1a: case 0x2a: case 0x3a: case 0x4a: case 0x5a: case 0x6a: case 0x7a:
- case 0x8a: case 0x9a: case 0xaa: case 0xba: case 0xca: case 0xda: case 0xea: case 0xfa: // JRNC abc
+ case 0x8a: case 0x9a: case 0xaa: case 0xba: case 0xca: case 0xda: case 0xea: case 0xfa: // JRNC abc
{
const int8_t e = ((int8_t)op) >> 3;
if (!(m_flags[m_mode] & FLAG_C))
m_pc += e;
break;
}
- case 0x03: case 0x23: case 0x43: case 0x63: case 0x83: case 0xa3: case 0xc3: case 0xe3: // JRR b,rr,ee
+ case 0x03: case 0x23: case 0x43: case 0x63: case 0x83: case 0xa3: case 0xc3: case 0xe3: // JRR b,rr,ee
{
const uint8_t b = (op >> 5) & 7;
const uint8_t rr = m_program->read_byte(m_pc+1);
@@ -567,7 +567,7 @@ void st6228_device::execute_run()
m_pc += ee;
break;
}
- case 0x13: case 0x33: case 0x53: case 0x73: case 0x93: case 0xb3: case 0xd3: case 0xf3: // JRS b,rr,ee
+ case 0x13: case 0x33: case 0x53: case 0x73: case 0x93: case 0xb3: case 0xd3: case 0xf3: // JRS b,rr,ee
{
const uint8_t b = (op >> 5) & 7;
const uint8_t rr = m_program->read_byte(m_pc+1);
@@ -579,7 +579,7 @@ void st6228_device::execute_run()
m_pc += 2;
break;
}
- case 0x0b: case 0x2b: case 0x4b: case 0x6b: case 0x8b: case 0xab: case 0xcb: case 0xeb: // RES b,rr
+ case 0x0b: case 0x2b: case 0x4b: case 0x6b: case 0x8b: case 0xab: case 0xcb: case 0xeb: // RES b,rr
{
const uint8_t b = (op >> 5) & 7;
const uint8_t rr = m_program->read_byte(m_pc+1);
@@ -588,7 +588,7 @@ void st6228_device::execute_run()
m_pc++;
break;
}
- case 0x1b: case 0x3b: case 0x5b: case 0x7b: case 0x9b: case 0xbb: case 0xdb: case 0xfb: // SET b,rr
+ case 0x1b: case 0x3b: case 0x5b: case 0x7b: case 0x9b: case 0xbb: case 0xdb: case 0xfb: // SET b,rr
{
const uint8_t b = (op >> 5) & 7;
const uint8_t rr = m_program->read_byte(m_pc+1);
@@ -600,7 +600,7 @@ void st6228_device::execute_run()
case 0x04: case 0x14: case 0x24: case 0x34: case 0x44: case 0x54: case 0x64: case 0x74:
case 0x84: case 0x94: case 0xa4: case 0xb4: case 0xc4: case 0xd4: case 0xe4: case 0xf4:
case 0x0c: case 0x1c: case 0x2c: case 0x3c: case 0x4c: case 0x5c: case 0x6c: case 0x7c:
- case 0x8c: case 0x9c: case 0xac: case 0xbc: case 0xcc: case 0xdc: case 0xec: case 0xfc: // JRZ e
+ case 0x8c: case 0x9c: case 0xac: case 0xbc: case 0xcc: case 0xdc: case 0xec: case 0xfc: // JRZ e
{
const int8_t e = ((int8_t)op) >> 3;
if (m_flags[m_mode] & FLAG_Z)
@@ -610,7 +610,7 @@ void st6228_device::execute_run()
case 0x06: case 0x16: case 0x26: case 0x36: case 0x46: case 0x56: case 0x66: case 0x76:
case 0x86: case 0x96: case 0xa6: case 0xb6: case 0xc6: case 0xd6: case 0xe6: case 0xf6:
case 0x0e: case 0x1e: case 0x2e: case 0x3e: case 0x4e: case 0x5e: case 0x6e: case 0x7e:
- case 0x8e: case 0x9e: case 0xae: case 0xbe: case 0xce: case 0xde: case 0xee: case 0xfe: // JRC e
+ case 0x8e: case 0x9e: case 0xae: case 0xbe: case 0xce: case 0xde: case 0xee: case 0xfe: // JRC e
{
const int8_t e = ((int8_t)op) >> 3;
if (m_flags[m_mode] & FLAG_C)
@@ -681,7 +681,7 @@ void st6228_device::execute_run()
else
m_flags[m_mode] |= FLAG_Z;
break;
- case 0x0d: // LDI rr,nn
+ case 0x0d: // LDI rr,nn
{
const uint8_t rr = m_program->read_byte(m_pc+1);
const uint8_t nn = m_program->read_byte(m_pc+2);
@@ -824,7 +824,7 @@ void st6228_device::execute_run()
else
m_flags[m_mode] |= FLAG_Z;
break;
- case 0x17: // LDI A,rr
+ case 0x17: // LDI A,rr
{
m_regs[REG_A] = m_program->read_byte(m_pc+1);
diff --git a/src/devices/cpu/st62xx/st62xx.h b/src/devices/cpu/st62xx/st62xx.h
index 8eae2774df0..f0748c44c95 100644
--- a/src/devices/cpu/st62xx/st62xx.h
+++ b/src/devices/cpu/st62xx/st62xx.h
@@ -136,47 +136,47 @@ protected:
enum
{
- PROGRAM_ROM_START = 0x40,
- REGS_START = 0x80,
- REG_X = 0x80,
- REG_Y = 0x81,
- REG_V = 0x82,
- REG_W = 0x83,
- DATA_RAM_START = 0x84,
- REG_PORTA_DATA = 0xc0,
- REG_PORTB_DATA = 0xc1,
- REG_PORTC_DATA = 0xc2,
- REG_PORTD_DATA = 0xc3,
- REG_PORTA_DIR = 0xc4,
- REG_PORTB_DIR = 0xc5,
- REG_PORTC_DIR = 0xc6,
- REG_PORTD_DIR = 0xc7,
- REG_INT_OPTION = 0xc8,
- REG_DATA_ROM_WINDOW = 0xc9,
- REG_ROM_BANK_SELECT = 0xca,
- REG_RAM_BANK_SELECT = 0xcb,
- REG_PORTA_OPTION = 0xcc,
- REG_PORTB_OPTION = 0xcd,
- REG_PORTC_OPTION = 0xce,
- REG_PORTD_OPTION = 0xcf,
- REG_AD_DATA = 0xd0,
- REG_AD_CONTROL = 0xd1,
- REG_TIMER_PRESCALE = 0xd2,
- REG_TIMER_COUNT = 0xd3,
- REG_TIMER_CONTROL = 0xd4,
- REG_UART_DATA = 0xd6,
- REG_UART_CONTROL = 0xd7,
- REG_WATCHDOG = 0xd8,
- REG_INT_POLARITY = 0xda,
- REG_SPI_INT_DISABLE = 0xdc,
- REG_SPI_DATA = 0xdd,
- REG_ARTIMER_MODE = 0xe5,
- REG_ARTIMER_ARCS0 = 0xe6,
- REG_ARTIMER_ARCS1 = 0xe7,
- REG_ARTIMER_RELOAD = 0xe9,
- REG_ARTIMER_COMPARE = 0xea,
- REG_ARTIMER_LOAD = 0xeb,
- REG_A = 0xff
+ PROGRAM_ROM_START = 0x40,
+ REGS_START = 0x80,
+ REG_X = 0x80,
+ REG_Y = 0x81,
+ REG_V = 0x82,
+ REG_W = 0x83,
+ DATA_RAM_START = 0x84,
+ REG_PORTA_DATA = 0xc0,
+ REG_PORTB_DATA = 0xc1,
+ REG_PORTC_DATA = 0xc2,
+ REG_PORTD_DATA = 0xc3,
+ REG_PORTA_DIR = 0xc4,
+ REG_PORTB_DIR = 0xc5,
+ REG_PORTC_DIR = 0xc6,
+ REG_PORTD_DIR = 0xc7,
+ REG_INT_OPTION = 0xc8,
+ REG_DATA_ROM_WINDOW = 0xc9,
+ REG_ROM_BANK_SELECT = 0xca,
+ REG_RAM_BANK_SELECT = 0xcb,
+ REG_PORTA_OPTION = 0xcc,
+ REG_PORTB_OPTION = 0xcd,
+ REG_PORTC_OPTION = 0xce,
+ REG_PORTD_OPTION = 0xcf,
+ REG_AD_DATA = 0xd0,
+ REG_AD_CONTROL = 0xd1,
+ REG_TIMER_PRESCALE = 0xd2,
+ REG_TIMER_COUNT = 0xd3,
+ REG_TIMER_CONTROL = 0xd4,
+ REG_UART_DATA = 0xd6,
+ REG_UART_CONTROL = 0xd7,
+ REG_WATCHDOG = 0xd8,
+ REG_INT_POLARITY = 0xda,
+ REG_SPI_INT_DISABLE = 0xdc,
+ REG_SPI_DATA = 0xdd,
+ REG_ARTIMER_MODE = 0xe5,
+ REG_ARTIMER_ARCS0 = 0xe6,
+ REG_ARTIMER_ARCS1 = 0xe7,
+ REG_ARTIMER_RELOAD = 0xe9,
+ REG_ARTIMER_COMPARE = 0xea,
+ REG_ARTIMER_LOAD = 0xeb,
+ REG_A = 0xff
};
enum
@@ -198,8 +198,8 @@ protected:
enum
{
- FLAG_C = 0x01,
- FLAG_Z = 0x02
+ FLAG_C = 0x01,
+ FLAG_Z = 0x02
};
enum
@@ -252,4 +252,4 @@ protected:
DECLARE_DEVICE_TYPE(ST6228, st6228_device)
-#endif // MAME_CPU_ST62XX_H
\ No newline at end of file
+#endif // MAME_CPU_ST62XX_H
diff --git a/src/devices/cpu/st62xx/st62xx_dasm.cpp b/src/devices/cpu/st62xx/st62xx_dasm.cpp
index 0f3c9b4c999..7328cc32a7c 100644
--- a/src/devices/cpu/st62xx/st62xx_dasm.cpp
+++ b/src/devices/cpu/st62xx/st62xx_dasm.cpp
@@ -4,8 +4,8 @@
STmicro ST6-series microcontroller disassembler
- To Do:
- - Named registers/bits
+ To Do:
+ - Named registers/bits
**********************************************************************/
diff --git a/src/devices/cpu/tlcs870/tlcs870.cpp b/src/devices/cpu/tlcs870/tlcs870.cpp
index 79af9af88b4..c29db26f769 100644
--- a/src/devices/cpu/tlcs870/tlcs870.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870.cpp
@@ -94,7 +94,7 @@ void tlcs870_device::tmp87ph40an_mem(address_map &map)
map(0x003c, 0x003c).rw(FUNC(tlcs870_device::il_l_r), FUNC(tlcs870_device::il_l_w)); // Interrupt latch
map(0x003d, 0x003d).rw(FUNC(tlcs870_device::il_h_r), FUNC(tlcs870_device::il_h_w)); //
-
+
// 0x3e reserved
map(0x003f, 0x003f).rw(FUNC(tlcs870_device::psw_r), FUNC(tlcs870_device::rbs_w)); // Program status word / Register bank selector
@@ -296,9 +296,9 @@ WRITE8_MEMBER(tlcs870_device::tc1cr_w)
LOG("%d: SCAP1/MCAP1/METT1/MPPG1\n", (m_TC1CR & 0x40) ? 1 : 0);
LOG("%d: TC1S-1 (TC1 Start Control)\n", (m_TC1CR & 0x20) ? 1 : 0);
LOG("%d: TC1S-0 (TC1 Start Control)\n", (m_TC1CR & 0x10) ? 1 : 0);
- LOG("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0);
- LOG("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0);
- LOG("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0);
+ LOG("%d: TC1CK-1 (TC1 Source Clock select)\n", (m_TC1CR & 0x08) ? 1 : 0);
+ LOG("%d: TC1CK-0 (TC1 Source Clock select)\n", (m_TC1CR & 0x04) ? 1 : 0);
+ LOG("%d: TC1M-1 (TC1 Mode Select)\n", (m_TC1CR & 0x02) ? 1 : 0);
LOG("%d: TC1M-0 (TC1 Mode Select)\n", (m_TC1CR & 0x01) ? 1 : 0);
}
@@ -371,9 +371,9 @@ WRITE8_MEMBER(tlcs870_device::tc2cr_w)
LOG("%d: (invalid)\n", (m_TC2CR & 0x40) ? 1 : 0);
LOG("%d: TC2S (TC2 Start Control)\n", (m_TC2CR & 0x20) ? 1 : 0);
LOG("%d: TC2CK-2 (TC2 Source Clock select)\n", (m_TC2CR & 0x10) ? 1 : 0);
- LOG("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0);
- LOG("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0);
- LOG("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0);
+ LOG("%d: TC2CK-1 (TC2 Source Clock select)\n", (m_TC2CR & 0x08) ? 1 : 0);
+ LOG("%d: TC2CK-0 (TC2 Source Clock select)\n", (m_TC2CR & 0x04) ? 1 : 0);
+ LOG("%d: (invalid)\n", (m_TC2CR & 0x02) ? 1 : 0);
LOG("%d: TC2M (TC2 Mode Select)\n", (m_TC2CR & 0x01) ? 1 : 0);
}
@@ -403,9 +403,9 @@ WRITE8_MEMBER(tlcs870_device::tc3cr_w)
LOG("%d: SCAP (Software Capture Control)\n", (m_TC3CR & 0x40) ? 1 : 0);
LOG("%d: (invalid)\n", (m_TC3CR & 0x20) ? 1 : 0);
LOG("%d: TC3S (TC3 Start Control)\n", (m_TC3CR & 0x10) ? 1 : 0);
- LOG("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0);
- LOG("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0);
- LOG("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0);
+ LOG("%d: TC3CK-1 (TC3 Source Clock select)\n", (m_TC3CR & 0x08) ? 1 : 0);
+ LOG("%d: TC3CK-0 (TC3 Source Clock select)\n", (m_TC3CR & 0x04) ? 1 : 0);
+ LOG("%d: (invalid)\n", (m_TC3CR & 0x02) ? 1 : 0);
LOG("%d: TC3M (TC3 Mode Select)\n", (m_TC3CR & 0x01) ? 1 : 0);
}
@@ -440,9 +440,9 @@ WRITE8_MEMBER(tlcs870_device::tc4cr_w)
LOG("%d: TFF4-0 (Timer F/F 4 Control)\n", (m_TC4CR & 0x40) ? 1 : 0);
LOG("%d: (invalid)\n", (m_TC4CR & 0x20) ? 1 : 0);
LOG("%d: TC4S (TC4 Start Control)\n", (m_TC4CR & 0x10) ? 1 : 0);
- LOG("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0);
- LOG("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0);
- LOG("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0);
+ LOG("%d: TC4CK-1 (TC4 Source Clock select)\n", (m_TC4CR & 0x08) ? 1 : 0);
+ LOG("%d: TC4CK-0 (TC4 Source Clock select)\n", (m_TC4CR & 0x04) ? 1 : 0);
+ LOG("%d: TC4M-1 (TC4 Mode Select)\n", (m_TC4CR & 0x02) ? 1 : 0);
LOG("%d: TC4M-0 (TC4 Mode Select)\n", (m_TC4CR & 0x01) ? 1 : 0);
}
@@ -453,7 +453,7 @@ WRITE8_MEMBER(tlcs870_device::treg4_w)
// Time Base Timer
-// this is used with TLCS870_IRQ_INTTBT (FFF2 INTTBT) (not used by hng64)
+// this is used with TLCS870_IRQ_INTTBT (FFF2 INTTBT) (not used by hng64)
// the divider output makes use of PORT1 bit 3, which must be properly configured
WRITE8_MEMBER(tlcs870_device::tbtcr_w)
{
@@ -464,9 +464,9 @@ WRITE8_MEMBER(tlcs870_device::tbtcr_w)
LOG("%d: DVOCK-1 (Divide Output Frequency Selection)n", (m_TBTCR & 0x40) ? 1 : 0);
LOG("%d: DVOCK-0 (Divide Output Frequency Selection)\n", (m_TBTCR & 0x20) ? 1 : 0);
LOG("%d: DV7CK (?)\n", (m_TBTCR & 0x10) ? 1 : 0);
- LOG("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0);
- LOG("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0);
- LOG("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0);
+ LOG("%d: TBTEN (Time Base Timer Enable)\n", (m_TBTCR & 0x08) ? 1 : 0);
+ LOG("%d: TBTCK-2 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x04) ? 1 : 0);
+ LOG("%d: TBTCK-1 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x02) ? 1 : 0);
LOG("%d: TBTCK-0 (Time Base Timer Interrupt Frequency)\n", (m_TBTCR & 0x01) ? 1 : 0);
}
@@ -489,9 +489,9 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
LOG("%d: SIOINH1 (Abort/Continue transfer)\n", (m_SIOCR1[0] & 0x40) ? 1 : 0);
LOG("%d: SIOM1-2 (Serial Mode)\n", (m_SIOCR1[0] & 0x20) ? 1 : 0);
LOG("%d: SIOM1-1 (Serial Mode)\n", (m_SIOCR1[0] & 0x10) ? 1 : 0);
- LOG("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0);
- LOG("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0);
- LOG("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0);
+ LOG("%d: SIOM1-0 (Serial Mode)\n", (m_SIOCR1[0] & 0x08) ? 1 : 0);
+ LOG("%d: SCK1-2 (Serial Clock)\n", (m_SIOCR1[0] & 0x04) ? 1 : 0);
+ LOG("%d: SCK1-1 (Serial Clock)\n", (m_SIOCR1[0] & 0x02) ? 1 : 0);
LOG("%d: SCK1-0 (Serial Clock)\n", (m_SIOCR1[0] & 0x01) ? 1 : 0);
m_transfer_mode[0] = (m_SIOCR1[0] & 0x38) >> 3;
@@ -503,7 +503,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
m_receive_bits[0] = 0;
break;
- case 0x2:
+ case 0x2:
LOG("(Serial set to 4-bit transmit mode)\n");
m_transmit_bits[0] = 4;
m_receive_bits[0] = 0;
@@ -523,7 +523,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
case 0x6:
LOG("(Serial set to 4-bit receive mode)\n");
m_transmit_bits[0] = 0;
- m_receive_bits[0] = 4;
+ m_receive_bits[0] = 4;
break;
default:
@@ -540,7 +540,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr1_w)
m_transfer_shiftreg[0] = 0;
m_transfer_pos[0] = 0;
- m_serial_transmit_timer[0]->adjust(attotime::zero);
+ m_serial_transmit_timer[0]->adjust(attotime::zero);
}
}
@@ -554,9 +554,9 @@ WRITE8_MEMBER(tlcs870_device::sio1cr2_w)
LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x40) ? 1 : 0);
LOG("%d: (invalid)\n", (m_SIOCR2[0] & 0x20) ? 1 : 0);
LOG("%d: WAIT1-1 (Wait Control\n", (m_SIOCR2[0] & 0x10) ? 1 : 0);
- LOG("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0);
- LOG("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0);
- LOG("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0);
+ LOG("%d: WAIT1-0 (Wait Control)\n", (m_SIOCR2[0] & 0x08) ? 1 : 0);
+ LOG("%d: BUF1-2 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x04) ? 1 : 0);
+ LOG("%d: BUF1-1 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x02) ? 1 : 0);
LOG("%d: BUF1-0 (Number of Transfer Bytes)\n", (m_SIOCR2[0] & 0x01) ? 1 : 0);
m_transfer_numbytes[0] = (m_SIOCR2[0] & 0x7);
@@ -567,7 +567,7 @@ WRITE8_MEMBER(tlcs870_device::sio1cr2_w)
READ8_MEMBER(tlcs870_device::sio1sr_r)
{
/* TS-- ----
-
+
T = Transfer in Progress
S = Shift in Progress
@@ -625,9 +625,9 @@ WRITE8_MEMBER(tlcs870_device::sio2cr1_w)
LOG("%d: SIOINH2 (Abort/Continue transfer)\n", (m_SIOCR1[1] & 0x40) ? 1 : 0);
LOG("%d: SIOM2-2 (Serial Mode)\n", (m_SIOCR1[1] & 0x20) ? 1 : 0);
LOG("%d: SIOM2-1 (Serial Mode)\n", (m_SIOCR1[1] & 0x10) ? 1 : 0);
- LOG("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0);
- LOG("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0);
- LOG("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0);
+ LOG("%d: SIOM2-0 (Serial Mode)\n", (m_SIOCR1[1] & 0x08) ? 1 : 0);
+ LOG("%d: SCK2-2 (Serial Clock)\n", (m_SIOCR1[1] & 0x04) ? 1 : 0);
+ LOG("%d: SCK2-1 (Serial Clock)\n", (m_SIOCR1[1] & 0x02) ? 1 : 0);
LOG("%d: SCK2-0 (Serial Clock)\n", (m_SIOCR1[1] & 0x01) ? 1 : 0);
}
@@ -640,9 +640,9 @@ WRITE8_MEMBER(tlcs870_device::sio2cr2_w)
LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x40) ? 1 : 0);
LOG("%d: (invalid)\n", (m_SIOCR2[1] & 0x20) ? 1 : 0);
LOG("%d: WAIT2-1 (Wait Control\n", (m_SIOCR2[1] & 0x10) ? 1 : 0);
- LOG("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0);
- LOG("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0);
- LOG("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0);
+ LOG("%d: WAIT2-0 (Wait Control)\n", (m_SIOCR2[1] & 0x08) ? 1 : 0);
+ LOG("%d: BUF2-2 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x04) ? 1 : 0);
+ LOG("%d: BUF2-1 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x02) ? 1 : 0);
LOG("%d: BUF2-0 (Number of Transfer Bytes)\n", (m_SIOCR2[1] & 0x01) ? 1 : 0);
}
@@ -653,7 +653,7 @@ TIMER_CALLBACK_MEMBER(tlcs870_device::sio1_transmit_cb)
READ8_MEMBER(tlcs870_device::sio2sr_r)
{
/* TS-- ----
-
+
T = Transfer in Progress
S = Shift in Progress
@@ -672,9 +672,9 @@ WRITE8_MEMBER(tlcs870_device::wdtcr1_w)
LOG("%d: (invalid)\n", (m_WDTCR1 & 0x40) ? 1 : 0);
LOG("%d: (invalid)\n", (m_WDTCR1 & 0x20) ? 1 : 0);
LOG("%d: (invalid)\n", (m_WDTCR1 & 0x10) ? 1 : 0);
- LOG("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0);
- LOG("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0);
- LOG("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0);
+ LOG("%d: WDTEN (Watchdog Timer Enable, also req disable code to WDTCR2)\n", (m_WDTCR1 & 0x08) ? 1 : 0);
+ LOG("%d: WDTT-1 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x04) ? 1 : 0);
+ LOG("%d: WDTT-0 (Watchdog Timer Detection Time)\n", (m_WDTCR1 & 0x02) ? 1 : 0);
LOG("%d: WDTOUT (Watchdog Timer Output select, 0 = interrupt, 1 = reset out)\n",(m_WDTCR1 & 0x01) ? 1 : 0);
// WDTOUT cannot be set to 1 by software
@@ -708,9 +708,9 @@ WRITE8_MEMBER(tlcs870_device::syscr1_w)
LOG("%d: RELM (release method for STOP, 0 edge, 1 level)\n", (m_SYSCR1 & 0x40) ? 1 : 0);
LOG("%d: RETM (return mode after STOP, 0 normal, 1 slow)\n", (m_SYSCR1 & 0x20) ? 1 : 0);
LOG("%d: OUTEN (port output control during STOP)\n", (m_SYSCR1 & 0x10) ? 1 : 0);
- LOG("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0);
- LOG("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0);
- LOG("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0);
+ LOG("%d: WUT-1 (warm up time at STOP release)\n", (m_SYSCR1 & 0x08) ? 1 : 0);
+ LOG("%d: WUT-0 (warm up time at STOP release)\n", (m_SYSCR1 & 0x04) ? 1 : 0);
+ LOG("%d: (invalid)\n", (m_SYSCR1 & 0x02) ? 1 : 0);
LOG("%d: (invalid)\n", (m_SYSCR1 & 0x01) ? 1 : 0);
}
@@ -723,9 +723,9 @@ WRITE8_MEMBER(tlcs870_device::syscr2_w)
LOG("%d: XTEN (Low Frequency Oscillator control)\n", (m_SYSCR2 & 0x40) ? 1 : 0);
LOG("%d: SYSCK (system clock select 0 high, 1 low)\n", (m_SYSCR2 & 0x20) ? 1 : 0);
LOG("%d: IDLE (IDLE mode start)\n", (m_SYSCR2 & 0x10) ? 1 : 0); // hng64 sets this in case of ram test failures
- LOG("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0);
- LOG("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0);
- LOG("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0);
+ LOG("%d: (invalid)\n", (m_SYSCR2 & 0x08) ? 1 : 0);
+ LOG("%d: (invalid)\n", (m_SYSCR2 & 0x04) ? 1 : 0);
+ LOG("%d: (invalid)\n", (m_SYSCR2 & 0x02) ? 1 : 0);
LOG("%d: (invalid)\n", (m_SYSCR2 & 0x01) ? 1 : 0);
}
@@ -760,12 +760,12 @@ READ8_MEMBER(tlcs870_device::adcdr_r)
return m_ADCDR;
}
-/*
+/*
ADCCR register bits
es-apppp
-
+
e = end flag (1 = done, data available in ADCDR, 0 = not requested / not finished) (r/o)
s = start flag (1 = request data be processed and put in ADCDR)
@@ -810,9 +810,9 @@ WRITE8_MEMBER(tlcs870_device::eintcr_w)
LOG("%d: INT0EN (Interrupt 0 enable)\n", (m_EINTCR & 0x40) ? 1 : 0);
LOG("%d: (invalid)\n", (m_EINTCR & 0x20) ? 1 : 0);
LOG("%d: INT4ES (edge select)\n", (m_EINTCR & 0x10) ? 1 : 0);
- LOG("%d: INT3ES (edge select)\n", (m_EINTCR & 0x08) ? 1 : 0);
- LOG("%d: INT2ES (edge select)\n", (m_EINTCR & 0x04) ? 1 : 0);
- LOG("%d: INT1ES (edge select)\n", (m_EINTCR & 0x02) ? 1 : 0);
+ LOG("%d: INT3ES (edge select)\n", (m_EINTCR & 0x08) ? 1 : 0);
+ LOG("%d: INT2ES (edge select)\n", (m_EINTCR & 0x04) ? 1 : 0);
+ LOG("%d: INT1ES (edge select)\n", (m_EINTCR & 0x02) ? 1 : 0);
LOG("%d: (invalid)\n", (m_EINTCR & 0x01) ? 1 : 0);
/* For edge select register 0 = rising edge, 1 = falling edge
@@ -858,15 +858,15 @@ WRITE8_MEMBER(tlcs870_device::eir_h_w)
LOG("%d: EF12 (External Interrupt 4)\n", (m_EIR & 0x1000) ? 1 : 0);
LOG("%d: EF11 (External Interrupt 3)\n", (m_EIR & 0x0800) ? 1 : 0);
LOG("%d: EF10 (8-bit TC4 Interrupt)\n", (m_EIR & 0x0400) ? 1 : 0);
- LOG("%d: EF9 (Serial Interface 1 Interrupt)\n", (m_EIR & 0x0200) ? 1 : 0);
+ LOG("%d: EF9 (Serial Interface 1 Interrupt)\n", (m_EIR & 0x0200) ? 1 : 0);
LOG("%d: EF8 (8-bit TC3 Interrupt)\n", (m_EIR & 0x0100) ? 1 : 0);
}
/*
- the READ/WRITE/MODIFY operations cannot be used to clear interrupt latches
+ the READ/WRITE/MODIFY operations cannot be used to clear interrupt latches
- also you can't set a latch by writing '1' to it, only clear a latch
- by writing 0 to it
+ also you can't set a latch by writing '1' to it, only clear a latch
+ by writing 0 to it
*/
READ8_MEMBER(tlcs870_device::il_l_r)
@@ -1028,7 +1028,7 @@ void tlcs870_device::execute_run()
void tlcs870_device::device_reset()
{
m_pc.d = RM16(0xfffe);
-
+
m_RBS = 0x00;
m_EIR = 0x0000;
m_IL = 0x0000;
diff --git a/src/devices/cpu/tlcs870/tlcs870.h b/src/devices/cpu/tlcs870/tlcs870.h
index 7d23d08c71e..93390d1be0c 100644
--- a/src/devices/cpu/tlcs870/tlcs870.h
+++ b/src/devices/cpu/tlcs870/tlcs870.h
@@ -174,7 +174,7 @@ private:
uint8_t m_port_out_latch[8];
int m_read_input_port;
uint8_t m_port0_cr, m_port1_cr, m_port6_cr, m_port7_cr;
-
+
DECLARE_READ8_MEMBER(port0_r);
DECLARE_READ8_MEMBER(port1_r);
DECLARE_READ8_MEMBER(port2_r);
@@ -279,7 +279,7 @@ private:
uint16_t m_TREG1B;
uint8_t m_TC1CR;
uint16_t m_TREG2;
- uint8_t m_TC2CR;
+ uint8_t m_TC2CR;
uint8_t m_TREG3A;
uint8_t m_TREG3B;
uint8_t m_TC3CR;
diff --git a/src/devices/cpu/tlcs870/tlcs870_ops.cpp b/src/devices/cpu/tlcs870/tlcs870_ops.cpp
index 3a14f319ae2..f215774b5d0 100644
--- a/src/devices/cpu/tlcs870/tlcs870_ops.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870_ops.cpp
@@ -4,7 +4,7 @@
Toshiba TLCS-870 Series MCUs
- direct opcodes, no prefix
+ direct opcodes, no prefix
*************************************************************************************************************/
@@ -158,7 +158,7 @@ void tlcs870_device::do_NOP(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- NOP 0000 0000 - - - - 1
+ NOP 0000 0000 - - - - 1
*/
m_cycles = 1;
}
@@ -167,7 +167,7 @@ void tlcs870_device::do_SWAP_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SWAP A 0000 0001 1 - - - 3
+ SWAP A 0000 0001 1 - - - 3
*/
m_cycles = 3;
@@ -178,7 +178,7 @@ void tlcs870_device::do_MUL_W_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- MUL W, A 0000 0010 Z Z - - 7
+ MUL W, A 0000 0010 Z Z - - 7
*/
m_cycles = 7;
@@ -189,7 +189,7 @@ void tlcs870_device::do_DIV_WA_C(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DIV WA, C 0000 0011 Z Z C - 7
+ DIV WA, C 0000 0011 Z Z C - 7
*/
m_cycles = 7;
@@ -199,10 +199,10 @@ void tlcs870_device::do_DIV_WA_C(const uint8_t opbyte0)
void tlcs870_device::do_RETI(const uint8_t opbyte0)
{
/*
- Return from maskable interrupt service (how does this differ from RETN?)
+ Return from maskable interrupt service (how does this differ from RETN?)
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- RETI 0000 0100 * * * * 6
+ RETI 0000 0100 * * * * 6
*/
m_cycles = 6;
@@ -218,7 +218,7 @@ void tlcs870_device::do_RET(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- RET 0000 0101 - - - - 6
+ RET 0000 0101 - - - - 6
*/
m_cycles = 6;
@@ -230,7 +230,7 @@ void tlcs870_device::do_POP_PSW(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- POP PSW 0000 0110 * * * * 3
+ POP PSW 0000 0110 * * * * 3
*/
m_cycles = 3;
@@ -243,7 +243,7 @@ void tlcs870_device::do_PUSH_PSW(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- POP PSW 0000 0111 - - - - 2
+ POP PSW 0000 0111 - - - - 2
*/
m_cycles = 2;
@@ -256,7 +256,7 @@ void tlcs870_device::do_DAA_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DAA A 0000 1010 C Z C H 2
+ DAA A 0000 1010 C Z C H 2
*/
m_cycles = 2;
@@ -271,7 +271,7 @@ void tlcs870_device::do_DAS_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DAS A 0000 1011 C Z C H 2
+ DAS A 0000 1011 C Z C H 2
*/
m_cycles = 2;
@@ -286,7 +286,7 @@ void tlcs870_device::do_CLR_CF(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR CF 0000 1100 1 - 0 - 1
+ CLR CF 0000 1100 1 - 0 - 1
*/
m_cycles = 1;
@@ -298,7 +298,7 @@ void tlcs870_device::do_SET_CF(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SET CF 0000 1101 0 - 1 - 1
+ SET CF 0000 1101 0 - 1 - 1
*/
m_cycles = 1;
@@ -310,7 +310,7 @@ void tlcs870_device::do_CPL_CF(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CPL CF 0000 1110 * - * - 1
+ CPL CF 0000 1110 * - * - 1
*/
m_cycles = 1;
@@ -330,7 +330,7 @@ void tlcs870_device::do_LD_RBS_n(const uint8_t opbyte0) // register bank switchi
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD RBS, n 0000 1111 0000 nnnn 1 - - - 4
+ LD RBS, n 0000 1111 0000 nnnn 1 - - - 4
*/
m_cycles = 4;
@@ -344,7 +344,7 @@ void tlcs870_device::do_INC_rr(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- INC rr 0001 00rr C Z - - 2
+ INC rr 0001 00rr C Z - - 2
*/
m_cycles = 2;
@@ -371,7 +371,7 @@ void tlcs870_device::do_LD_rr_mn(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD rr,mn 0001 01rr nnnn nnnn mmmm mmmm 1 - - - 3
+ LD rr,mn 0001 01rr nnnn nnnn mmmm mmmm 1 - - - 3
*/
m_cycles = 3;
@@ -385,7 +385,7 @@ void tlcs870_device::do_DEC_rr(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DEC rr 0001 10rr C Z - - 2
+ DEC rr 0001 10rr C Z - - 2
*/
m_cycles = 2;
@@ -419,7 +419,7 @@ void tlcs870_device::do_SHLC_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SHLC A 0001 1100 C Z * - 1
+ SHLC A 0001 1100 C Z * - 1
*/
m_cycles = 1;
@@ -434,7 +434,7 @@ void tlcs870_device::do_SHRC_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SHRC A 0001 1101 C Z * - 1
+ SHRC A 0001 1101 C Z * - 1
*/
m_cycles = 1;
@@ -449,7 +449,7 @@ void tlcs870_device::do_ROLC_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ROLC A 0001 1110 C Z * - 1
+ ROLC A 0001 1110 C Z * - 1
*/
m_cycles = 1;
@@ -464,7 +464,7 @@ void tlcs870_device::do_RORC_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- RORC A 0001 1111 C Z * - 1
+ RORC A 0001 1111 C Z * - 1
*/
m_cycles = 1;
@@ -479,7 +479,7 @@ void tlcs870_device::do_INC_inx(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- INC (x) 0010 0000 xxxx xxxx C Z - - 5
+ INC (x) 0010 0000 xxxx xxxx C Z - - 5
*/
m_cycles = 5;
@@ -507,7 +507,7 @@ void tlcs870_device::do_INC_inHL(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- INC (HL) 0010 0001 C Z - - 4
+ INC (HL) 0010 0001 C Z - - 4
*/
m_cycles = 4;
@@ -534,7 +534,7 @@ void tlcs870_device::do_LD_A_inx(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD A, (x) 0010 0010 xxxx xxxx 1 Z - - 3
+ LD A, (x) 0010 0010 xxxx xxxx 1 Z - - 3
*/
m_cycles = 3;
@@ -553,7 +553,7 @@ void tlcs870_device::do_LD_A_inHL(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD A, (HL) 0010 0011 1 Z - - 2
+ LD A, (HL) 0010 0011 1 Z - - 2
*/
m_cycles = 2;
@@ -572,7 +572,7 @@ void tlcs870_device::do_LD_inx_iny(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), (y) 0010 0110 yyyy yyyy xxxx xxxx 1 Z - - 5
+ LD (x), (y) 0010 0110 yyyy yyyy xxxx xxxx 1 Z - - 5
*/
m_cycles = 5;
@@ -593,7 +593,7 @@ void tlcs870_device::do_DEC_inx(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DEC (x) 0010 1000 xxxx xxxx C Z - - 5
+ DEC (x) 0010 1000 xxxx xxxx C Z - - 5
*/
m_cycles = 5;
@@ -627,7 +627,7 @@ void tlcs870_device::do_DEC_inHL(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DEC (HL) 0010 1001 C Z - - 4
+ DEC (HL) 0010 1001 C Z - - 4
*/
m_cycles = 4;
@@ -661,7 +661,7 @@ void tlcs870_device::do_LD_inx_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), A 0010 1010 xxxx xxxx 1 - - - 3
+ LD (x), A 0010 1010 xxxx xxxx 1 - - - 3
*/
m_cycles = 3;
@@ -680,7 +680,7 @@ void tlcs870_device::do_LD_inHL_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (HL), A 0010 1011 1 - - - 2
+ LD (HL), A 0010 1011 1 - - - 2
*/
m_cycles = 2;
@@ -696,7 +696,7 @@ void tlcs870_device::do_LD_inx_n(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), n 0010 1100 xxxx xxxx nnnn nnnn 1 - - - 4
+ LD (x), n 0010 1100 xxxx xxxx nnnn nnnn 1 - - - 4
*/
m_cycles = 4;
@@ -712,7 +712,7 @@ void tlcs870_device::do_LD_inHL_n(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (HL), n 0010 1101 nnnn nnnn 1 - - - 3
+ LD (HL), n 0010 1101 nnnn nnnn 1 - - - 3
*/
m_cycles = 3;
@@ -728,7 +728,7 @@ void tlcs870_device::do_CLR_inx(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR (x) 0010 1110 xxxx xxxx 1 - - - 4
+ CLR (x) 0010 1110 xxxx xxxx 1 - - - 4
*/
m_cycles = 4;
@@ -743,7 +743,7 @@ void tlcs870_device::do_CLR_inHL(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR (HL) 0010 1111 1 - - - 2
+ CLR (HL) 0010 1111 1 - - - 2
*/
m_cycles = 2;
@@ -757,7 +757,7 @@ void tlcs870_device::do_LD_r_n(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD r,n 0011 0rrr nnnn nnnn 1 - - - 2
+ LD r,n 0011 0rrr nnnn nnnn 1 - - - 2
*/
m_cycles = 2;
@@ -773,9 +773,9 @@ void tlcs870_device::do_SET_inxbit(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SET (x).b 0100 0bbb xxxx xxxx Z * - - 5
+ SET (x).b 0100 0bbb xxxx xxxx Z * - - 5
- (opbyte0 == 0x40) && (opval == 0x3a) is EI
+ (opbyte0 == 0x40) && (opval == 0x3a) is EI
*/
m_cycles = 5;
@@ -807,9 +807,9 @@ void tlcs870_device::do_CLR_inxbit(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR (x).b 0100 1bbb xxxx xxxx Z * - - 5
+ CLR (x).b 0100 1bbb xxxx xxxx Z * - - 5
- (opbyte0 == 0x48) && (opval == 0x3a) is DI
+ (opbyte0 == 0x48) && (opval == 0x3a) is DI
*/
m_cycles = 5;
@@ -841,7 +841,7 @@ void tlcs870_device::do_LD_A_r(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD A, r 0101 0rrr 1 Z - - 1
+ LD A, r 0101 0rrr 1 Z - - 1
*/
m_cycles = 1;
@@ -858,7 +858,7 @@ void tlcs870_device::do_LD_r_A(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD r, A 0101 1rrr 1 Z - - 1
+ LD r, A 0101 1rrr 1 Z - - 1
*/
m_cycles = 1;
@@ -875,7 +875,7 @@ void tlcs870_device::do_INC_r(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- INC r 0110 0rrr C Z - - 1
+ INC r 0110 0rrr C Z - - 1
*/
m_cycles = 1;
@@ -901,7 +901,7 @@ void tlcs870_device::do_DEC_r(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DEC r 0110 1rrr C Z - - 1
+ DEC r 0110 1rrr C Z - - 1
*/
m_cycles = 1;
@@ -933,10 +933,10 @@ void tlcs870_device::do_DEC_r(const uint8_t opbyte0)
void tlcs870_device::do_JRS_T_a(const uint8_t opbyte0)
{
/*
- Jump Relative Short, if True
+ Jump Relative Short, if True
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JRS T, a 100d dddd 1 - - - 4 (2 if not taken)
+ JRS T, a 100d dddd 1 - - - 4 (2 if not taken)
*/
m_cycles = 2;
@@ -950,7 +950,7 @@ void tlcs870_device::do_JRS_T_a(const uint8_t opbyte0)
m_cycles += 2;
m_addr = m_tmppc + 2 + val;
}
-
+
// always gets set?
set_JF();
}
@@ -958,10 +958,10 @@ void tlcs870_device::do_JRS_T_a(const uint8_t opbyte0)
void tlcs870_device::do_JRS_F_a(const uint8_t opbyte0)
{
/*
- Jump Relative Short, if False
+ Jump Relative Short, if False
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JRS F, a 101d dddd 1 - - - 4 (2 if not taken)
+ JRS F, a 101d dddd 1 - - - 4 (2 if not taken)
*/
m_cycles = 2;
@@ -975,7 +975,7 @@ void tlcs870_device::do_JRS_F_a(const uint8_t opbyte0)
m_cycles += 2;
m_addr = m_tmppc + 2 + val;
}
-
+
// manual isn't clear in description, but probably always set?
set_JF();
}
@@ -983,10 +983,10 @@ void tlcs870_device::do_JRS_F_a(const uint8_t opbyte0)
void tlcs870_device::do_CALLV_n(const uint8_t opbyte0)
{
/*
- Call Vector
+ Call Vector
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CALLV n 1100 nnnn - - - - 7
+ CALLV n 1100 nnnn - - - - 7
*/
m_cycles = 7;
@@ -1002,14 +1002,14 @@ void tlcs870_device::do_JR_cc_a(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JR T, a 1101 0110 dddd dddd 1 - - - 4 (2 if not taken)
- JR F, a 1101 0111 dddd dddd 1 - - - 4 (2 if not taken)
- JR EQ, a (Z, a) 1101 0000 dddd dddd 1 - - - 4 (2 if not taken)
- JR NE, a (NZ, a) 1101 0001 dddd dddd 1 - - - 4 (2 if not taken)
- JR CS, a (LT, a) 1101 0010 dddd dddd 1 - - - 4 (2 if not taken)
- JR CC, a (GE, a) 1101 0011 dddd dddd 1 - - - 4 (2 if not taken)
- JR LE, a 1101 0100 dddd dddd 1 - - - 4 (2 if not taken)
- JR GT, a 1101 0101 dddd dddd 1 - - - 4 (2 if not taken)
+ JR T, a 1101 0110 dddd dddd 1 - - - 4 (2 if not taken)
+ JR F, a 1101 0111 dddd dddd 1 - - - 4 (2 if not taken)
+ JR EQ, a (Z, a) 1101 0000 dddd dddd 1 - - - 4 (2 if not taken)
+ JR NE, a (NZ, a) 1101 0001 dddd dddd 1 - - - 4 (2 if not taken)
+ JR CS, a (LT, a) 1101 0010 dddd dddd 1 - - - 4 (2 if not taken)
+ JR CC, a (GE, a) 1101 0011 dddd dddd 1 - - - 4 (2 if not taken)
+ JR LE, a 1101 0100 dddd dddd 1 - - - 4 (2 if not taken)
+ JR GT, a 1101 0101 dddd dddd 1 - - - 4 (2 if not taken)
*/
m_cycles = 2;
@@ -1034,9 +1034,9 @@ void tlcs870_device::do_LD_CF_inxbit(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD CF, (x).b 1101 1bbb xxxx xxxx ~C - * - 4
+ LD CF, (x).b 1101 1bbb xxxx xxxx ~C - * - 4
- aka TEST (x).b
+ aka TEST (x).b
*/
m_cycles = 4;
@@ -1057,7 +1057,7 @@ void tlcs870_device::do_LD_SP_mn(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD SP ,mn 1111 1010 nnnn nnnn mmmm mmmm 1 - - - 3
+ LD SP ,mn 1111 1010 nnnn nnnn mmmm mmmm 1 - - - 3
*/
m_cycles = 3;
@@ -1070,7 +1070,7 @@ void tlcs870_device::do_JR_a(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JR a 1111 1011 dddd dddd 1 - - - 4
+ JR a 1111 1011 dddd dddd 1 - - - 4
*/
m_cycles = 4;
@@ -1086,7 +1086,7 @@ void tlcs870_device::do_CALL_mn(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CALL mn 1111 1100 nnnn nnnn mmmm mmmm - - - - 6
+ CALL mn 1111 1100 nnnn nnnn mmmm mmmm - - - - 6
*/
m_cycles = 6;
@@ -1102,7 +1102,7 @@ void tlcs870_device::do_CALLP_n(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CALLP n 1111 1101 nnnn nnnn - - - - 6
+ CALLP n 1111 1101 nnnn nnnn - - - - 6
*/
m_cycles = 6;
@@ -1118,7 +1118,7 @@ void tlcs870_device::do_JP_mn(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JP mn 1111 1110 nnnn nnnn mmmm mmmm 1 - - - 4
+ JP mn 1111 1110 nnnn nnnn mmmm mmmm 1 - - - 4
*/
m_cycles = 4;
@@ -1130,8 +1130,8 @@ void tlcs870_device::do_JP_mn(const uint8_t opbyte0)
void tlcs870_device::do_ff_opcode(const uint8_t opbyte0)
{
/*
- OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SWI 1111 1111 - - - - 9 (1 if already in NMI)
+ OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
+ SWI 1111 1111 - - - - 9 (1 if already in NMI)
*/
m_cycles = 9; // TODO: 1 if in NMI this acts as a NOP
@@ -1147,14 +1147,14 @@ void tlcs870_device::do_ALUOP_A_n(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC A, n 0111 0000 nnnn nnnn C Z C H 2
- ADD A, n 0111 0001 nnnn nnnn C Z C H 2
- SUBB A, n 0111 0010 nnnn nnnn C Z C H 2
- SUB A, n 0111 0011 nnnn nnnn C Z C H 2
- AND A, n 0111 0100 nnnn nnnn Z Z - - 2
- XOR A, n 0111 0101 nnnn nnnn Z Z - - 2
- OR A, n 0111 0110 nnnn nnnn Z Z - - 2
- CMP A, n 0111 0111 nnnn nnnn Z Z C H 2
+ ADDC A, n 0111 0000 nnnn nnnn C Z C H 2
+ ADD A, n 0111 0001 nnnn nnnn C Z C H 2
+ SUBB A, n 0111 0010 nnnn nnnn C Z C H 2
+ SUB A, n 0111 0011 nnnn nnnn C Z C H 2
+ AND A, n 0111 0100 nnnn nnnn Z Z - - 2
+ XOR A, n 0111 0101 nnnn nnnn Z Z - - 2
+ OR A, n 0111 0110 nnnn nnnn Z Z - - 2
+ CMP A, n 0111 0111 nnnn nnnn Z Z C H 2
*/
m_cycles = 2;
@@ -1173,14 +1173,14 @@ void tlcs870_device::do_ALUOP_A_inx(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC A, (x) 0111 1000 xxxx xxxx C Z C H 4
- ADD A, (x) 0111 1001 xxxx xxxx C Z C H 4
- SUBB A, (x) 0111 1010 xxxx xxxx C Z C H 4
- SUB A, (x) 0111 1011 xxxx xxxx C Z C H 4
- AND A, (x) 0111 1100 xxxx xxxx Z Z - - 4
- XOR A, (x) 0111 1101 xxxx xxxx Z Z - - 4
- OR A, (x) 0111 1110 xxxx xxxx Z Z - - 4
- CMP A, (x) 0111 1111 xxxx xxxx Z Z C H 4
+ ADDC A, (x) 0111 1000 xxxx xxxx C Z C H 4
+ ADD A, (x) 0111 1001 xxxx xxxx C Z C H 4
+ SUBB A, (x) 0111 1010 xxxx xxxx C Z C H 4
+ SUB A, (x) 0111 1011 xxxx xxxx C Z C H 4
+ AND A, (x) 0111 1100 xxxx xxxx Z Z - - 4
+ XOR A, (x) 0111 1101 xxxx xxxx Z Z - - 4
+ OR A, (x) 0111 1110 xxxx xxxx Z Z - - 4
+ CMP A, (x) 0111 1111 xxxx xxxx Z Z C H 4
*/
m_cycles = 4;
@@ -1204,7 +1204,7 @@ void tlcs870_device::do_LDW_inx_mn(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LDW (x), mn 0010 0100 xxxx xxxx nnnn nnnn mmmm mmmm 1 - - - 6
+ LDW (x), mn 0010 0100 xxxx xxxx nnnn nnnn mmmm mmmm 1 - - - 6
*/
m_cycles = 6;
@@ -1221,7 +1221,7 @@ void tlcs870_device::do_LDW_inHL_mn(const uint8_t opbyte0)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LDW (HL), mn 0010 0101 nnnn nnnn mmmm mmmm 1 - - - 5
+ LDW (HL), mn 0010 0101 nnnn nnnn mmmm mmmm 1 - - - 5
*/
m_cycles = 5;
diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp
index 3f5a77d0217..058368d5a5d 100644
--- a/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870_ops_dst.cpp
@@ -6,19 +6,19 @@
(dst) prefix ops (f0 to f7 subtable)
- (dst) address depends on the first byte of the opcode
+ (dst) address depends on the first byte of the opcode
- F0 (x)
- F1 invalid (would be (PC+A) based on the src table, check for undefined behavior?)
- F2 (DE)
- F3 (HL)
- F4 (HL+d)
- F5 invalid (would be (HL+C) based on the src table, check for undefined behavior?)
- F6 (HL+)
- F7 (-HL)
+ F0 (x)
+ F1 invalid (would be (PC+A) based on the src table, check for undefined behavior?)
+ F2 (DE)
+ F3 (HL)
+ F4 (HL+d)
+ F5 invalid (would be (HL+C) based on the src table, check for undefined behavior?)
+ F6 (HL+)
+ F7 (-HL)
- note, in cases where the address is an immediate value, not a register (x) and (HL+d) the
- immediate value is directly after the first byte of the opcode
+ note, in cases where the address is an immediate value, not a register (x) and (HL+d) the
+ immediate value is directly after the first byte of the opcode
*************************************************************************************************************/
@@ -83,17 +83,17 @@ void tlcs870_device::do_LD_indst_rr(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), rr 1111 0000 xxxx xxxx 0001 00rr 1 - - - 5
- LD (PC+A), rr invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
- LD (DE), rr 1111 0010 0001 00rr 1 - - - 4
- LD (HL), rr 1111 0011 0001 00rr 1 - - - 4
- LD (HL+d), rr 1111 0100 dddd dddd 0001 00rr 1 - - - 6
- LD (HL+C), rr invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
- LD (HL+), rr not listed, invalid due to 16-bit op? ? ? ? ? ?
- LD (-HL), rr not listed, invalid due to 16-bit op? ? ? ? ? ?
+ LD (x), rr 1111 0000 xxxx xxxx 0001 00rr 1 - - - 5
+ LD (PC+A), rr invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
+ LD (DE), rr 1111 0010 0001 00rr 1 - - - 4
+ LD (HL), rr 1111 0011 0001 00rr 1 - - - 4
+ LD (HL+d), rr 1111 0100 dddd dddd 0001 00rr 1 - - - 6
+ LD (HL+C), rr invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
+ LD (HL+), rr not listed, invalid due to 16-bit op? ? ? ? ? ?
+ LD (-HL), rr not listed, invalid due to 16-bit op? ? ? ? ? ?
- aka LD (dst),rr
- (dst) can only be (x) (pp) or (HL+d) ? not (HL+) or (-HL) ?
+ aka LD (dst),rr
+ (dst) can only be (x) (pp) or (HL+d) ? not (HL+) or (-HL) ?
*/
m_cycles += 4;
@@ -111,17 +111,17 @@ void tlcs870_device::do_LD_indst_n(const uint8_t opbyte0, const uint8_t opbyte1,
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), n not listed, redundant encoding? ? ? ? ? ?
- LD (PC+A), n invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
- LD (DE), n 1111 0010 0010 1100 nnnn nnnn 1 - - - 4
- LD (HL), n not listed, redundant encoding? ? ? ? ? ?
- LD (HL+d), n 1111 0100 dddd dddd 0010 1100 nnnn nnnn 1 - - - 6
- LD (HL+C), n invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
- LD (HL+), n 1111 0110 0010 1100 nnnn nnnn 1 - - - 5
- LD (-HL), n 1111 0111 0010 1100 nnnn nnnn 1 - - - 5
+ LD (x), n not listed, redundant encoding? ? ? ? ? ?
+ LD (PC+A), n invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
+ LD (DE), n 1111 0010 0010 1100 nnnn nnnn 1 - - - 4
+ LD (HL), n not listed, redundant encoding? ? ? ? ? ?
+ LD (HL+d), n 1111 0100 dddd dddd 0010 1100 nnnn nnnn 1 - - - 6
+ LD (HL+C), n invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
+ LD (HL+), n 1111 0110 0010 1100 nnnn nnnn 1 - - - 5
+ LD (-HL), n 1111 0111 0010 1100 nnnn nnnn 1 - - - 5
- aka (dst),n
- (dst) can only be (DE), (HL+), (-HL), or (HL+d) because (x) and (HL) are redundant encodings?
+ aka (dst),n
+ (dst) can only be (DE), (HL+), (-HL), or (HL+d) because (x) and (HL) are redundant encodings?
*/
m_cycles += 4;
@@ -135,16 +135,16 @@ void tlcs870_device::do_LD_indst_r(const uint8_t opbyte0, const uint8_t opbyte1,
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), r 1111 0000 xxxx xxxx 0101 1rrr 1 - - - 4
- LD (PC+A), r invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
- LD (DE), r 1111 0010 0101 1rrr 1 - - - 3
- LD (HL), r 1111 0011 0101 1rrr 1 - - - 3
- LD (HL+d), r 1111 0100 dddd dddd 0101 1rrr 1 - - - 5
- LD (HL+C), r invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
- LD (HL+), r 1111 0110 0101 0rrr 1 - - - 4 (invalid if r is H or L)
- LD (-HL), r 1111 0111 0101 0rrr 1 - - - 4
+ LD (x), r 1111 0000 xxxx xxxx 0101 1rrr 1 - - - 4
+ LD (PC+A), r invalid encoding (all PC+A are invalid for dst) ? ? ? ? ?
+ LD (DE), r 1111 0010 0101 1rrr 1 - - - 3
+ LD (HL), r 1111 0011 0101 1rrr 1 - - - 3
+ LD (HL+d), r 1111 0100 dddd dddd 0101 1rrr 1 - - - 5
+ LD (HL+C), r invalid encoding (all HL+C are invalid for dst) ? ? ? ? ?
+ LD (HL+), r 1111 0110 0101 0rrr 1 - - - 4 (invalid if r is H or L)
+ LD (-HL), r 1111 0111 0101 0rrr 1 - - - 4
- aka LD (dst),r
+ aka LD (dst),r
*/
m_cycles += 3;
diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp
index c2fb2fb90cb..d0e6f9de3ef 100644
--- a/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870_ops_helper.cpp
@@ -216,35 +216,35 @@ const bool tlcs870_device::check_jump_condition(int param1)
return takejump;
}
-/*
- All 16-bit ALU ops that would set the 'H' flag list the behavior as undefined.
- Logically the half flag would be the 8/9 bit carry (usual C flag) in a 16-bit
- op, but since this isn't listed as being the case there's a chance the behavior
- is something unexpected, such as still using the 3/4 carry, or, if it's
- internally handled as 4 4-bit operations, maybe the 12/13 bit carry
+/*
+ All 16-bit ALU ops that would set the 'H' flag list the behavior as undefined.
+ Logically the half flag would be the 8/9 bit carry (usual C flag) in a 16-bit
+ op, but since this isn't listed as being the case there's a chance the behavior
+ is something unexpected, such as still using the 3/4 carry, or, if it's
+ internally handled as 4 4-bit operations, maybe the 12/13 bit carry
- This needs testing on hardware.
+ This needs testing on hardware.
- (8-bit) JF ZF CF HF
- ADDC C Z C H
- ADD C Z C H
- SUBB C Z C H
- SUB C Z C H
- AND Z Z - -
- XOR Z Z - -
- OR Z Z - -
- CMP Z Z C H
+ (8-bit) JF ZF CF HF
+ ADDC C Z C H
+ ADD C Z C H
+ SUBB C Z C H
+ SUB C Z C H
+ AND Z Z - -
+ XOR Z Z - -
+ OR Z Z - -
+ CMP Z Z C H
+
+ (16-bit)
+ ADDC C Z C U
+ ADD C Z C U
+ SUBB C Z C U
+ SUB C Z C U
+ AND Z Z - -
+ XOR Z Z - -
+ OR Z Z - -
+ CMP Z Z C U
- (16-bit)
- ADDC C Z C U
- ADD C Z C U
- SUBB C Z C U
- SUB C Z C U
- AND Z Z - -
- XOR Z Z - -
- OR Z Z - -
- CMP Z Z C U
-
*/
uint8_t tlcs870_device::do_add_8bit(uint16_t param1, uint16_t param2)
diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp
index 9a5177d5831..74cbd7d071a 100644
--- a/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870_ops_reg.cpp
@@ -6,31 +6,31 @@
(reg) prefix ops (e8 to ef subtable)
- (reg) implies one of the follow registers
+ (reg) implies one of the follow registers
(8-bit mode operations)
- E8 A
- E9 W
- EA C
- EB B
- EC E
- ED D
- EE L
- EF H
+ E8 A
+ E9 W
+ EA C
+ EB B
+ EC E
+ ED D
+ EE L
+ EF H
- (16-bit mode operations)
+ (16-bit mode operations)
E8 WA
- E9 BC
- EA DE
- EB HL
- EC WA
- ED BC
- EE DE
- EF HL
+ E9 BC
+ EA DE
+ EB HL
+ EC WA
+ ED BC
+ EE DE
+ EF HL
- (RETN operation - special)
- E8 RETN
- E9-EF invalid
+ (RETN operation - special)
+ E8 RETN
+ E9-EF invalid
*************************************************************************************************************/
@@ -145,9 +145,9 @@ void tlcs870_device::do_RETN(const uint8_t opbyte0, const uint8_t opbyte1)
if (opbyte0 == 0xe8)
{
/*
- Return from non-maskable interrupt service (how does this differ from RETI?)
- OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- RETN 1110 1000 0000 0100 * * * * 7
+ Return from non-maskable interrupt service (how does this differ from RETI?)
+ OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
+ RETN 1110 1000 0000 0100 * * * * 7
*/
m_cycles = 7;
@@ -169,7 +169,7 @@ void tlcs870_device::do_SWAP_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SWAP g 1110 1ggg 0000 0001 1 - - - 4
+ SWAP g 1110 1ggg 0000 0001 1 - - - 4
*/
m_cycles = 4;
@@ -181,7 +181,7 @@ void tlcs870_device::do_DAA_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DAS g 1110 1ggg 0000 1010 C Z C H 3
+ DAS g 1110 1ggg 0000 1010 C Z C H 3
*/
m_cycles = 3;
@@ -197,7 +197,7 @@ void tlcs870_device::do_DAS_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DAS g 1110 1ggg 0000 1011 C Z C H 3
+ DAS g 1110 1ggg 0000 1011 C Z C H 3
*/
m_cycles = 3;
@@ -212,9 +212,9 @@ void tlcs870_device::do_DAS_g(const uint8_t opbyte0, const uint8_t opbyte1)
void tlcs870_device::do_SHLC_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
- Logical Shift Left with Carry Flag
+ Logical Shift Left with Carry Flag
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SHLC g 1110 1ggg 0001 1100 C Z * - 2
+ SHLC g 1110 1ggg 0001 1100 C Z * - 2
*/
m_cycles = 2;
@@ -228,9 +228,9 @@ void tlcs870_device::do_SHLC_g(const uint8_t opbyte0, const uint8_t opbyte1)
void tlcs870_device::do_SHRC_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
- Logical Shift Right with Carry Flag
+ Logical Shift Right with Carry Flag
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SHRC g 1110 1ggg 0001 1101 C Z * - 2
+ SHRC g 1110 1ggg 0001 1101 C Z * - 2
*/
m_cycles = 2;
@@ -244,9 +244,9 @@ void tlcs870_device::do_SHRC_g(const uint8_t opbyte0, const uint8_t opbyte1)
void tlcs870_device::do_ROLC_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
- Rotate Left through Carry flag
+ Rotate Left through Carry flag
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ROLC g 1110 1ggg 0001 1110 C Z * - 2
+ ROLC g 1110 1ggg 0001 1110 C Z * - 2
*/
m_cycles = 2;
@@ -261,9 +261,9 @@ void tlcs870_device::do_ROLC_g(const uint8_t opbyte0, const uint8_t opbyte1)
void tlcs870_device::do_RORC_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
- Rotate Right through Carry flag
+ Rotate Right through Carry flag
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- RORC g 1110 1ggg 0001 1111 C Z * - 2
+ RORC g 1110 1ggg 0001 1111 C Z * - 2
*/
m_cycles = 2;
@@ -279,7 +279,7 @@ void tlcs870_device::do_LD_r_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD r, g 1110 1ggg 0101 1rrr 1 Z - - 2
+ LD r, g 1110 1ggg 0101 1rrr 1 Z - - 2
*/
m_cycles = 2;
@@ -296,7 +296,7 @@ void tlcs870_device::do_XCH_r_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- XCG r, g 1110 1ggg 1010 1rrr 1 Z - - 3
+ XCG r, g 1110 1ggg 1010 1rrr 1 Z - - 3
*/
m_cycles = 3;
@@ -320,14 +320,14 @@ void tlcs870_device::do_ALUOP_A_g(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC A, g 1110 1ggg 0110 0000 C Z C H 2
- ADD A, g 1110 1ggg 0110 0001 C Z C H 2
- SUBB A, g 1110 1ggg 0110 0010 C Z C H 2
- SUB A, g 1110 1ggg 0110 0011 C Z C H 2
- AND A, g 1110 1ggg 0110 0100 Z Z - - 2
- XOR A, g 1110 1ggg 0110 0101 Z Z - - 2
- OR A, g 1110 1ggg 0110 0110 Z Z - - 2
- CMP A, g 1110 1ggg 0110 0111 Z Z C H 2
+ ADDC A, g 1110 1ggg 0110 0000 C Z C H 2
+ ADD A, g 1110 1ggg 0110 0001 C Z C H 2
+ SUBB A, g 1110 1ggg 0110 0010 C Z C H 2
+ SUB A, g 1110 1ggg 0110 0011 C Z C H 2
+ AND A, g 1110 1ggg 0110 0100 Z Z - - 2
+ XOR A, g 1110 1ggg 0110 0101 Z Z - - 2
+ OR A, g 1110 1ggg 0110 0110 Z Z - - 2
+ CMP A, g 1110 1ggg 0110 0111 Z Z C H 2
*/
m_cycles = 2;
@@ -345,14 +345,14 @@ void tlcs870_device::do_ALUOP_g_A(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC g, A 1110 1ggg 0110 1000 C Z C H 3
- ADD g, A 1110 1ggg 0110 1001 C Z C H 3
- SUBB g, A 1110 1ggg 0110 1010 C Z C H 3
- SUB g, A 1110 1ggg 0110 1011 C Z C H 3
- AND g, A 1110 1ggg 0110 1100 Z Z - - 3
- XOR g, A 1110 1ggg 0110 1101 Z Z - - 3
- OR g, A 1110 1ggg 0110 1110 Z Z - - 3
- CMP g, A 1110 1ggg 0110 1111 Z Z C H 3
+ ADDC g, A 1110 1ggg 0110 1000 C Z C H 3
+ ADD g, A 1110 1ggg 0110 1001 C Z C H 3
+ SUBB g, A 1110 1ggg 0110 1010 C Z C H 3
+ SUB g, A 1110 1ggg 0110 1011 C Z C H 3
+ AND g, A 1110 1ggg 0110 1100 Z Z - - 3
+ XOR g, A 1110 1ggg 0110 1101 Z Z - - 3
+ OR g, A 1110 1ggg 0110 1110 Z Z - - 3
+ CMP g, A 1110 1ggg 0110 1111 Z Z C H 3
*/
m_cycles = 3;
@@ -369,14 +369,14 @@ void tlcs870_device::do_ALUOP_g_n(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC g, n 1110 1ggg 0111 0000 nnnn nnnn C Z C H 3
- ADD g, n 1110 1ggg 0111 0001 nnnn nnnn C Z C H 3
- SUBB g, n 1110 1ggg 0111 0010 nnnn nnnn C Z C H 3
- SUB g, n 1110 1ggg 0111 0011 nnnn nnnn C Z C H 3
- AND g, n 1110 1ggg 0111 0100 nnnn nnnn Z Z - - 3
- XOR g, n 1110 1ggg 0111 0101 nnnn nnnn Z Z - - 3
- OR g, n 1110 1ggg 0111 0110 nnnn nnnn Z Z - - 3
- CMP g, n 1110 1ggg 0111 0111 nnnn nnnn Z Z C H 3
+ ADDC g, n 1110 1ggg 0111 0000 nnnn nnnn C Z C H 3
+ ADD g, n 1110 1ggg 0111 0001 nnnn nnnn C Z C H 3
+ SUBB g, n 1110 1ggg 0111 0010 nnnn nnnn C Z C H 3
+ SUB g, n 1110 1ggg 0111 0011 nnnn nnnn C Z C H 3
+ AND g, n 1110 1ggg 0111 0100 nnnn nnnn Z Z - - 3
+ XOR g, n 1110 1ggg 0111 0101 nnnn nnnn Z Z - - 3
+ OR g, n 1110 1ggg 0111 0110 nnnn nnnn Z Z - - 3
+ CMP g, n 1110 1ggg 0111 0111 nnnn nnnn Z Z C H 3
*/
m_cycles = 3;
@@ -400,14 +400,14 @@ void tlcs870_device::do_ALUOP_WA_gg(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC WA, gg 1110 10gg 0011 0000 C Z C U 4
- ADD WA, gg 1110 10gg 0011 0001 C Z C U 4
- SUBB WA, gg 1110 10gg 0011 0010 C Z C U 4
- SUB WA, gg 1110 10gg 0011 0011 C Z C U 4
- AND WA, gg 1110 10gg 0011 0100 Z Z - - 4
- XOR WA, gg 1110 10gg 0011 0101 Z Z - - 4
- OR WA, gg 1110 10gg 0011 0110 Z Z - - 4
- CMP WA, gg 1110 10gg 0011 0111 Z Z C U 4
+ ADDC WA, gg 1110 10gg 0011 0000 C Z C U 4
+ ADD WA, gg 1110 10gg 0011 0001 C Z C U 4
+ SUBB WA, gg 1110 10gg 0011 0010 C Z C U 4
+ SUB WA, gg 1110 10gg 0011 0011 C Z C U 4
+ AND WA, gg 1110 10gg 0011 0100 Z Z - - 4
+ XOR WA, gg 1110 10gg 0011 0101 Z Z - - 4
+ OR WA, gg 1110 10gg 0011 0110 Z Z - - 4
+ CMP WA, gg 1110 10gg 0011 0111 Z Z C U 4
*/
m_cycles = 4;
@@ -426,14 +426,14 @@ void tlcs870_device::do_ALUOP_gg_mn(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC gg, mn 1110 10gg 0011 1000 nnnn nnnn mmmm mmmm C Z C U 4
- ADD gg, mn 1110 10gg 0011 1001 nnnn nnnn mmmm mmmm C Z C U 4
- SUBB gg, mn 1110 10gg 0011 1010 nnnn nnnn mmmm mmmm C Z C U 4
- SUB gg, mn 1110 10gg 0011 1011 nnnn nnnn mmmm mmmm C Z C U 4
- AND gg, mn 1110 10gg 0011 1100 nnnn nnnn mmmm mmmm Z Z - - 4
- XOR gg, mn 1110 10gg 0011 1101 nnnn nnnn mmmm mmmm Z Z - - 4
- OR gg, mn 1110 10gg 0011 1110 nnnn nnnn mmmm mmmm Z Z - - 4
- CMP gg, mn 1110 10gg 0011 1111 nnnn nnnn mmmm mmmm Z Z C U 4
+ ADDC gg, mn 1110 10gg 0011 1000 nnnn nnnn mmmm mmmm C Z C U 4
+ ADD gg, mn 1110 10gg 0011 1001 nnnn nnnn mmmm mmmm C Z C U 4
+ SUBB gg, mn 1110 10gg 0011 1010 nnnn nnnn mmmm mmmm C Z C U 4
+ SUB gg, mn 1110 10gg 0011 1011 nnnn nnnn mmmm mmmm C Z C U 4
+ AND gg, mn 1110 10gg 0011 1100 nnnn nnnn mmmm mmmm Z Z - - 4
+ XOR gg, mn 1110 10gg 0011 1101 nnnn nnnn mmmm mmmm Z Z - - 4
+ OR gg, mn 1110 10gg 0011 1110 nnnn nnnn mmmm mmmm Z Z - - 4
+ CMP gg, mn 1110 10gg 0011 1111 nnnn nnnn mmmm mmmm Z Z C U 4
*/
m_cycles = 4;
@@ -459,8 +459,8 @@ void tlcs870_device::do_SET_inppbit(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SET (DE).g 1110 1ggg 1000 0010 Z * - - 5
- SET (HL).g 1110 1ggg 1000 0011 Z * - - 5
+ SET (DE).g 1110 1ggg 1000 0010 Z * - - 5
+ SET (HL).g 1110 1ggg 1000 0011 Z * - - 5
*/
m_cycles = 5;
@@ -489,8 +489,8 @@ void tlcs870_device::do_CLR_inppbit(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR (DE).g 1110 1ggg 1000 1010 Z * - - 5
- CLR (HL).g 1110 1ggg 1000 1011 Z * - - 5
+ CLR (DE).g 1110 1ggg 1000 1010 Z * - - 5
+ CLR (HL).g 1110 1ggg 1000 1011 Z * - - 5
*/
m_cycles = 5;
@@ -520,8 +520,8 @@ void tlcs870_device::do_CPL_inpp_indirectbit(const uint8_t opbyte0, const uint8_
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CPL (DE).g 1110 1ggg 1001 0010 Z * - - 5
- CPL (HL).g 1110 1ggg 1001 0011 Z * - - 5
+ CPL (DE).g 1110 1ggg 1001 0010 Z * - - 5
+ CPL (HL).g 1110 1ggg 1001 0011 Z * - - 5
*/
m_cycles = 5;
@@ -555,8 +555,8 @@ void tlcs870_device::do_LD_inpp_indirectbit_CF(const uint8_t opbyte0, const uint
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (DE).g, CF 1110 1ggg 1001 1010 1 - - - 5
- LD (HL).g, CF 1110 1ggg 1001 1011 1 - - - 5
+ LD (DE).g, CF 1110 1ggg 1001 1010 1 - - - 5
+ LD (HL).g, CF 1110 1ggg 1001 1011 1 - - - 5
*/
m_cycles = 5;
@@ -585,10 +585,10 @@ void tlcs870_device::do_LD_CF_inpp_indirectbit(const uint8_t opbyte0, const uint
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD CF, (DE).g 1110 1ggg 1001 1110 ~C - * - 4
- LD CF, (HL).g 1110 1ggg 1001 1111 ~C - * - 4
+ LD CF, (DE).g 1110 1ggg 1001 1110 ~C - * - 4
+ LD CF, (HL).g 1110 1ggg 1001 1111 ~C - * - 4
- aka aka TEST (pp).g
+ aka aka TEST (pp).g
*/
m_cycles = 4;
@@ -610,7 +610,7 @@ void tlcs870_device::do_SET_gbit(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SET g.b 1110 1ggg 0100 0bbb Z * - - 3
+ SET g.b 1110 1ggg 0100 0bbb Z * - - 3
*/
m_cycles = 3;
@@ -639,7 +639,7 @@ void tlcs870_device::do_CLR_gbit(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR g.b 1110 1ggg 0100 1bbb Z * - - 3
+ CLR g.b 1110 1ggg 0100 1bbb Z * - - 3
*/
m_cycles = 3;
@@ -668,7 +668,7 @@ void tlcs870_device::do_CPL_gbit(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CPL g.b 1110 1ggg 1100 0bbb Z * - - 3
+ CPL g.b 1110 1ggg 1100 0bbb Z * - - 3
*/
m_cycles = 3;
@@ -701,7 +701,7 @@ void tlcs870_device::do_LD_gbit_CF(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD g.b, CF 1110 1ggg 1100 1bbb 1 - - - 2
+ LD g.b, CF 1110 1ggg 1100 1bbb 1 - - - 2
*/
m_cycles = 2;
@@ -730,7 +730,7 @@ void tlcs870_device::do_XOR_CF_gbit(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- XOR CF, g.b 1110 1ggg 1101 0bbb ~C - * - 2
+ XOR CF, g.b 1110 1ggg 1101 0bbb ~C - * - 2
*/
m_cycles = 2;
@@ -776,9 +776,9 @@ void tlcs870_device::do_LD_CF_gbit(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD CF, g.b 1110 1ggg 1101 1bbb ~C - * - 2
+ LD CF, g.b 1110 1ggg 1101 1bbb ~C - * - 2
- aka TEST g.b
+ aka TEST g.b
*/
m_cycles = 2;
@@ -802,12 +802,12 @@ void tlcs870_device::do_MUL_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- MUL W, A not listed (redundant encoding?) ? ? ? ? ?
- MUL B, C 1110 1010 0000 0010 Z Z - - 8
- MUL D, E 1110 1010 0000 0010 Z Z - - 8
- MUL H, L 1110 1011 0000 0010 Z Z - - 8
+ MUL W, A not listed (redundant encoding?) ? ? ? ? ?
+ MUL B, C 1110 1010 0000 0010 Z Z - - 8
+ MUL D, E 1110 1010 0000 0010 Z Z - - 8
+ MUL H, L 1110 1011 0000 0010 Z Z - - 8
- aka MUL ggH, ggL (odd syntax, basically MUL gg)
+ aka MUL ggH, ggL (odd syntax, basically MUL gg)
*/
m_cycles = 8;
@@ -819,10 +819,10 @@ void tlcs870_device::do_DIV_gg_C(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DIV WA, C not listed (redundant encoding?) ? ? ? ? ?
- DIV BC, C not listed (illegal?) ? ? ? ? ?
- DIV DE, C 1110 1010 0000 0011 Z Z C - 8
- DIV HL, C 1110 1011 0000 0011 Z Z C - 8
+ DIV WA, C not listed (redundant encoding?) ? ? ? ? ?
+ DIV BC, C not listed (illegal?) ? ? ? ? ?
+ DIV DE, C 1110 1010 0000 0011 Z Z C - 8
+ DIV HL, C 1110 1011 0000 0011 Z Z C - 8
*/
m_cycles = 8;
@@ -834,7 +834,7 @@ void tlcs870_device::do_POP_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- POP gg 1110 10gg 0000 0110 - - - - 5
+ POP gg 1110 10gg 0000 0110 - - - - 5
*/
m_cycles = 5;
@@ -848,7 +848,7 @@ void tlcs870_device::do_PUSH_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- PUSH gg 1110 10gg 0000 0111 - - - - 4
+ PUSH gg 1110 10gg 0000 0111 - - - - 4
*/
m_cycles = 4;
@@ -863,7 +863,7 @@ void tlcs870_device::do_LD_SP_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD SP, gg 1110 10gg 1111 1010 1 - - - 3
+ LD SP, gg 1110 10gg 1111 1010 1 - - - 3
*/
m_cycles = 3;
@@ -875,7 +875,7 @@ void tlcs870_device::do_LD_gg_SP(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD gg, SP 1110 10gg 1111 1011 1 - - - 3
+ LD gg, SP 1110 10gg 1111 1011 1 - - - 3
*/
m_cycles = 3;
@@ -887,7 +887,7 @@ void tlcs870_device::do_LD_rr_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD rr, gg 1110 10gg 0001 00rr 1 - - - 2
+ LD rr, gg 1110 10gg 0001 00rr 1 - - - 2
*/
m_cycles = 2;
@@ -902,7 +902,7 @@ void tlcs870_device::do_XCH_rr_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- XCH rr, gg 1110 10gg 0001 01rr 1 - - - 3
+ XCH rr, gg 1110 10gg 0001 01rr 1 - - - 3
*/
m_cycles = 3;
@@ -920,7 +920,7 @@ void tlcs870_device::do_CALL_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CALL gg 1110 10gg 1111 1100 - - - - 6
+ CALL gg 1110 10gg 1111 1100 - - - - 6
*/
m_cycles = 6;
@@ -938,7 +938,7 @@ void tlcs870_device::do_JP_gg(const uint8_t opbyte0, const uint8_t opbyte1)
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JP gg 1110 10gg 1111 1110 1 - - - 3
+ JP gg 1110 10gg 1111 1110 1 - - - 3
*/
m_cycles = 3;
diff --git a/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp b/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp
index 6295d9c06b3..3f4103f7b4a 100644
--- a/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870_ops_src.cpp
@@ -6,19 +6,19 @@
(src) prefix ops (e0 to e7 subtable)
- (src) address depends on the first byte of the opcode
+ (src) address depends on the first byte of the opcode
- E0 (x)
- E1 (PC+A)
- E2 (DE)
- E3 (HL)
- E4 (HL+d)
- E5 (HL+C)
- E6 (HL+)
- E7 (-HL)
+ E0 (x)
+ E1 (PC+A)
+ E2 (DE)
+ E3 (HL)
+ E4 (HL+d)
+ E5 (HL+C)
+ E6 (HL+)
+ E7 (-HL)
- note, in cases where the address is an immediate value, not a register (x) and (HL+d) the
- immediate value is directly after the first byte of the opcode
+ note, in cases where the address is an immediate value, not a register (x) and (HL+d) the
+ immediate value is directly after the first byte of the opcode
*************************************************************************************************************/
@@ -109,16 +109,16 @@ void tlcs870_device::do_LD_rr_insrc(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD rr, (x) 1110 0000 xxxx xxxx 0001 01rr 1 - - - 5
- LD rr, (PC+A) 1110 0001 0001 01rr 1 - - - 6
- LD rr, (DE) 1110 0010 0001 01rr 1 - - - 4
- LD rr, (HL) 1110 0011 0001 01rr 1 - - - 4
- LD rr, (HL+d) 1110 0100 dddd dddd 0001 01rr 1 - - - 6
- LD rr, (HL+C) 1110 0101 0001 01rr 1 - - - 6
- LD rr, (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ?
- LD rr, (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ?
+ LD rr, (x) 1110 0000 xxxx xxxx 0001 01rr 1 - - - 5
+ LD rr, (PC+A) 1110 0001 0001 01rr 1 - - - 6
+ LD rr, (DE) 1110 0010 0001 01rr 1 - - - 4
+ LD rr, (HL) 1110 0011 0001 01rr 1 - - - 4
+ LD rr, (HL+d) 1110 0100 dddd dddd 0001 01rr 1 - - - 6
+ LD rr, (HL+C) 1110 0101 0001 01rr 1 - - - 6
+ LD rr, (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ?
+ LD rr, (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ?
- aka LD rr, (src)
+ aka LD rr, (src)
*/
m_cycles += 4;
@@ -135,16 +135,16 @@ void tlcs870_device::do_INC_insrc(const uint8_t opbyte0, const uint8_t opbyte1,
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- INC (x) not listed, redundant encoding? ? ? ? ? ?
- INC (PC+A) 1110 0001 0010 0000 C Z - - 6
- INC (DE) 1110 0010 0010 0000 C Z - - 4
- INC (HL) not listed, redundant encoding? ? ? ? ? ?
- INC (HL+d) 1110 0100 dddd dddd 0010 0000 C Z - - 6
- INC (HL+C) 1110 0101 0010 0000 C Z - - 6
- INC (HL+) 1110 0110 0010 0000 C Z - - 5
- INC (-HL) 1110 0111 0010 0000 C Z - - 5
+ INC (x) not listed, redundant encoding? ? ? ? ? ?
+ INC (PC+A) 1110 0001 0010 0000 C Z - - 6
+ INC (DE) 1110 0010 0010 0000 C Z - - 4
+ INC (HL) not listed, redundant encoding? ? ? ? ? ?
+ INC (HL+d) 1110 0100 dddd dddd 0010 0000 C Z - - 6
+ INC (HL+C) 1110 0101 0010 0000 C Z - - 6
+ INC (HL+) 1110 0110 0010 0000 C Z - - 5
+ INC (-HL) 1110 0111 0010 0000 C Z - - 5
- aka INC (src)
+ aka INC (src)
*/
m_cycles += 4;
@@ -169,16 +169,16 @@ void tlcs870_device::do_DEC_insrc(const uint8_t opbyte0, const uint8_t opbyte1,
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- DEC (x) not listed, redundant encoding? ? ? ? ? ?
- DEC (PC+A) 1110 0001 0010 1000 C Z - - 6
- DEC (DE) 1110 0010 0010 1000 C Z - - 4
- DEC (HL) not listed, redundant encoding? ? ? ? ? ?
- DEC (HL+d) 1110 0100 dddd dddd 0010 1000 C Z - - 6
- DEC (HL+C) 1110 0101 0010 1000 C Z - - 6
- DEC (HL+) 1110 0110 0010 1000 C Z - - 5
- DEC (-HL) 1110 0111 0010 1000 C Z - - 5
+ DEC (x) not listed, redundant encoding? ? ? ? ? ?
+ DEC (PC+A) 1110 0001 0010 1000 C Z - - 6
+ DEC (DE) 1110 0010 0010 1000 C Z - - 4
+ DEC (HL) not listed, redundant encoding? ? ? ? ? ?
+ DEC (HL+d) 1110 0100 dddd dddd 0010 1000 C Z - - 6
+ DEC (HL+C) 1110 0101 0010 1000 C Z - - 6
+ DEC (HL+) 1110 0110 0010 1000 C Z - - 5
+ DEC (-HL) 1110 0111 0010 1000 C Z - - 5
- aka DEC (src)
+ aka DEC (src)
*/
m_cycles += 4;
@@ -211,17 +211,17 @@ void tlcs870_device::do_ROLD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ROLD A, (x) 1110 0000 xxxx xxxx 0000 1000 1 0 0 0 8
- ROLD A, (PC+A) not listed, invalid? ? ? ? ? ?
- ROLD A, (DE) 1110 0010 0000 1000 1 0 0 0 7
- ROLD A, (HL) 1110 0011 0000 1000 1 0 0 0 7
- ROLD A, (HL+d) 1110 0100 dddd dddd 0000 1000 1 0 0 0 9
- ROLD A, (HL+C) 1110 0101 0000 1000 1 0 0 0 9
- ROLD A, (HL+) 1110 0110 0000 1000 1 0 0 0 8
- ROLD A, (-HL) 1110 0111 0000 1000 1 0 0 0 8
+ ROLD A, (x) 1110 0000 xxxx xxxx 0000 1000 1 0 0 0 8
+ ROLD A, (PC+A) not listed, invalid? ? ? ? ? ?
+ ROLD A, (DE) 1110 0010 0000 1000 1 0 0 0 7
+ ROLD A, (HL) 1110 0011 0000 1000 1 0 0 0 7
+ ROLD A, (HL+d) 1110 0100 dddd dddd 0000 1000 1 0 0 0 9
+ ROLD A, (HL+C) 1110 0101 0000 1000 1 0 0 0 9
+ ROLD A, (HL+) 1110 0110 0000 1000 1 0 0 0 8
+ ROLD A, (-HL) 1110 0111 0000 1000 1 0 0 0 8
- aka ROLD A,(src)
- 12-bit left rotation using lower 4 bits of REG_A and content of (src)
+ aka ROLD A,(src)
+ 12-bit left rotation using lower 4 bits of REG_A and content of (src)
*/
m_cycles += 7;
@@ -242,17 +242,17 @@ void tlcs870_device::do_RORD_A_insrc(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- RORD A, (x) 1110 0000 xxxx xxxx 0000 1001 1 0 0 0 8
- RORD A, (PC+A) not listed, invalid? ? ? ? ? ?
- RORD A, (DE) 1110 0010 0000 1001 1 0 0 0 7
- RORD A, (HL) 1110 0011 0000 1001 1 0 0 0 7
- RORD A, (HL+d) 1110 0100 dddd dddd 0000 1001 1 0 0 0 9
- RORD A, (HL+C) 1110 0101 0000 1001 1 0 0 0 9
- RORD A, (HL+) 1110 0110 0000 1001 1 0 0 0 8
- RORD A, (-HL) 1110 0111 0000 1001 1 0 0 0 8
+ RORD A, (x) 1110 0000 xxxx xxxx 0000 1001 1 0 0 0 8
+ RORD A, (PC+A) not listed, invalid? ? ? ? ? ?
+ RORD A, (DE) 1110 0010 0000 1001 1 0 0 0 7
+ RORD A, (HL) 1110 0011 0000 1001 1 0 0 0 7
+ RORD A, (HL+d) 1110 0100 dddd dddd 0000 1001 1 0 0 0 9
+ RORD A, (HL+C) 1110 0101 0000 1001 1 0 0 0 9
+ RORD A, (HL+) 1110 0110 0000 1001 1 0 0 0 8
+ RORD A, (-HL) 1110 0111 0000 1001 1 0 0 0 8
- aka RORD A,(src)
- 12-bit right rotation using lower 4 bits of REG_A and content of (src)
+ aka RORD A,(src)
+ 12-bit right rotation using lower 4 bits of REG_A and content of (src)
*/
m_cycles += 7;
@@ -275,16 +275,16 @@ void tlcs870_device::do_LD_inx_insrc(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x), (x) not listed, invalid? or redundant? ? ? ? ? ?
- LD (x), (PC+A) 1110 0001 0010 0110 xxxx xxxx 1 U - - 7
- LD (x), (DE) 1110 0010 0010 0110 xxxx xxxx 1 U - - 5
- LD (x), (HL) 1110 0011 0010 0110 xxxx xxxx 1 U - - 5
- LD (x), (HL+d) 1110 0100 dddd dddd 0010 0110 xxxx xxxx 1 U - - 7
- LD (x), (HL+C) 1110 0101 0010 0110 xxxx xxxx 1 U - - 7
- LD (x), (HL+) not listed, invalid? ? ? ? ? ?
- LD (x), (-HL) not listed, invalid? ? ? ? ? ?
+ LD (x), (x) not listed, invalid? or redundant? ? ? ? ? ?
+ LD (x), (PC+A) 1110 0001 0010 0110 xxxx xxxx 1 U - - 7
+ LD (x), (DE) 1110 0010 0010 0110 xxxx xxxx 1 U - - 5
+ LD (x), (HL) 1110 0011 0010 0110 xxxx xxxx 1 U - - 5
+ LD (x), (HL+d) 1110 0100 dddd dddd 0010 0110 xxxx xxxx 1 U - - 7
+ LD (x), (HL+C) 1110 0101 0010 0110 xxxx xxxx 1 U - - 7
+ LD (x), (HL+) not listed, invalid? ? ? ? ? ?
+ LD (x), (-HL) not listed, invalid? ? ? ? ? ?
- aka LD (x),(src)
+ aka LD (x),(src)
*/
m_cycles += 5;
@@ -300,16 +300,16 @@ void tlcs870_device::do_LD_inHL_insrc(const uint8_t opbyte0, const uint8_t opbyt
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (HL), (x) 1110 0000 xxxx xxxx 0010 0111 1 Z - - 5
- LD (HL), (PC+A) 1110 0001 0010 0111 1 Z - - 6
- LD (HL), (DE) 1110 0010 0010 0111 1 Z - - 4
- LD (HL), (HL) 1110 0011 0010 0111 1 Z - - 4
- LD (HL), (HL+d) 1110 0100 dddd dddd 0010 0111 1 Z - - 6
- LD (HL), (HL+C) 1110 0101 0010 0111 1 Z - - 6
- LD (HL), (HL+) not listed, invalid? ? ? ? ? ?
- LD (HL), (-HL) not listed, invalid? ? ? ? ? ?
+ LD (HL), (x) 1110 0000 xxxx xxxx 0010 0111 1 Z - - 5
+ LD (HL), (PC+A) 1110 0001 0010 0111 1 Z - - 6
+ LD (HL), (DE) 1110 0010 0010 0111 1 Z - - 4
+ LD (HL), (HL) 1110 0011 0010 0111 1 Z - - 4
+ LD (HL), (HL+d) 1110 0100 dddd dddd 0010 0111 1 Z - - 6
+ LD (HL), (HL+C) 1110 0101 0010 0111 1 Z - - 6
+ LD (HL), (HL+) not listed, invalid? ? ? ? ? ?
+ LD (HL), (-HL) not listed, invalid? ? ? ? ? ?
- aka LD (HL),(src)
+ aka LD (HL),(src)
*/
m_cycles += 4;
@@ -327,16 +327,16 @@ void tlcs870_device::do_LD_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1,
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD r, (x) 1110 0000 xxxx xxxx 0101 1rrr 1 Z - - 4
- LD r, (PC+A) 1110 0001 0101 1rrr 1 Z - - 5
- LD r, (DE) 1110 0010 0101 1rrr 1 Z - - 3
- LD r, (HL) 1110 0011 0101 1rrr 1 Z - - 3
- LD r, (HL+d) 1110 0100 dddd dddd 0101 1rrr 1 Z - - 5
- LD r, (HL+C) 1110 0101 0101 1rrr 1 Z - - 5
- LD r, (HL+) 1110 0110 0101 1rrr 1 Z - - 4 (invalid if r is H or L)
- LD r, (-HL) 1110 0111 0101 1rrr 1 Z - - 4
+ LD r, (x) 1110 0000 xxxx xxxx 0101 1rrr 1 Z - - 4
+ LD r, (PC+A) 1110 0001 0101 1rrr 1 Z - - 5
+ LD r, (DE) 1110 0010 0101 1rrr 1 Z - - 3
+ LD r, (HL) 1110 0011 0101 1rrr 1 Z - - 3
+ LD r, (HL+d) 1110 0100 dddd dddd 0101 1rrr 1 Z - - 5
+ LD r, (HL+C) 1110 0101 0101 1rrr 1 Z - - 5
+ LD r, (HL+) 1110 0110 0101 1rrr 1 Z - - 4 (invalid if r is H or L)
+ LD r, (-HL) 1110 0111 0101 1rrr 1 Z - - 4
- aka LD r, (src)
+ aka LD r, (src)
*/
m_cycles += 3;
@@ -354,16 +354,16 @@ void tlcs870_device::do_MCMP_insrc_n(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- MCMP (x), n 1110 0000 xxxx xxxx 0010 1111 nnnn nnnn Z Z C H 6
- MCMP (PC+A), n 1110 0001 0010 1111 nnnn nnnn Z Z C H 7
- MCMP (DE), n 1110 0010 0010 1111 nnnn nnnn Z Z C H 5
- MCMP (HL), n 1110 0011 0010 1111 nnnn nnnn Z Z C H 5
- MCMP (HL+d), n 1110 0100 dddd dddd 0010 1111 nnnn nnnn Z Z C H 7
- MCMP (HL+C), n 1110 0101 0010 1111 nnnn nnnn Z Z C H 7
- MCMP (HL+), n 1110 0110 0010 1111 nnnn nnnn Z Z C H 6
- MCMP (-HL), n 1110 0111 0010 1111 nnnn nnnn Z Z C H 6
+ MCMP (x), n 1110 0000 xxxx xxxx 0010 1111 nnnn nnnn Z Z C H 6
+ MCMP (PC+A), n 1110 0001 0010 1111 nnnn nnnn Z Z C H 7
+ MCMP (DE), n 1110 0010 0010 1111 nnnn nnnn Z Z C H 5
+ MCMP (HL), n 1110 0011 0010 1111 nnnn nnnn Z Z C H 5
+ MCMP (HL+d), n 1110 0100 dddd dddd 0010 1111 nnnn nnnn Z Z C H 7
+ MCMP (HL+C), n 1110 0101 0010 1111 nnnn nnnn Z Z C H 7
+ MCMP (HL+), n 1110 0110 0010 1111 nnnn nnnn Z Z C H 6
+ MCMP (-HL), n 1110 0111 0010 1111 nnnn nnnn Z Z C H 6
- aka MCMP (src), n
+ aka MCMP (src), n
*/
m_cycles += 5;
@@ -403,16 +403,16 @@ void tlcs870_device::do_XCH_r_insrc(const uint8_t opbyte0, const uint8_t opbyte1
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- XCH r, (x) 1110 0000 xxxx xxxx 1010 1rrr 1 Z - - 5
- XCH r, (PC+A) 1110 0001 1010 1rrr 1 Z - - 6
- XCH r, (DE) 1110 0010 1010 1rrr 1 Z - - 4
- XCH r, (HL) 1110 0011 1010 1rrr 1 Z - - 4
- XCH r, (HL+d) 1110 0100 dddd dddd 1010 1rrr 1 Z - - 6
- XCH r, (HL+C) 1110 0101 1010 1rrr 1 Z - - 6
- XCH r, (HL+) 1110 0110 1010 1rrr 1 Z - - 5 (invalid if r is H or L)
- XCH r, (-HL) 1110 0111 1010 1rrr 1 Z - - 5
+ XCH r, (x) 1110 0000 xxxx xxxx 1010 1rrr 1 Z - - 5
+ XCH r, (PC+A) 1110 0001 1010 1rrr 1 Z - - 6
+ XCH r, (DE) 1110 0010 1010 1rrr 1 Z - - 4
+ XCH r, (HL) 1110 0011 1010 1rrr 1 Z - - 4
+ XCH r, (HL+d) 1110 0100 dddd dddd 1010 1rrr 1 Z - - 6
+ XCH r, (HL+C) 1110 0101 1010 1rrr 1 Z - - 6
+ XCH r, (HL+) 1110 0110 1010 1rrr 1 Z - - 5 (invalid if r is H or L)
+ XCH r, (-HL) 1110 0111 1010 1rrr 1 Z - - 5
- aka XCH r,(src)
+ aka XCH r,(src)
*/
m_cycles += 4;
@@ -444,79 +444,79 @@ void tlcs870_device::do_ALUOP_insrc_inHL(const uint8_t opbyte0, const uint8_t op
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC (x), (HL) 1110 0000 xxxx xxxx 0110 0000 C Z C H 7
- ADDC (PC+A), (HL) 1110 0001 0110 0000 C Z C H 8
- ADDC (DE), (HL) 1110 0010 0110 0000 C Z C H 6
- ADDC (HL), (HL) 1110 0011 0110 0000 C Z C H 6
- ADDC (HL+d), (HL) 1110 0100 dddd dddd 0110 0000 C Z C H 8
- ADDC (HL+C), (HL) 1110 0101 0110 0000 C Z C H 8
- ADDC (HL+), (HL) not listed, invalid? ? ? ? ? ?
- ADDC (-HL), (HL) not listed, invalid? ? ? ? ? ?
-
- ADD (x), (HL) 1110 0000 xxxx xxxx 0110 0001 C Z C H 7
- ADD (PC+A), (HL) 1110 0001 0110 0001 C Z C H 8
- ADD (DE), (HL) 1110 0010 0110 0001 C Z C H 6
- ADD (HL), (HL) 1110 0011 0110 0001 C Z C H 6
- ADD (HL+d), (HL) 1110 0100 dddd dddd 0110 0001 C Z C H 8
- ADD (HL+C), (HL) 1110 0101 0110 0001 C Z C H 8
- ADD (HL+), (HL) not listed, invalid? ? ? ? ? ?
- ADD (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ ADDC (x), (HL) 1110 0000 xxxx xxxx 0110 0000 C Z C H 7
+ ADDC (PC+A), (HL) 1110 0001 0110 0000 C Z C H 8
+ ADDC (DE), (HL) 1110 0010 0110 0000 C Z C H 6
+ ADDC (HL), (HL) 1110 0011 0110 0000 C Z C H 6
+ ADDC (HL+d), (HL) 1110 0100 dddd dddd 0110 0000 C Z C H 8
+ ADDC (HL+C), (HL) 1110 0101 0110 0000 C Z C H 8
+ ADDC (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ ADDC (-HL), (HL) not listed, invalid? ? ? ? ? ?
- SUBB (x), (HL) 1110 0000 xxxx xxxx 0110 0010 C Z C H 7
- SUBB (PC+A), (HL) 1110 0001 0110 0010 C Z C H 8
- SUBB (DE), (HL) 1110 0010 0110 0010 C Z C H 6
- SUBB (HL), (HL) 1110 0011 0110 0010 C Z C H 6
- SUBB (HL+d), (HL) 1110 0100 dddd dddd 0110 0010 C Z C H 8
- SUBB (HL+C), (HL) 1110 0101 0110 0010 C Z C H 8
- SUBB (HL+), (HL) not listed, invalid? ? ? ? ? ?
- SUBB (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ ADD (x), (HL) 1110 0000 xxxx xxxx 0110 0001 C Z C H 7
+ ADD (PC+A), (HL) 1110 0001 0110 0001 C Z C H 8
+ ADD (DE), (HL) 1110 0010 0110 0001 C Z C H 6
+ ADD (HL), (HL) 1110 0011 0110 0001 C Z C H 6
+ ADD (HL+d), (HL) 1110 0100 dddd dddd 0110 0001 C Z C H 8
+ ADD (HL+C), (HL) 1110 0101 0110 0001 C Z C H 8
+ ADD (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ ADD (-HL), (HL) not listed, invalid? ? ? ? ? ?
- SUB (x), (HL) 1110 0000 xxxx xxxx 0110 0011 C Z C H 7
- SUB (PC+A), (HL) 1110 0001 0110 0011 C Z C H 8
- SUB (DE), (HL) 1110 0010 0110 0011 C Z C H 6
- SUB (HL), (HL) 1110 0011 0110 0011 C Z C H 6
- SUB (HL+d), (HL) 1110 0100 dddd dddd 0110 0011 C Z C H 8
- SUB (HL+C), (HL) 1110 0101 0110 0011 C Z C H 8
- SUB (HL+), (HL) not listed, invalid? ? ? ? ? ?
- SUB (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ SUBB (x), (HL) 1110 0000 xxxx xxxx 0110 0010 C Z C H 7
+ SUBB (PC+A), (HL) 1110 0001 0110 0010 C Z C H 8
+ SUBB (DE), (HL) 1110 0010 0110 0010 C Z C H 6
+ SUBB (HL), (HL) 1110 0011 0110 0010 C Z C H 6
+ SUBB (HL+d), (HL) 1110 0100 dddd dddd 0110 0010 C Z C H 8
+ SUBB (HL+C), (HL) 1110 0101 0110 0010 C Z C H 8
+ SUBB (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ SUBB (-HL), (HL) not listed, invalid? ? ? ? ? ?
- AND (x), (HL) 1110 0000 xxxx xxxx 0110 0100 Z Z - - 7
- AND (PC+A), (HL) 1110 0001 0110 0100 Z Z - - 8
- AND (DE), (HL) 1110 0010 0110 0100 Z Z - - 6
- AND (HL), (HL) 1110 0011 0110 0100 Z Z - - 6
- AND (HL+d), (HL) 1110 0100 dddd dddd 0110 0100 Z Z - - 8
- AND (HL+C), (HL) 1110 0101 0110 0100 Z Z - - 8
- AND (HL+), (HL) not listed, invalid? ? ? ? ? ?
- AND (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ SUB (x), (HL) 1110 0000 xxxx xxxx 0110 0011 C Z C H 7
+ SUB (PC+A), (HL) 1110 0001 0110 0011 C Z C H 8
+ SUB (DE), (HL) 1110 0010 0110 0011 C Z C H 6
+ SUB (HL), (HL) 1110 0011 0110 0011 C Z C H 6
+ SUB (HL+d), (HL) 1110 0100 dddd dddd 0110 0011 C Z C H 8
+ SUB (HL+C), (HL) 1110 0101 0110 0011 C Z C H 8
+ SUB (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ SUB (-HL), (HL) not listed, invalid? ? ? ? ? ?
- XOR (x), (HL) 1110 0000 xxxx xxxx 0110 0101 Z Z - - 7
- XOR (PC+A), (HL) 1110 0001 0110 0101 Z Z - - 8
- XOR (DE), (HL) 1110 0010 0110 0101 Z Z - - 6
- XOR (HL), (HL) 1110 0011 0110 0101 Z Z - - 6
- XOR (HL+d), (HL) 1110 0100 dddd dddd 0110 0101 Z Z - - 8
- XOR (HL+C), (HL) 1110 0101 0110 0101 Z Z - - 8
- XOR (HL+), (HL) not listed, invalid? ? ? ? ? ?
- XOR (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ AND (x), (HL) 1110 0000 xxxx xxxx 0110 0100 Z Z - - 7
+ AND (PC+A), (HL) 1110 0001 0110 0100 Z Z - - 8
+ AND (DE), (HL) 1110 0010 0110 0100 Z Z - - 6
+ AND (HL), (HL) 1110 0011 0110 0100 Z Z - - 6
+ AND (HL+d), (HL) 1110 0100 dddd dddd 0110 0100 Z Z - - 8
+ AND (HL+C), (HL) 1110 0101 0110 0100 Z Z - - 8
+ AND (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ AND (-HL), (HL) not listed, invalid? ? ? ? ? ?
- OR (x), (HL) 1110 0000 xxxx xxxx 0110 0110 Z Z - - 7
- OR (PC+A), (HL) 1110 0001 0110 0110 Z Z - - 8
- OR (DE), (HL) 1110 0010 0110 0110 Z Z - - 6
- OR (HL), (HL) 1110 0011 0110 0110 Z Z - - 6
- OR (HL+d), (HL) 1110 0100 dddd dddd 0110 0110 Z Z - - 8
- OR (HL+C), (HL) 1110 0101 0110 0110 Z Z - - 8
- OR (HL+), (HL) not listed, invalid? ? ? ? ? ?
- OR (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ XOR (x), (HL) 1110 0000 xxxx xxxx 0110 0101 Z Z - - 7
+ XOR (PC+A), (HL) 1110 0001 0110 0101 Z Z - - 8
+ XOR (DE), (HL) 1110 0010 0110 0101 Z Z - - 6
+ XOR (HL), (HL) 1110 0011 0110 0101 Z Z - - 6
+ XOR (HL+d), (HL) 1110 0100 dddd dddd 0110 0101 Z Z - - 8
+ XOR (HL+C), (HL) 1110 0101 0110 0101 Z Z - - 8
+ XOR (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ XOR (-HL), (HL) not listed, invalid? ? ? ? ? ?
- CMP (x), (HL) 1110 0000 xxxx xxxx 0110 0111 Z Z C H 6
- CMP (PC+A), (HL) 1110 0001 0110 0111 Z Z C H 7
- CMP (DE), (HL) 1110 0010 0110 0111 Z Z C H 5
- CMP (HL), (HL) 1110 0011 0110 0111 Z Z C H 5
- CMP (HL+d), (HL) 1110 0100 dddd dddd 0110 0111 Z Z C H 7
- CMP (HL+C), (HL) 1110 0101 0110 0111 Z Z C H 7
- CMP (HL+), (HL) not listed, invalid? ? ? ? ? ?
- CMP (-HL), (HL) not listed, invalid? ? ? ? ? ?
+ OR (x), (HL) 1110 0000 xxxx xxxx 0110 0110 Z Z - - 7
+ OR (PC+A), (HL) 1110 0001 0110 0110 Z Z - - 8
+ OR (DE), (HL) 1110 0010 0110 0110 Z Z - - 6
+ OR (HL), (HL) 1110 0011 0110 0110 Z Z - - 6
+ OR (HL+d), (HL) 1110 0100 dddd dddd 0110 0110 Z Z - - 8
+ OR (HL+C), (HL) 1110 0101 0110 0110 Z Z - - 8
+ OR (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ OR (-HL), (HL) not listed, invalid? ? ? ? ? ?
- aka (ALU OP) (src), (HL)
+ CMP (x), (HL) 1110 0000 xxxx xxxx 0110 0111 Z Z C H 6
+ CMP (PC+A), (HL) 1110 0001 0110 0111 Z Z C H 7
+ CMP (DE), (HL) 1110 0010 0110 0111 Z Z C H 5
+ CMP (HL), (HL) 1110 0011 0110 0111 Z Z C H 5
+ CMP (HL+d), (HL) 1110 0100 dddd dddd 0110 0111 Z Z C H 7
+ CMP (HL+C), (HL) 1110 0101 0110 0111 Z Z C H 7
+ CMP (HL+), (HL) not listed, invalid? ? ? ? ? ?
+ CMP (-HL), (HL) not listed, invalid? ? ? ? ? ?
+
+ aka (ALU OP) (src), (HL)
*/
m_cycles += 6;
@@ -541,89 +541,89 @@ void tlcs870_device::do_ALUOP_insrc_n(const uint8_t opbyte0, const uint8_t opbyt
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC (x), n 1110 0000 xxxx xxxx 0111 0000 nnnn nnnn C Z C H 6
- ADDC (PC+A), n 1110 0001 0111 0000 nnnn nnnn C Z C H 7
- ADDC (DE), n 1110 0010 0111 0000 nnnn nnnn C Z C H 5
- ADDC (HL), n 1110 0011 0111 0000 nnnn nnnn C Z C H 5
- ADDC (HL+d), n 1110 0100 dddd dddd 0111 0000 nnnn nnnn C Z C H 7
- ADDC (HL+C), n 1110 0101 0111 0000 nnnn nnnn C Z C H 7
- ADDC (HL+), n 1110 0110 0111 0000 nnnn nnnn C Z C H 6
- ADDC (-HL), n 1110 0111 0111 0000 nnnn nnnn C Z C H 6
+ ADDC (x), n 1110 0000 xxxx xxxx 0111 0000 nnnn nnnn C Z C H 6
+ ADDC (PC+A), n 1110 0001 0111 0000 nnnn nnnn C Z C H 7
+ ADDC (DE), n 1110 0010 0111 0000 nnnn nnnn C Z C H 5
+ ADDC (HL), n 1110 0011 0111 0000 nnnn nnnn C Z C H 5
+ ADDC (HL+d), n 1110 0100 dddd dddd 0111 0000 nnnn nnnn C Z C H 7
+ ADDC (HL+C), n 1110 0101 0111 0000 nnnn nnnn C Z C H 7
+ ADDC (HL+), n 1110 0110 0111 0000 nnnn nnnn C Z C H 6
+ ADDC (-HL), n 1110 0111 0111 0000 nnnn nnnn C Z C H 6
- ADD (x), n 1110 0000 xxxx xxxx 0111 0001 nnnn nnnn C Z C H 6
- ADD (PC+A), n 1110 0001 0111 0001 nnnn nnnn C Z C H 7
- ADD (DE), n 1110 0010 0111 0001 nnnn nnnn C Z C H 5
- ADD (HL), n 1110 0011 0111 0001 nnnn nnnn C Z C H 5
- ADD (HL+d), n 1110 0100 dddd dddd 0111 0001 nnnn nnnn C Z C H 7
- ADD (HL+C), n 1110 0101 0111 0001 nnnn nnnn C Z C H 7
- ADD (HL+), n 1110 0110 0111 0001 nnnn nnnn C Z C H 6
- ADD (-HL), n 1110 0111 0111 0001 nnnn nnnn C Z C H 6
+ ADD (x), n 1110 0000 xxxx xxxx 0111 0001 nnnn nnnn C Z C H 6
+ ADD (PC+A), n 1110 0001 0111 0001 nnnn nnnn C Z C H 7
+ ADD (DE), n 1110 0010 0111 0001 nnnn nnnn C Z C H 5
+ ADD (HL), n 1110 0011 0111 0001 nnnn nnnn C Z C H 5
+ ADD (HL+d), n 1110 0100 dddd dddd 0111 0001 nnnn nnnn C Z C H 7
+ ADD (HL+C), n 1110 0101 0111 0001 nnnn nnnn C Z C H 7
+ ADD (HL+), n 1110 0110 0111 0001 nnnn nnnn C Z C H 6
+ ADD (-HL), n 1110 0111 0111 0001 nnnn nnnn C Z C H 6
- SUBB (x), n 1110 0000 xxxx xxxx 0111 0010 nnnn nnnn C Z C H 6
- SUBB (PC+A), n 1110 0001 0111 0010 nnnn nnnn C Z C H 7
- SUBB (DE), n 1110 0010 0111 0010 nnnn nnnn C Z C H 5
- SUBB (HL), n 1110 0011 0111 0010 nnnn nnnn C Z C H 5
- SUBB (HL+d), n 1110 0100 dddd dddd 0111 0010 nnnn nnnn C Z C H 7
- SUBB (HL+C), n 1110 0101 0111 0010 nnnn nnnn C Z C H 7
- SUBB (HL+), n 1110 0110 0111 0010 nnnn nnnn C Z C H 6
- SUBB (-HL), n 1110 0111 0111 0010 nnnn nnnn C Z C H 6
+ SUBB (x), n 1110 0000 xxxx xxxx 0111 0010 nnnn nnnn C Z C H 6
+ SUBB (PC+A), n 1110 0001 0111 0010 nnnn nnnn C Z C H 7
+ SUBB (DE), n 1110 0010 0111 0010 nnnn nnnn C Z C H 5
+ SUBB (HL), n 1110 0011 0111 0010 nnnn nnnn C Z C H 5
+ SUBB (HL+d), n 1110 0100 dddd dddd 0111 0010 nnnn nnnn C Z C H 7
+ SUBB (HL+C), n 1110 0101 0111 0010 nnnn nnnn C Z C H 7
+ SUBB (HL+), n 1110 0110 0111 0010 nnnn nnnn C Z C H 6
+ SUBB (-HL), n 1110 0111 0111 0010 nnnn nnnn C Z C H 6
- SUB (x), n 1110 0000 xxxx xxxx 0111 0011 nnnn nnnn C Z C H 6
- SUB (PC+A), n 1110 0001 0111 0011 nnnn nnnn C Z C H 7
- SUB (DE), n 1110 0010 0111 0011 nnnn nnnn C Z C H 5
- SUB (HL), n 1110 0011 0111 0011 nnnn nnnn C Z C H 5
- SUB (HL+d), n 1110 0100 dddd dddd 0111 0011 nnnn nnnn C Z C H 7
- SUB (HL+C), n 1110 0101 0111 0011 nnnn nnnn C Z C H 7
- SUB (HL+), n 1110 0110 0111 0011 nnnn nnnn C Z C H 6
- SUB (-HL), n 1110 0111 0111 0011 nnnn nnnn C Z C H 6
+ SUB (x), n 1110 0000 xxxx xxxx 0111 0011 nnnn nnnn C Z C H 6
+ SUB (PC+A), n 1110 0001 0111 0011 nnnn nnnn C Z C H 7
+ SUB (DE), n 1110 0010 0111 0011 nnnn nnnn C Z C H 5
+ SUB (HL), n 1110 0011 0111 0011 nnnn nnnn C Z C H 5
+ SUB (HL+d), n 1110 0100 dddd dddd 0111 0011 nnnn nnnn C Z C H 7
+ SUB (HL+C), n 1110 0101 0111 0011 nnnn nnnn C Z C H 7
+ SUB (HL+), n 1110 0110 0111 0011 nnnn nnnn C Z C H 6
+ SUB (-HL), n 1110 0111 0111 0011 nnnn nnnn C Z C H 6
- AND (x), n 1110 0000 xxxx xxxx 0111 0100 nnnn nnnn Z Z - - 6
- AND (PC+A), n 1110 0001 0111 0100 nnnn nnnn Z Z - - 7
- AND (DE), n 1110 0010 0111 0100 nnnn nnnn Z Z - - 5
- AND (HL), n 1110 0011 0111 0100 nnnn nnnn Z Z - - 5
- AND (HL+d), n 1110 0100 dddd dddd 0111 0100 nnnn nnnn Z Z - - 7
- AND (HL+C), n 1110 0101 0111 0100 nnnn nnnn Z Z - - 7
- AND (HL+), n 1110 0110 0111 0100 nnnn nnnn Z Z - - 6
- AND (-HL), n 1110 0111 0111 0100 nnnn nnnn Z Z - - 6
+ AND (x), n 1110 0000 xxxx xxxx 0111 0100 nnnn nnnn Z Z - - 6
+ AND (PC+A), n 1110 0001 0111 0100 nnnn nnnn Z Z - - 7
+ AND (DE), n 1110 0010 0111 0100 nnnn nnnn Z Z - - 5
+ AND (HL), n 1110 0011 0111 0100 nnnn nnnn Z Z - - 5
+ AND (HL+d), n 1110 0100 dddd dddd 0111 0100 nnnn nnnn Z Z - - 7
+ AND (HL+C), n 1110 0101 0111 0100 nnnn nnnn Z Z - - 7
+ AND (HL+), n 1110 0110 0111 0100 nnnn nnnn Z Z - - 6
+ AND (-HL), n 1110 0111 0111 0100 nnnn nnnn Z Z - - 6
- XOR (x), n 1110 0000 xxxx xxxx 0111 0101 nnnn nnnn Z Z - - 6
- XOR (PC+A), n 1110 0001 0111 0101 nnnn nnnn Z Z - - 7
- XOR (DE), n 1110 0010 0111 0101 nnnn nnnn Z Z - - 5
- XOR (HL), n 1110 0011 0111 0101 nnnn nnnn Z Z - - 5
- XOR (HL+d), n 1110 0100 dddd dddd 0111 0101 nnnn nnnn Z Z - - 7
- XOR (HL+C), n 1110 0101 0111 0101 nnnn nnnn Z Z - - 7
- XOR (HL+), n 1110 0110 0111 0101 nnnn nnnn Z Z - - 6
- XOR (-HL), n 1110 0111 0111 0101 nnnn nnnn Z Z - - 6
+ XOR (x), n 1110 0000 xxxx xxxx 0111 0101 nnnn nnnn Z Z - - 6
+ XOR (PC+A), n 1110 0001 0111 0101 nnnn nnnn Z Z - - 7
+ XOR (DE), n 1110 0010 0111 0101 nnnn nnnn Z Z - - 5
+ XOR (HL), n 1110 0011 0111 0101 nnnn nnnn Z Z - - 5
+ XOR (HL+d), n 1110 0100 dddd dddd 0111 0101 nnnn nnnn Z Z - - 7
+ XOR (HL+C), n 1110 0101 0111 0101 nnnn nnnn Z Z - - 7
+ XOR (HL+), n 1110 0110 0111 0101 nnnn nnnn Z Z - - 6
+ XOR (-HL), n 1110 0111 0111 0101 nnnn nnnn Z Z - - 6
- OR (x), n 1110 0000 xxxx xxxx 0111 0110 nnnn nnnn Z Z - - 6
- OR (PC+A), n 1110 0001 0111 0110 nnnn nnnn Z Z - - 7
- OR (DE), n 1110 0010 0111 0110 nnnn nnnn Z Z - - 5
- OR (HL), n 1110 0011 0111 0110 nnnn nnnn Z Z - - 5
- OR (HL+d), n 1110 0100 dddd dddd 0111 0110 nnnn nnnn Z Z - - 7
- OR (HL+C), n 1110 0101 0111 0110 nnnn nnnn Z Z - - 7
- OR (HL+), n 1110 0110 0111 0110 nnnn nnnn Z Z - - 6
- OR (-HL), n 1110 0111 0111 0110 nnnn nnnn Z Z - - 6
+ OR (x), n 1110 0000 xxxx xxxx 0111 0110 nnnn nnnn Z Z - - 6
+ OR (PC+A), n 1110 0001 0111 0110 nnnn nnnn Z Z - - 7
+ OR (DE), n 1110 0010 0111 0110 nnnn nnnn Z Z - - 5
+ OR (HL), n 1110 0011 0111 0110 nnnn nnnn Z Z - - 5
+ OR (HL+d), n 1110 0100 dddd dddd 0111 0110 nnnn nnnn Z Z - - 7
+ OR (HL+C), n 1110 0101 0111 0110 nnnn nnnn Z Z - - 7
+ OR (HL+), n 1110 0110 0111 0110 nnnn nnnn Z Z - - 6
+ OR (-HL), n 1110 0111 0111 0110 nnnn nnnn Z Z - - 6
- CMP (x), n 1110 0000 xxxx xxxx 0111 0111 nnnn nnnn Z Z C H 5
- CMP (PC+A), n 1110 0001 0111 0111 nnnn nnnn Z Z C H 6
- CMP (DE), n 1110 0010 0111 0111 nnnn nnnn Z Z C H 4
- CMP (HL), n 1110 0011 0111 0111 nnnn nnnn Z Z C H 4
- CMP (HL+d), n 1110 0100 dddd dddd 0111 0111 nnnn nnnn Z Z C H 6
- CMP (HL+C), n 1110 0101 0111 0111 nnnn nnnn Z Z C H 6
- CMP (HL+), n 1110 0110 0111 0111 nnnn nnnn Z Z C H 5
- CMP (-HL), n 1110 0111 0111 0111 nnnn nnnn Z Z C H 5
+ CMP (x), n 1110 0000 xxxx xxxx 0111 0111 nnnn nnnn Z Z C H 5
+ CMP (PC+A), n 1110 0001 0111 0111 nnnn nnnn Z Z C H 6
+ CMP (DE), n 1110 0010 0111 0111 nnnn nnnn Z Z C H 4
+ CMP (HL), n 1110 0011 0111 0111 nnnn nnnn Z Z C H 4
+ CMP (HL+d), n 1110 0100 dddd dddd 0111 0111 nnnn nnnn Z Z C H 6
+ CMP (HL+C), n 1110 0101 0111 0111 nnnn nnnn Z Z C H 6
+ CMP (HL+), n 1110 0110 0111 0111 nnnn nnnn Z Z C H 5
+ CMP (-HL), n 1110 0111 0111 0111 nnnn nnnn Z Z C H 5
- aka (ALU OP) (src), n
+ aka (ALU OP) (src), n
*/
m_cycles += 5;
const uint8_t n = READ8();
const int aluop = (opbyte1 & 0x7);
-
+
if (aluop != 0x07)
m_read_input_port = 0; // reads output latch, not actual ports if accessing memory mapped ports
-
+
const uint8_t val = RM8(srcaddr);
const uint8_t result = do_alu_8bit(aluop, val, n);
@@ -639,79 +639,79 @@ void tlcs870_device::do_ALUOP_A_insrc(const uint8_t opbyte0, const uint8_t opbyt
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- ADDC A, (x) 1110 0000 xxxx xxxx 0111 1000 C Z C H 4
- ADDC A, (PC+A) 1110 0001 0111 1000 C Z C H 5
- ADDC A, (DE) 1110 0010 0111 1000 C Z C H 3
- ADDC A, (HL) 1110 0011 0111 1000 C Z C H 3
- ADDC A, (HL+d) 1110 0100 dddd dddd 0111 1000 C Z C H 5
- ADDC A, (HL+C) 1110 0101 0111 1000 C Z C H 5
- ADDC A, (HL+) 1110 0110 0111 1000 C Z C H 4
- ADDC A, (-HL) 1110 0111 0111 1000 C Z C H 4
+ ADDC A, (x) 1110 0000 xxxx xxxx 0111 1000 C Z C H 4
+ ADDC A, (PC+A) 1110 0001 0111 1000 C Z C H 5
+ ADDC A, (DE) 1110 0010 0111 1000 C Z C H 3
+ ADDC A, (HL) 1110 0011 0111 1000 C Z C H 3
+ ADDC A, (HL+d) 1110 0100 dddd dddd 0111 1000 C Z C H 5
+ ADDC A, (HL+C) 1110 0101 0111 1000 C Z C H 5
+ ADDC A, (HL+) 1110 0110 0111 1000 C Z C H 4
+ ADDC A, (-HL) 1110 0111 0111 1000 C Z C H 4
- ADD A, (x) 1110 0000 xxxx xxxx 0111 1001 C Z C H 4
- ADD A, (PC+A) 1110 0001 0111 1001 C Z C H 5
- ADD A, (DE) 1110 0010 0111 1001 C Z C H 3
- ADD A, (HL) 1110 0011 0111 1001 C Z C H 3
- ADD A, (HL+d) 1110 0100 dddd dddd 0111 1001 C Z C H 5
- ADD A, (HL+C) 1110 0101 0111 1001 C Z C H 5
- ADD A, (HL+) 1110 0110 0111 1001 C Z C H 4
- ADD A, (-HL) 1110 0111 0111 1001 C Z C H 4
+ ADD A, (x) 1110 0000 xxxx xxxx 0111 1001 C Z C H 4
+ ADD A, (PC+A) 1110 0001 0111 1001 C Z C H 5
+ ADD A, (DE) 1110 0010 0111 1001 C Z C H 3
+ ADD A, (HL) 1110 0011 0111 1001 C Z C H 3
+ ADD A, (HL+d) 1110 0100 dddd dddd 0111 1001 C Z C H 5
+ ADD A, (HL+C) 1110 0101 0111 1001 C Z C H 5
+ ADD A, (HL+) 1110 0110 0111 1001 C Z C H 4
+ ADD A, (-HL) 1110 0111 0111 1001 C Z C H 4
- SUBB A, (x) 1110 0000 xxxx xxxx 0111 1010 C Z C H 4
- SUBB A, (PC+A) 1110 0001 0111 1010 C Z C H 5
- SUBB A, (DE) 1110 0010 0111 1010 C Z C H 3
- SUBB A, (HL) 1110 0011 0111 1010 C Z C H 3
- SUBB A, (HL+d) 1110 0100 dddd dddd 0111 1010 C Z C H 5
- SUBB A, (HL+C) 1110 0101 0111 1010 C Z C H 5
- SUBB A, (HL+) 1110 0110 0111 1010 C Z C H 4
- SUBB A, (-HL) 1110 0111 0111 1010 C Z C H 4
+ SUBB A, (x) 1110 0000 xxxx xxxx 0111 1010 C Z C H 4
+ SUBB A, (PC+A) 1110 0001 0111 1010 C Z C H 5
+ SUBB A, (DE) 1110 0010 0111 1010 C Z C H 3
+ SUBB A, (HL) 1110 0011 0111 1010 C Z C H 3
+ SUBB A, (HL+d) 1110 0100 dddd dddd 0111 1010 C Z C H 5
+ SUBB A, (HL+C) 1110 0101 0111 1010 C Z C H 5
+ SUBB A, (HL+) 1110 0110 0111 1010 C Z C H 4
+ SUBB A, (-HL) 1110 0111 0111 1010 C Z C H 4
- SUB A, (x) 1110 0000 xxxx xxxx 0111 1011 C Z C H 4
- SUB A, (PC+A) 1110 0001 0111 1011 C Z C H 5
- SUB A, (DE) 1110 0010 0111 1011 C Z C H 3
- SUB A, (HL) 1110 0011 0111 1011 C Z C H 3
- SUB A, (HL+d) 1110 0100 dddd dddd 0111 1011 C Z C H 5
- SUB A, (HL+C) 1110 0101 0111 1011 C Z C H 5
- SUB A, (HL+) 1110 0110 0111 1011 C Z C H 4
- SUB A, (-HL) 1110 0111 0111 1011 C Z C H 4
+ SUB A, (x) 1110 0000 xxxx xxxx 0111 1011 C Z C H 4
+ SUB A, (PC+A) 1110 0001 0111 1011 C Z C H 5
+ SUB A, (DE) 1110 0010 0111 1011 C Z C H 3
+ SUB A, (HL) 1110 0011 0111 1011 C Z C H 3
+ SUB A, (HL+d) 1110 0100 dddd dddd 0111 1011 C Z C H 5
+ SUB A, (HL+C) 1110 0101 0111 1011 C Z C H 5
+ SUB A, (HL+) 1110 0110 0111 1011 C Z C H 4
+ SUB A, (-HL) 1110 0111 0111 1011 C Z C H 4
- AND A, (x) 1110 0000 xxxx xxxx 0111 1100 Z Z - - 4
- AND A, (PC+A) 1110 0001 0111 1100 Z Z - - 5
- AND A, (DE) 1110 0010 0111 1100 Z Z - - 3
- AND A, (HL) 1110 0011 0111 1100 Z Z - - 3
- AND A, (HL+d) 1110 0100 dddd dddd 0111 1100 Z Z - - 5
- AND A, (HL+C) 1110 0101 0111 1100 Z Z - - 5
- AND A, (HL+) 1110 0110 0111 1100 Z Z - - 4
- AND A, (-HL) 1110 0111 0111 1100 Z Z - - 4
+ AND A, (x) 1110 0000 xxxx xxxx 0111 1100 Z Z - - 4
+ AND A, (PC+A) 1110 0001 0111 1100 Z Z - - 5
+ AND A, (DE) 1110 0010 0111 1100 Z Z - - 3
+ AND A, (HL) 1110 0011 0111 1100 Z Z - - 3
+ AND A, (HL+d) 1110 0100 dddd dddd 0111 1100 Z Z - - 5
+ AND A, (HL+C) 1110 0101 0111 1100 Z Z - - 5
+ AND A, (HL+) 1110 0110 0111 1100 Z Z - - 4
+ AND A, (-HL) 1110 0111 0111 1100 Z Z - - 4
- XOR A, (x) 1110 0000 xxxx xxxx 0111 1101 Z Z - - 4
- XOR A, (PC+A) 1110 0001 0111 1101 Z Z - - 5
- XOR A, (DE) 1110 0010 0111 1101 Z Z - - 3
- XOR A, (HL) 1110 0011 0111 1101 Z Z - - 3
- XOR A, (HL+d) 1110 0100 dddd dddd 0111 1101 Z Z - - 5
- XOR A, (HL+C) 1110 0101 0111 1101 Z Z - - 5
- XOR A, (HL+) 1110 0110 0111 1101 Z Z - - 4
- XOR A, (-HL) 1110 0111 0111 1101 Z Z - - 4
+ XOR A, (x) 1110 0000 xxxx xxxx 0111 1101 Z Z - - 4
+ XOR A, (PC+A) 1110 0001 0111 1101 Z Z - - 5
+ XOR A, (DE) 1110 0010 0111 1101 Z Z - - 3
+ XOR A, (HL) 1110 0011 0111 1101 Z Z - - 3
+ XOR A, (HL+d) 1110 0100 dddd dddd 0111 1101 Z Z - - 5
+ XOR A, (HL+C) 1110 0101 0111 1101 Z Z - - 5
+ XOR A, (HL+) 1110 0110 0111 1101 Z Z - - 4
+ XOR A, (-HL) 1110 0111 0111 1101 Z Z - - 4
- OR A, (x) 1110 0000 xxxx xxxx 0111 1110 Z Z - - 4
- OR A, (PC+A) 1110 0001 0111 1110 Z Z - - 5
- OR A, (DE) 1110 0010 0111 1110 Z Z - - 3
- OR A, (HL) 1110 0011 0111 1110 Z Z - - 3
- OR A, (HL+d) 1110 0100 dddd dddd 0111 1110 Z Z - - 5
- OR A, (HL+C) 1110 0101 0111 1110 Z Z - - 5
- OR A, (HL+) 1110 0110 0111 1110 Z Z - - 4
- OR A, (-HL) 1110 0111 0111 1110 Z Z - - 4
+ OR A, (x) 1110 0000 xxxx xxxx 0111 1110 Z Z - - 4
+ OR A, (PC+A) 1110 0001 0111 1110 Z Z - - 5
+ OR A, (DE) 1110 0010 0111 1110 Z Z - - 3
+ OR A, (HL) 1110 0011 0111 1110 Z Z - - 3
+ OR A, (HL+d) 1110 0100 dddd dddd 0111 1110 Z Z - - 5
+ OR A, (HL+C) 1110 0101 0111 1110 Z Z - - 5
+ OR A, (HL+) 1110 0110 0111 1110 Z Z - - 4
+ OR A, (-HL) 1110 0111 0111 1110 Z Z - - 4
- CMP A, (x) 1110 0000 xxxx xxxx 0111 1111 Z Z C H 4
- CMP A, (PC+A) 1110 0001 0111 1111 Z Z C H 5
- CMP A, (DE) 1110 0010 0111 1111 Z Z C H 3
- CMP A, (HL) 1110 0011 0111 1111 Z Z C H 3
- CMP A, (HL+d) 1110 0100 dddd dddd 0111 1111 Z Z C H 5
- CMP A, (HL+C) 1110 0101 0111 1111 Z Z C H 5
- CMP A, (HL+) 1110 0110 0111 1111 Z Z C H 4
- CMP A, (-HL) 1110 0111 0111 1111 Z Z C H 4
+ CMP A, (x) 1110 0000 xxxx xxxx 0111 1111 Z Z C H 4
+ CMP A, (PC+A) 1110 0001 0111 1111 Z Z C H 5
+ CMP A, (DE) 1110 0010 0111 1111 Z Z C H 3
+ CMP A, (HL) 1110 0011 0111 1111 Z Z C H 3
+ CMP A, (HL+d) 1110 0100 dddd dddd 0111 1111 Z Z C H 5
+ CMP A, (HL+C) 1110 0101 0111 1111 Z Z C H 5
+ CMP A, (HL+) 1110 0110 0111 1111 Z Z C H 4
+ CMP A, (-HL) 1110 0111 0111 1111 Z Z C H 4
- aka (ALU OP) A, (src)
+ aka (ALU OP) A, (src)
*/
m_cycles += 3;
@@ -735,16 +735,16 @@ void tlcs870_device::do_CALL_insrc(const uint8_t opbyte0, const uint8_t opbyte1,
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CALL (x) 1110 0000 xxxx xxxx 1111 1100 - - - - 9
- CALL (PC+A) 1110 0001 1111 1100 - - - - 10
- CALL (DE) 1110 0010 1111 1100 - - - - 8
- CALL (HL) 1110 0011 1111 1100 - - - - 8
- CALL (HL+d) 1110 0100 dddd dddd 1111 1100 - - - - 10
- CALL (HL+C) 1110 0101 1111 1100 - - - - 10
- CALL (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ?
- CALL (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ?
+ CALL (x) 1110 0000 xxxx xxxx 1111 1100 - - - - 9
+ CALL (PC+A) 1110 0001 1111 1100 - - - - 10
+ CALL (DE) 1110 0010 1111 1100 - - - - 8
+ CALL (HL) 1110 0011 1111 1100 - - - - 8
+ CALL (HL+d) 1110 0100 dddd dddd 1111 1100 - - - - 10
+ CALL (HL+C) 1110 0101 1111 1100 - - - - 10
+ CALL (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ?
+ CALL (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ?
- aka CALL (src)
+ aka CALL (src)
*/
m_cycles += 8;
@@ -762,16 +762,16 @@ void tlcs870_device::do_JP_insrc(const uint8_t opbyte0, const uint8_t opbyte1, c
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- JP (x) 1110 0000 xxxx xxxx 1111 1110 1 - - - 6
- JP (PC+A) 1110 0001 1111 1110 1 - - - 7
- JP (DE) 1110 0010 1111 1110 1 - - - 5
- JP (HL) 1110 0011 1111 1110 1 - - - 5
- JP (HL+d) 1110 0100 dddd dddd 1111 1110 1 - - - 7
- JP (HL+C) 1110 0101 1111 1110 1 - - - 7
- JP (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ?
- JP (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ?
+ JP (x) 1110 0000 xxxx xxxx 1111 1110 1 - - - 6
+ JP (PC+A) 1110 0001 1111 1110 1 - - - 7
+ JP (DE) 1110 0010 1111 1110 1 - - - 5
+ JP (HL) 1110 0011 1111 1110 1 - - - 5
+ JP (HL+d) 1110 0100 dddd dddd 1111 1110 1 - - - 7
+ JP (HL+C) 1110 0101 1111 1110 1 - - - 7
+ JP (HL+) not listed, invalid due to 16-bit op? ? ? ? ? ?
+ JP (-HL) not listed, invalid due to 16-bit op? ? ? ? ? ?
- aka JP (src)
+ aka JP (src)
*/
m_cycles += 5;
@@ -788,16 +788,16 @@ void tlcs870_device::do_XOR_CF_insrcbit(const uint8_t opbyte0, const uint8_t opb
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- XOR CF, (x).b 1110 0000 xxxx xxxx 1101 0bbb ~C - * - 4
- XOR CF, (PC+A).b 1110 0001 1101 0bbb ~C - * - 5
- XOR CF, (DE).b 1110 0010 1101 0bbb ~C - * - 3
- XOR CF, (HL).b 1110 0011 1101 0bbb ~C - * - 3
- XOR CF, (HL+d).b 1110 0100 dddd dddd 1101 0bbb ~C - * - 5
- XOR CF, (HL+C).b 1110 0101 1101 0bbb ~C - * - 5
- XOR CF, (HL+).b 1110 0110 1101 0bbb ~C - * - 4
- XOR CF, (-HL).b 1110 0111 1101 0bbb ~C - * - 4
+ XOR CF, (x).b 1110 0000 xxxx xxxx 1101 0bbb ~C - * - 4
+ XOR CF, (PC+A).b 1110 0001 1101 0bbb ~C - * - 5
+ XOR CF, (DE).b 1110 0010 1101 0bbb ~C - * - 3
+ XOR CF, (HL).b 1110 0011 1101 0bbb ~C - * - 3
+ XOR CF, (HL+d).b 1110 0100 dddd dddd 1101 0bbb ~C - * - 5
+ XOR CF, (HL+C).b 1110 0101 1101 0bbb ~C - * - 5
+ XOR CF, (HL+).b 1110 0110 1101 0bbb ~C - * - 4
+ XOR CF, (-HL).b 1110 0111 1101 0bbb ~C - * - 4
- aka XOR CF,(src).b
+ aka XOR CF,(src).b
*/
m_cycles += 3;
@@ -843,16 +843,16 @@ void tlcs870_device::do_LD_insrcbit_CF(const uint8_t opbyte0, const uint8_t opby
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD (x).b, CF 1110 0000 xxxx xxxx 1100 1bbb 1 - - - 5
- LD (PC+A).b, CF 1110 0001 1100 1bbb 1 - - - 6
- LD (DE).b, CF 1110 0010 1100 1bbb 1 - - - 4
- LD (HL).b, CF 1110 0011 1100 1bbb 1 - - - 4
- LD (HL+d).b, CF 1110 0100 dddd dddd 1100 1bbb 1 - - - 6
- LD (HL+C).b, CF 1110 0101 1100 1bbb 1 - - - 6
- LD (HL+).b, CF 1110 0110 1100 1bbb 1 - - - 5
- LD (-HL).b, CF 1110 0111 1100 1bbb 1 - - - 5
+ LD (x).b, CF 1110 0000 xxxx xxxx 1100 1bbb 1 - - - 5
+ LD (PC+A).b, CF 1110 0001 1100 1bbb 1 - - - 6
+ LD (DE).b, CF 1110 0010 1100 1bbb 1 - - - 4
+ LD (HL).b, CF 1110 0011 1100 1bbb 1 - - - 4
+ LD (HL+d).b, CF 1110 0100 dddd dddd 1100 1bbb 1 - - - 6
+ LD (HL+C).b, CF 1110 0101 1100 1bbb 1 - - - 6
+ LD (HL+).b, CF 1110 0110 1100 1bbb 1 - - - 5
+ LD (-HL).b, CF 1110 0111 1100 1bbb 1 - - - 5
- aka LD (src).b,CF
+ aka LD (src).b,CF
*/
m_cycles += 4;
@@ -881,16 +881,16 @@ void tlcs870_device::do_CPL_insrcbit(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CPL (x).b 1110 0000 xxxx xxxx 1100 0bbb Z * - - 5
- CPL (PC+A).b 1110 0001 1100 0bbb Z * - - 6
- CPL (DE).b 1110 0010 1100 0bbb Z * - - 4
- CPL (HL).b 1110 0011 1100 0bbb Z * - - 4
- CPL (HL+d).b 1110 0100 dddd dddd 1100 0bbb Z * - - 6
- CPL (HL+C).b 1110 0101 1100 0bbb Z * - - 6
- CPL (HL+).b 1110 0110 1100 0bbb Z * - - 5
- CPL (-HL).b 1110 0111 1100 0bbb Z * - - 5
+ CPL (x).b 1110 0000 xxxx xxxx 1100 0bbb Z * - - 5
+ CPL (PC+A).b 1110 0001 1100 0bbb Z * - - 6
+ CPL (DE).b 1110 0010 1100 0bbb Z * - - 4
+ CPL (HL).b 1110 0011 1100 0bbb Z * - - 4
+ CPL (HL+d).b 1110 0100 dddd dddd 1100 0bbb Z * - - 6
+ CPL (HL+C).b 1110 0101 1100 0bbb Z * - - 6
+ CPL (HL+).b 1110 0110 1100 0bbb Z * - - 5
+ CPL (-HL).b 1110 0111 1100 0bbb Z * - - 5
- aka CPL (src).b
+ aka CPL (src).b
*/
m_cycles += 4;
@@ -924,16 +924,16 @@ void tlcs870_device::do_LD_CF_insrcbit(const uint8_t opbyte0, const uint8_t opby
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- LD CF, (x).b 1110 0000 xxxx xxxx 1101 1bbb ~C - * - 4
- LD CF, (PC+A).b 1110 0001 1101 1bbb ~C - * - 5
- LD CF, (DE).b 1110 0010 1101 1bbb ~C - * - 3
- LD CF, (HL).b 1110 0011 1101 1bbb ~C - * - 3
- LD CF, (HL+d).b 1110 0100 dddd dddd 1101 1bbb ~C - * - 5
- LD CF, (HL+C).b 1110 0101 1101 1bbb ~C - * - 5
- LD CF, (HL+).b 1110 0110 1101 1bbb ~C - * - 4
- LD CF, (-HL).b 1110 0111 1101 1bbb ~C - * - 4
+ LD CF, (x).b 1110 0000 xxxx xxxx 1101 1bbb ~C - * - 4
+ LD CF, (PC+A).b 1110 0001 1101 1bbb ~C - * - 5
+ LD CF, (DE).b 1110 0010 1101 1bbb ~C - * - 3
+ LD CF, (HL).b 1110 0011 1101 1bbb ~C - * - 3
+ LD CF, (HL+d).b 1110 0100 dddd dddd 1101 1bbb ~C - * - 5
+ LD CF, (HL+C).b 1110 0101 1101 1bbb ~C - * - 5
+ LD CF, (HL+).b 1110 0110 1101 1bbb ~C - * - 4
+ LD CF, (-HL).b 1110 0111 1101 1bbb ~C - * - 4
- aka LD CF,(src).b or TEST (src).b
+ aka LD CF,(src).b or TEST (src).b
*/
m_cycles += 3;
@@ -953,16 +953,16 @@ void tlcs870_device::do_SET_insrcbit(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- SET (x).b 1110 0000 xxxx xxxx 0100 0bbb Z * - - 5
- SET (PC+A).b 1110 0001 0100 0bbb Z * - - 6
- SET (DE).b 1110 0010 0100 0bbb Z * - - 4
- SET (HL).b 1110 0011 0100 0bbb Z * - - 4
- SET (HL+d).b 1110 0100 dddd dddd 0100 0bbb Z * - - 6
- SET (HL+C).b 1110 0101 0100 0bbb Z * - - 6
- SET (HL+).b 1110 0110 0100 0bbb Z * - - 5
- SET (-HL).b 1110 0111 0100 0bbb Z * - - 5
+ SET (x).b 1110 0000 xxxx xxxx 0100 0bbb Z * - - 5
+ SET (PC+A).b 1110 0001 0100 0bbb Z * - - 6
+ SET (DE).b 1110 0010 0100 0bbb Z * - - 4
+ SET (HL).b 1110 0011 0100 0bbb Z * - - 4
+ SET (HL+d).b 1110 0100 dddd dddd 0100 0bbb Z * - - 6
+ SET (HL+C).b 1110 0101 0100 0bbb Z * - - 6
+ SET (HL+).b 1110 0110 0100 0bbb Z * - - 5
+ SET (-HL).b 1110 0111 0100 0bbb Z * - - 5
- aka SET (src).b
+ aka SET (src).b
*/
m_cycles += 4;
@@ -992,16 +992,16 @@ void tlcs870_device::do_CLR_insrcbit(const uint8_t opbyte0, const uint8_t opbyte
{
/*
OP (opbyte0) (immval0) (opbyte1) (immval1) (immval2) JF ZF CF HF cycles
- CLR (x).b 1110 0000 xxxx xxxx 0100 1bbb Z * - - 5
- CLR (PC+A).b 1110 0001 0100 1bbb Z * - - 6
- CLR (DE).b 1110 0010 0100 1bbb Z * - - 4
- CLR (HL).b 1110 0011 0100 1bbb Z * - - 4
- CLR (HL+d).b 1110 0100 dddd dddd 0100 1bbb Z * - - 6
- CLR (HL+C).b 1110 0101 0100 1bbb Z * - - 6
- CLR (HL+).b 1110 0110 0100 1bbb Z * - - 5
- CLR (-HL).b 1110 0111 0100 1bbb Z * - - 5
+ CLR (x).b 1110 0000 xxxx xxxx 0100 1bbb Z * - - 5
+ CLR (PC+A).b 1110 0001 0100 1bbb Z * - - 6
+ CLR (DE).b 1110 0010 0100 1bbb Z * - - 4
+ CLR (HL).b 1110 0011 0100 1bbb Z * - - 4
+ CLR (HL+d).b 1110 0100 dddd dddd 0100 1bbb Z * - - 6
+ CLR (HL+C).b 1110 0101 0100 1bbb Z * - - 6
+ CLR (HL+).b 1110 0110 0100 1bbb Z * - - 5
+ CLR (-HL).b 1110 0111 0100 1bbb Z * - - 5
- aka CLR (src).b
+ aka CLR (src).b
*/
m_cycles += 4;
diff --git a/src/devices/cpu/tlcs870/tlcs870d.cpp b/src/devices/cpu/tlcs870/tlcs870d.cpp
index 50b7b12f05d..7900e764158 100644
--- a/src/devices/cpu/tlcs870/tlcs870d.cpp
+++ b/src/devices/cpu/tlcs870/tlcs870d.cpp
@@ -1469,7 +1469,7 @@ void tlcs870_disassembler::decode_register_prefix(uint8_t b0)
case 0xae:
case 0xaf:
// XCH r,g
- m_op = XCH;
+ m_op = XCH;
//m_flagsaffected |= FLAG_J | FLAG_Z;
diff --git a/src/devices/cpu/tms57002/tms57002.cpp b/src/devices/cpu/tms57002/tms57002.cpp
index 569f0b83a86..01ec9364e63 100644
--- a/src/devices/cpu/tms57002/tms57002.cpp
+++ b/src/devices/cpu/tms57002/tms57002.cpp
@@ -637,7 +637,7 @@ uint32_t tms57002_device::get_cmem(uint8_t addr)
cmem[addr] = update[update_counter_tail];
update_counter_tail = (update_counter_tail + 1) & 0x0f;
update_empty();
-
+
if(update_counter_head == update_counter_tail)
sti &= ~S_UPDATE;
@@ -794,7 +794,7 @@ void tms57002_device::execute_run()
else
xm_step_write();
}
-
+
macc_read = macc_write;
macc_write = macc;
diff --git a/src/devices/cpu/tms57002/tms57002.h b/src/devices/cpu/tms57002/tms57002.h
index 754d61bbeb1..28e57dc7969 100644
--- a/src/devices/cpu/tms57002/tms57002.h
+++ b/src/devices/cpu/tms57002/tms57002.h
@@ -141,10 +141,10 @@ private:
uint32_t xm_adr;
uint8_t host[4], hidx, allow_update;
-
+
uint32_t update[16];
uint8_t update_counter_head, update_counter_tail;
-
+
cd cache;
devcb_write_line m_dready_callback;
diff --git a/src/devices/cpu/tms57002/tmsinstr.lst b/src/devices/cpu/tms57002/tmsinstr.lst
index d73d2690f41..8ecd850a76f 100644
--- a/src/devices/cpu/tms57002/tmsinstr.lst
+++ b/src/devices/cpu/tms57002/tmsinstr.lst
@@ -545,7 +545,7 @@ zacc 1 10 1 n
zmac 1 30 1 n
zmac
-
+
raom 2b 3c 1 n f
raom
/* Undocumented instruction, reset ALU saturation flag */
diff --git a/src/devices/cpu/z180/z180.cpp b/src/devices/cpu/z180/z180.cpp
index 24ad1c3919d..b9b3c0fe418 100644
--- a/src/devices/cpu/z180/z180.cpp
+++ b/src/devices/cpu/z180/z180.cpp
@@ -364,7 +364,7 @@ bool z180_device::get_tend1()
#define Z180_CNTR_RESET 0x07
#define Z180_CNTR_RMASK 0xff
-#define Z180_CNTR_WMASK 0x4f /* Original: 0x7f - Modified: 0x4f - Inhibits setting up TI & RI flags due to the lack of CSIO implementation */
+#define Z180_CNTR_WMASK 0x4f /* Original: 0x7f - Modified: 0x4f - Inhibits setting up TI & RI flags due to the lack of CSIO implementation */
/* 0b CSI/O transmit/receive register */
#define Z180_TRDR_RESET 0x00
@@ -2390,7 +2390,7 @@ void z180_device::handle_io_timers(int cycles)
void z180_device::execute_run()
{
int curcycles;
-
+
/* check for NMIs on the way in; they can only be set externally */
/* via timers, and can't be dynamically enabled, so it is safe */
/* to just check here */
@@ -2441,7 +2441,7 @@ again:
if (!m_HALT)
{
m_R++;
- IO_FRC++; /* Added FRC counting, not implemented yet */
+ IO_FRC++; /* Added FRC counting, not implemented yet */
m_extra_cycles = 0;
curcycles = exec_op(ROP());
curcycles += m_extra_cycles;
@@ -2500,7 +2500,7 @@ again:
if (!m_HALT)
{
m_R++;
- IO_FRC++; /* Added FRC counting, not implemented yet */
+ IO_FRC++; /* Added FRC counting, not implemented yet */
m_extra_cycles = 0;
curcycles = exec_op(ROP());
curcycles += m_extra_cycles;
diff --git a/src/devices/machine/mb8421.cpp b/src/devices/machine/mb8421.cpp
index ce10f754d5e..a5b08f5ea90 100644
--- a/src/devices/machine/mb8421.cpp
+++ b/src/devices/machine/mb8421.cpp
@@ -9,7 +9,7 @@
MB843x is same as MB842x, except that it supports slave mode for 16-bit or
32-bit expansion. It makes sure there are no clashes with the _BUSY pin.
- IDT71321 is function compatible, but not pin compatible with MB8421
+ IDT71321 is function compatible, but not pin compatible with MB8421
**********************************************************************/
diff --git a/src/devices/machine/mc68681.cpp b/src/devices/machine/mc68681.cpp
index bc8244b731f..abb427feb48 100644
--- a/src/devices/machine/mc68681.cpp
+++ b/src/devices/machine/mc68681.cpp
@@ -760,7 +760,7 @@ WRITE8_MEMBER(xr68c681_device::write)
data &= 0x0f;
break;
}
-
+
mc68681_device::write(space, offset, data, mem_mask); /* pass on 68681 command */
}
diff --git a/src/devices/machine/pcf8583.cpp b/src/devices/machine/pcf8583.cpp
index 1865c882629..47babd1a2ac 100644
--- a/src/devices/machine/pcf8583.cpp
+++ b/src/devices/machine/pcf8583.cpp
@@ -4,12 +4,12 @@
Philips PCF8583 Clock and Calendar with 240 x 8-bit RAM
- TODO:
- - Alarm mode
- - Event-counter mode
- - Clock select
- - Clock output
- - Interrupts
+ TODO:
+ - Alarm mode
+ - Event-counter mode
+ - Clock select
+ - Clock output
+ - Interrupts
*********************************************************************/
diff --git a/src/devices/machine/pcf8583.h b/src/devices/machine/pcf8583.h
index 0031ef78dfe..f8d98295cb1 100644
--- a/src/devices/machine/pcf8583.h
+++ b/src/devices/machine/pcf8583.h
@@ -6,15 +6,15 @@
**********************************************************************
- The PCF8583 comes in three package configurations:
+ The PCF8583 comes in three package configurations:
- PCF8583P - 8-pin dual-inline package (DIP8)
- PCF8583T - 8-pin small-outline package (SO8)
- PCF8583BS - 20-pin thin quad-flat package (HVQFN20)
+ PCF8583P - 8-pin dual-inline package (DIP8)
+ PCF8583T - 8-pin small-outline package (SO8)
+ PCF8583BS - 20-pin thin quad-flat package (HVQFN20)
**********************************************************************
- DIP8 pinning: ____ ____
+ DIP8 pinning: ____ ____
| \/ |
OSCI 1 | | 8 Vdd
OSCI 2 | | 7 /INT
@@ -24,7 +24,7 @@
**********************************************************************
- SO8 pinning: _____ _____
+ SO8 pinning: _____ _____
| | \/ |
OSCI 1 | | | 8 Vdd
OSCI 2 | | | 7 /INT
@@ -34,10 +34,10 @@
**********************************************************************
- HVQFN20 pinning:
- NC NC NC NC NC
- 20 19 18 17 16
- __________________
+ HVQFN20 pinning:
+ NC NC NC NC NC
+ 20 19 18 17 16
+ __________________
| |
| __________ |
| | | |
@@ -95,45 +95,45 @@ protected:
private:
enum
{
- REG_CONTROL = 0x00,
- REG_HUNDREDTHS = 0x01,
- REG_SECONDS = 0x02,
- REG_MINUTES = 0x03,
- REG_HOURS = 0x04,
- REG_YEAR_DATE = 0x05,
- REG_MONTH_DAY = 0x06,
- REG_TIMER = 0x07,
- REG_ALARM_CONTROL = 0x08,
- REG_ALARM_HUNDREDTHS = 0x09,
- REG_ALARM_SECONDS = 0x0a,
- REG_ALARM_MINUTES = 0x0b,
- REG_ALARM_HOURS = 0x0c,
- REG_ALARM_DATE = 0x0d,
- REG_ALARM_MONTH = 0x0e,
- REG_ALARM_TIMER = 0x0f
+ REG_CONTROL = 0x00,
+ REG_HUNDREDTHS = 0x01,
+ REG_SECONDS = 0x02,
+ REG_MINUTES = 0x03,
+ REG_HOURS = 0x04,
+ REG_YEAR_DATE = 0x05,
+ REG_MONTH_DAY = 0x06,
+ REG_TIMER = 0x07,
+ REG_ALARM_CONTROL = 0x08,
+ REG_ALARM_HUNDREDTHS = 0x09,
+ REG_ALARM_SECONDS = 0x0a,
+ REG_ALARM_MINUTES = 0x0b,
+ REG_ALARM_HOURS = 0x0c,
+ REG_ALARM_DATE = 0x0d,
+ REG_ALARM_MONTH = 0x0e,
+ REG_ALARM_TIMER = 0x0f
};
enum
{
- CONTROL_STOP_BIT = 0x80
+ CONTROL_STOP_BIT = 0x80
};
static const device_timer_id TIMER_TICK = 0;
// get/set date
- uint8_t get_date_year() { return (m_data[REG_YEAR_DATE] >> 6) & 3; }
- void set_date_year(uint8_t year) { m_data[REG_YEAR_DATE] = (m_data[REG_YEAR_DATE] & 0x3f) | ((year % 4) << 6); }
- uint8_t get_date_month() { return bcd_to_integer(m_data[6] & 0x1f); }
- void set_date_month(uint8_t month) { m_data[REG_MONTH_DAY] = (m_data[REG_MONTH_DAY] & 0xe0) | (convert_to_bcd(month) & 0x1f); }
- uint8_t get_date_day() { return bcd_to_integer(m_data[REG_YEAR_DATE] & 0x3f); }
- void set_date_day(uint8_t day) { m_data[REG_YEAR_DATE] = (m_data[REG_YEAR_DATE] & 0xc0) | (convert_to_bcd(day) & 0x3f); }
+ uint8_t get_date_year() { return (m_data[REG_YEAR_DATE] >> 6) & 3; }
+ void set_date_year(uint8_t year) { m_data[REG_YEAR_DATE] = (m_data[REG_YEAR_DATE] & 0x3f) | ((year % 4) << 6); }
+ uint8_t get_date_month() { return bcd_to_integer(m_data[6] & 0x1f); }
+ void set_date_month(uint8_t month) { m_data[REG_MONTH_DAY] = (m_data[REG_MONTH_DAY] & 0xe0) | (convert_to_bcd(month) & 0x1f); }
+ uint8_t get_date_day() { return bcd_to_integer(m_data[REG_YEAR_DATE] & 0x3f); }
+ void set_date_day(uint8_t day) { m_data[REG_YEAR_DATE] = (m_data[REG_YEAR_DATE] & 0xc0) | (convert_to_bcd(day) & 0x3f); }
// get/set time
- uint8_t get_time_hour() { return bcd_to_integer(m_data[REG_HOURS]); }
- void set_time_hour(uint8_t hour) { m_data[REG_HOURS] = convert_to_bcd(hour); }
- uint8_t get_time_minute() { return bcd_to_integer(m_data[REG_MINUTES]); }
+ uint8_t get_time_hour() { return bcd_to_integer(m_data[REG_HOURS]); }
+ void set_time_hour(uint8_t hour) { m_data[REG_HOURS] = convert_to_bcd(hour); }
+ uint8_t get_time_minute() { return bcd_to_integer(m_data[REG_MINUTES]); }
void set_time_minute(uint8_t minute){ m_data[REG_MINUTES] = convert_to_bcd(minute); }
- uint8_t get_time_second() { return bcd_to_integer(m_data[REG_SECONDS]); }
+ uint8_t get_time_second() { return bcd_to_integer(m_data[REG_SECONDS]); }
void set_time_second(uint8_t second){ m_data[REG_SECONDS] = convert_to_bcd(second); }
void write_register(uint8_t offset, uint8_t data);
@@ -144,18 +144,18 @@ private:
// internal state
uint8_t m_data[256];
- int m_scl;
- int m_sda;
- int m_inp;
- bool m_transfer_active;
+ int m_scl;
+ int m_sda;
+ int m_inp;
+ bool m_transfer_active;
int m_bit_index;
- bool m_irq;
+ bool m_irq;
uint8_t m_data_recv_index;
uint8_t m_data_recv;
uint8_t m_mode;
uint8_t m_pos;
- uint8_t m_write_address;
- uint8_t m_read_address;
+ uint8_t m_write_address;
+ uint8_t m_read_address;
emu_timer * m_timer;
enum { RTC_MODE_NONE, RTC_MODE_SEND, RTC_MODE_RECV };
diff --git a/src/devices/machine/sda2006.cpp b/src/devices/machine/sda2006.cpp
old mode 100755
new mode 100644
index aef96819c8f..853e5cf871d
--- a/src/devices/machine/sda2006.cpp
+++ b/src/devices/machine/sda2006.cpp
@@ -5,15 +5,15 @@
#include "machine/sda2006.h"
//-------------------------------------------------
-//
+//
// Siemens SDA2006 512-bit (32x16) NV EEPROM
-//
+//
// TODO:
// - 8/12 bit controll word selection (currently emulates only 8 bt one)
// - INV pin
// - better( and correct) state flow
// - read mode, with reversed data stream
-//
+//
//-------------------------------------------------
enum {
@@ -23,8 +23,8 @@ enum {
CMD_UNKNOWN
};
-#define EEPROM_CAPACITY 0x40
-#define EEPROM_ADDRESS_MASK 0x1f
+#define EEPROM_CAPACITY 0x40
+#define EEPROM_ADDRESS_MASK 0x1f
// device type definition
DEFINE_DEVICE_TYPE(SDA2006, sda2006_device, "sda2006", "SDA2006 EEPROM")
@@ -173,7 +173,7 @@ WRITE_LINE_MEMBER( sda2006_device::write_clock )
m_write_stream_length = 0;
while(counter>0){
reversed_stream<<=1;
-
+
if (m_write_stream & mask) {
reversed_stream |= 1;
}
@@ -182,7 +182,7 @@ WRITE_LINE_MEMBER( sda2006_device::write_clock )
}
uint32_t command = bitswap<8>(m_write_stream, 7,6,5,4,3,0,1,2);
-
+
switch (command&3){
case CMD_WRITE: m_eeprom_data[(reversed_stream>>16) & EEPROM_ADDRESS_MASK] = reversed_stream & 0xffff; break;
case CMD_READ:
@@ -191,7 +191,7 @@ WRITE_LINE_MEMBER( sda2006_device::write_clock )
m_eeprom_state = EEPROM_READ;
break;
case CMD_READ_REVERSED:
- case CMD_UNKNOWN: break;
+ case CMD_UNKNOWN: break;
}
} else {
diff --git a/src/devices/machine/sda2006.h b/src/devices/machine/sda2006.h
old mode 100755
new mode 100644
index c17f655ef0a..31657be6344
--- a/src/devices/machine/sda2006.h
+++ b/src/devices/machine/sda2006.h
@@ -4,7 +4,7 @@
#define MAME_MACHINE_SDA2006_H
#pragma once
-
+
// sda2006_device
diff --git a/src/devices/sound/aica.cpp b/src/devices/sound/aica.cpp
index 4ad7c2f5995..e304b5a6fc4 100644
--- a/src/devices/sound/aica.cpp
+++ b/src/devices/sound/aica.cpp
@@ -14,7 +14,7 @@
- Some minor other tweeks (no EGHOLD, slighly more capable DSP)
TODO:
- - Where are EXTS Connected?
+ - Where are EXTS Connected?
*/
#include "emu.h"
@@ -980,7 +980,7 @@ void aica_device::w16(address_space &space,unsigned int addr,unsigned short val)
else if(addr<0x45c0)
*((unsigned short *) (m_DSP.EFREG+(addr-0x4580)/4))=val;
//else if(addr<0x45c8)
- // *((unsigned short *) (m_DSP.EXTS+(addr-0x45c0)/2))=val; // Read only
+ // *((unsigned short *) (m_DSP.EXTS+(addr-0x45c0)/2))=val; // Read only
}
}
diff --git a/src/devices/sound/c6280.cpp b/src/devices/sound/c6280.cpp
index 1b3665d40f8..647a7e5f4cb 100644
--- a/src/devices/sound/c6280.cpp
+++ b/src/devices/sound/c6280.cpp
@@ -36,9 +36,9 @@
- http://www.hudsonsoft.net/ww/about/about.html
- http://www.hudson.co.jp/corp/eng/coinfo/history.html
- Integrated on:
- HuC6280 CPU (PC Engine/TurboGrafx 16)
- HuC6230 Sound Chip (PC-FX, with OKI ADPCM)
+ Integrated on:
+ HuC6280 CPU (PC Engine/TurboGrafx 16)
+ HuC6230 Sound Chip (PC-FX, with OKI ADPCM)
*/
diff --git a/src/devices/sound/huc6230.cpp b/src/devices/sound/huc6230.cpp
index f762b2ad7f2..23155c4dc7f 100644
--- a/src/devices/sound/huc6230.cpp
+++ b/src/devices/sound/huc6230.cpp
@@ -2,12 +2,12 @@
// copyright-holders:cam900
/*
Hudson HuC6230 SoundBox
- HuC6280 PSG with ADPCM
+ HuC6280 PSG with ADPCM
- TODO:
- - Volume is linear?
- - Make it actually working
- - Implement CDDA Volume
+ TODO:
+ - Volume is linear?
+ - Make it actually working
+ - Implement CDDA Volume
*/
#include "emu.h"
@@ -52,7 +52,7 @@ void huc6230_device::sound_stream_update(sound_stream &stream, stream_sample_t *
if (!channel->m_interpolate)
sample = channel->m_curr_sample;
else
- sample = ((channel->m_prev_sample * (frq - channel->m_pos)) +
+ sample = ((channel->m_prev_sample * (frq - channel->m_pos)) +
(channel->m_curr_sample * channel->m_pos)) >> m_adpcm_freq;
outputs[0][i] = clamp(outputs[0][i] + ((sample * channel->m_lvol) >> 2), -32768, 32767);
diff --git a/src/devices/sound/qsoundhle.cpp b/src/devices/sound/qsoundhle.cpp
index 833c31c2e97..2fac6a79012 100644
--- a/src/devices/sound/qsoundhle.cpp
+++ b/src/devices/sound/qsoundhle.cpp
@@ -237,7 +237,7 @@ void qsound_hle_device::init_register_map()
m_register_map[(i << 3) + 4] = (uint16_t*)&m_voice[i].m_loop_len;
m_register_map[(i << 3) + 5] = (uint16_t*)&m_voice[i].m_end_addr;
m_register_map[(i << 3) + 6] = (uint16_t*)&m_voice[i].m_volume;
- m_register_map[(i << 3) + 7] = nullptr; // unused
+ m_register_map[(i << 3) + 7] = nullptr; // unused
m_register_map[i + 0x80] = (uint16_t*)&m_voice_pan[i];
m_register_map[i + 0xba] = (uint16_t*)&m_voice[i].m_echo;
}
@@ -277,7 +277,7 @@ int16_t qsound_hle_device::read_sample(uint16_t bank, uint16_t address)
bank &= 0x7FFF;
const uint32_t rom_addr = (bank << 16) | (address << 0);
const uint8_t sample_data = read_byte(rom_addr);
- return (int16_t)(sample_data << 8); // bit0-7 is tied to ground
+ return (int16_t)(sample_data << 8); // bit0-7 is tied to ground
}
/********************************************************************/
diff --git a/src/devices/sound/qsoundhle.h b/src/devices/sound/qsoundhle.h
index dfaded4d4bc..53d1300b583 100644
--- a/src/devices/sound/qsoundhle.h
+++ b/src/devices/sound/qsoundhle.h
@@ -38,18 +38,18 @@ private:
// DSP ROM sample map
enum {
- DATA_PAN_TAB = 0x110,
- DATA_ADPCM_TAB = 0x9dc,
- DATA_FILTER_TAB = 0xd53, // dual filter mode, 5 tables * 95 taps each
- DATA_FILTER_TAB2 = 0xf2e, // overlapping data (95+15+95)
+ DATA_PAN_TAB = 0x110,
+ DATA_ADPCM_TAB = 0x9dc,
+ DATA_FILTER_TAB = 0xd53, // dual filter mode, 5 tables * 95 taps each
+ DATA_FILTER_TAB2 = 0xf2e, // overlapping data (95+15+95)
STATE_BOOT = 0x000,
- STATE_INIT1 = 0x288,
- STATE_INIT2 = 0x61a,
- STATE_REFRESH1 = 0x039,
- STATE_REFRESH2 = 0x04f,
- STATE_NORMAL1 = 0x314,
- STATE_NORMAL2 = 0x6b2
+ STATE_INIT1 = 0x288,
+ STATE_INIT2 = 0x61a,
+ STATE_REFRESH1 = 0x039,
+ STATE_REFRESH2 = 0x04f,
+ STATE_NORMAL1 = 0x314,
+ STATE_NORMAL2 = 0x6b2
};
const uint16_t PAN_TABLE_DRY = 0;
@@ -87,7 +87,7 @@ private:
// Q1 Filter
struct qsound_fir {
- int m_tap_count = 0; // usually 95
+ int m_tap_count = 0; // usually 95
int m_delay_pos = 0;
uint16_t m_table_pos = 0;
int16_t m_taps[95] = { 0 };
diff --git a/src/devices/sound/zsg2.cpp b/src/devices/sound/zsg2.cpp
index 92ddef50212..6e97ce01f43 100644
--- a/src/devices/sound/zsg2.cpp
+++ b/src/devices/sound/zsg2.cpp
@@ -6,47 +6,47 @@
Written by Olivier Galibert
MAME conversion by R. Belmont
Working emulation by The Talentuous Hands Of The Popularious hap
- Properly working emulation by superctr
+ Properly working emulation by superctr
---------------------------------------------------------
- Register map:
- 000-5fe : Channel specific registers
- (high) (low)
- +000 : xxxxxxxx -------- : Start address (low)
- +000 : -------- xxxxxxxx : Unknown register (usually cleared)
- +002 : xxxxxxxx -------- : Address page
- : -------- xxxxxxxx : Start address (high)
- +004 : -------- -------- : Unknown register (usually cleared)
- +006 : -----x-- -------- : Unknown bit, always set
- +008 : xxxxxxxx xxxxxxxx : Frequency
- +00a : xxxxxxxx -------- : DSP ch 3 (right) output gain
- : -------- xxxxxxxx : Loop address (low)
- +00c : xxxxxxxx xxxxxxxx : End address
- +00e : xxxxxxxx -------- : DSP ch 2 (Left) output gain
- : -------- xxxxxxxx : Loop address (high)
- +010 : xxxxxxxx xxxxxxxx : Initial filter time constant
- +012 : xxxxxxxx xxxxxxxx : Current filter time constant
- +014 : xxxxxxxx xxxxxxxx : Initial volume
- +016 : xxxxxxxx xxxxxxxx : Current volume
- +018 : xxxxxxxx xxxxxxxx : Target filter time constant
- +01a : xxxxxxxx -------- : DSP ch 1 (chorus) output gain
- : -------- xxxxxxxx : Filter ramping speed
- +01c : xxxxxxxx xxxxxxxx : Target volume
- +01e : xxxxxxxx -------- : DSP ch 0 (reverb) output gain
- : -------- xxxxxxxx : Filter ramping speed
- 600-604 : Key on flags (each bit corresponds to a channel)
- 608-60c : Key off flags (each bit corresponds to a channel)
- 618 : Unknown register (usually 0x5cbc is written)
- 61a : Unknown register (usually 0x5cbc is written)
- 620 : Unknown register (usually 0x0128 is written)
- 628 : Unknown register (usually 0x0066 is written)
- 630 : Unknown register (usually 0x0001 is written)
- 638 : ROM readback address low
- 63a : ROM readback address high
- 63c : ROM readback word low
- 63e : ROM readback word high
+ Register map:
+ 000-5fe : Channel specific registers
+ (high) (low)
+ +000 : xxxxxxxx -------- : Start address (low)
+ +000 : -------- xxxxxxxx : Unknown register (usually cleared)
+ +002 : xxxxxxxx -------- : Address page
+ : -------- xxxxxxxx : Start address (high)
+ +004 : -------- -------- : Unknown register (usually cleared)
+ +006 : -----x-- -------- : Unknown bit, always set
+ +008 : xxxxxxxx xxxxxxxx : Frequency
+ +00a : xxxxxxxx -------- : DSP ch 3 (right) output gain
+ : -------- xxxxxxxx : Loop address (low)
+ +00c : xxxxxxxx xxxxxxxx : End address
+ +00e : xxxxxxxx -------- : DSP ch 2 (Left) output gain
+ : -------- xxxxxxxx : Loop address (high)
+ +010 : xxxxxxxx xxxxxxxx : Initial filter time constant
+ +012 : xxxxxxxx xxxxxxxx : Current filter time constant
+ +014 : xxxxxxxx xxxxxxxx : Initial volume
+ +016 : xxxxxxxx xxxxxxxx : Current volume
+ +018 : xxxxxxxx xxxxxxxx : Target filter time constant
+ +01a : xxxxxxxx -------- : DSP ch 1 (chorus) output gain
+ : -------- xxxxxxxx : Filter ramping speed
+ +01c : xxxxxxxx xxxxxxxx : Target volume
+ +01e : xxxxxxxx -------- : DSP ch 0 (reverb) output gain
+ : -------- xxxxxxxx : Filter ramping speed
+ 600-604 : Key on flags (each bit corresponds to a channel)
+ 608-60c : Key off flags (each bit corresponds to a channel)
+ 618 : Unknown register (usually 0x5cbc is written)
+ 61a : Unknown register (usually 0x5cbc is written)
+ 620 : Unknown register (usually 0x0128 is written)
+ 628 : Unknown register (usually 0x0066 is written)
+ 630 : Unknown register (usually 0x0001 is written)
+ 638 : ROM readback address low
+ 63a : ROM readback address high
+ 63c : ROM readback word low
+ 63e : ROM readback word high
- ---------------------------------------------------------
+ ---------------------------------------------------------
Additional notes on the sample format, reverse-engineered
by Olivier Galibert and David Haywood:
@@ -553,15 +553,15 @@ void zsg2_device::control_w(int reg, uint16_t data)
break;
}
-// case 0x0c: //These registers are sometimes written to by the CPU. Unknown purpose.
-// break;
-// case 0x0d:
-// break;
-// case 0x10:
-// break;
+// case 0x0c: //These registers are sometimes written to by the CPU. Unknown purpose.
+// break;
+// case 0x0d:
+// break;
+// case 0x10:
+// break;
-// case 0x18:
-// break;
+// case 0x18:
+// break;
case 0x1c:
// rom readback address low (low 2 bits always 0)
diff --git a/src/devices/video/huc6272.cpp b/src/devices/video/huc6272.cpp
index 264e896bbd3..8fd271afc0a 100644
--- a/src/devices/video/huc6272.cpp
+++ b/src/devices/video/huc6272.cpp
@@ -6,7 +6,7 @@
TODO:
- Use NSCSI instead of legacy one!
- - ADPCM Transfer is correct?
+ - ADPCM Transfer is correct?
***************************************************************************/
diff --git a/src/emu/emumem_hedp.cpp b/src/emu/emumem_hedp.cpp
index 84b43191d1d..84a592fbfbd 100644
--- a/src/emu/emumem_hedp.cpp
+++ b/src/emu/emumem_hedp.cpp
@@ -5,62 +5,62 @@
#include "emumem_hea.h"
#include "emumem_hedp.h"
-template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
+template template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
{
return m_delegate(*inh::m_space, ((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift), mem_mask);
}
-template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
+template template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
{
return m_delegate(*inh::m_space, ((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift));
}
-template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
+template template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
{
return m_delegate(((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift), mem_mask);
}
-template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
+template template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
{
return m_delegate(((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift));
}
-template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
+template template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
{
return m_delegate(*inh::m_space);
}
-template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
+template template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ typename emu::detail::handler_entry_size::uX> handler_entry_read_delegate::read_impl(offs_t offset, uX mem_mask)
{
return m_delegate();
}
@@ -76,61 +76,61 @@ template std::string handle
}
template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
{
m_delegate(*inh::m_space, ((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift), data, mem_mask);
}
template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
{
m_delegate(*inh::m_space, ((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift), data);
}
template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
{
m_delegate(((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift), data, mem_mask);
}
template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
{
m_delegate(((offset - inh::m_address_base) & inh::m_address_mask) >> (Width + AddrShift), data);
}
template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
{
m_delegate(*inh::m_space, data);
}
template template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> handler_entry_write_delegate::write_impl(offs_t offset, uX data, uX mem_mask)
{
m_delegate(data);
}
diff --git a/src/emu/emumem_hedp.h b/src/emu/emumem_hedp.h
index 4b21085f7a9..cba4877b20c 100644
--- a/src/emu/emumem_hedp.h
+++ b/src/emu/emumem_hedp.h
@@ -21,47 +21,47 @@ public:
private:
READ m_delegate;
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- uX> read_impl(offs_t offset, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ uX> read_impl(offs_t offset, uX mem_mask);
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- uX> read_impl(offs_t offset, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ uX> read_impl(offs_t offset, uX mem_mask);
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- uX> read_impl(offs_t offset, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ uX> read_impl(offs_t offset, uX mem_mask);
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- uX> read_impl(offs_t offset, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ uX> read_impl(offs_t offset, uX mem_mask);
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- uX> read_impl(offs_t offset, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ uX> read_impl(offs_t offset, uX mem_mask);
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- uX> read_impl(offs_t offset, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ uX> read_impl(offs_t offset, uX mem_mask);
};
template class handler_entry_write_delegate : public handler_entry_write_address
@@ -80,47 +80,47 @@ public:
private:
WRITE m_delegate;
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> write_impl(offs_t offset, uX data, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> write_impl(offs_t offset, uX data, uX mem_mask);
- template
- std::enable_if_t::value ||
- std::is_same::value ||
- std::is_same::value ||
- std::is_same::value,
- void> write_impl(offs_t offset, uX data, uX mem_mask);
+ template
+ std::enable_if_t::value ||
+ std::is_same::value ||
+ std::is_same::value ||
+ std::is_same::value,
+ void> write_impl(offs_t offset, uX data, uX mem_mask);
- template
- std::enable_if_t