diff --git a/src/emu/cpu/cop400/410ops.c b/src/emu/cpu/cop400/410ops.c index 27821fac30a..1aecfc99be1 100644 --- a/src/emu/cpu/cop400/410ops.c +++ b/src/emu/cpu/cop400/410ops.c @@ -9,7 +9,7 @@ ***************************************************************************/ -#define INSTRUCTION(mnemonic) INLINE UINT16 (mnemonic)(UINT8 opcode) +#define INSTRUCTION(mnemonic) INLINE void (mnemonic)(UINT8 opcode) #define ROM(addr) cpu_readop(addr) #define RAM_W(addr, value) (data_write_byte_8(addr, value)) @@ -31,7 +31,10 @@ #define PC R.PC #define prevPC R.PREVPC #define skip R.skip -#define skip_lbi R.skip_lbi +#define skipLBI R.skipLBI + +#define READ_M RAM_R(B) +#define WRITE_M(VAL) RAM_W(B,VAL) #define IN_G() IN(COP400_PORT_G) #define IN_L() IN(COP400_PORT_L) @@ -138,8 +141,6 @@ INLINE void WRITE_G(UINT8 data) INSTRUCTION(illegal) { logerror("COP400: PC = %04x, Illegal opcode = %02x\n", PC-1, ROM(PC-1)); - - return PC + 1; } /* Arithmetic Instructions */ @@ -174,8 +175,6 @@ INSTRUCTION(asc) { C = 0; } - - return PC + 1; } /* @@ -194,8 +193,6 @@ INSTRUCTION(asc) INSTRUCTION(add) { A = (A + RAM_R(B)) & 0x0F; - - return PC + 1; } /* @@ -225,8 +222,6 @@ INSTRUCTION(aisc) skip = 1; A &= 0xF; } - - return PC + 1; } /* @@ -245,8 +240,6 @@ INSTRUCTION(aisc) INSTRUCTION(clra) { A = 0; - - return PC + 1; } /* @@ -265,8 +258,6 @@ INSTRUCTION(clra) INSTRUCTION(comp) { A = A ^ 0xF; - - return PC + 1; } /* @@ -283,8 +274,6 @@ INSTRUCTION(comp) INSTRUCTION(nop) { // do nothing - - return PC + 1; } /* @@ -303,8 +292,6 @@ INSTRUCTION(nop) INSTRUCTION(rc) { C = 0; - - return PC + 1; } /* @@ -323,8 +310,6 @@ INSTRUCTION(rc) INSTRUCTION(sc) { C = 1; - - return PC + 1; } /* @@ -343,8 +328,6 @@ INSTRUCTION(sc) INSTRUCTION(xor) { A = RAM_R(B) ^ A; - - return PC + 1; } /* Transfer-of-Control Instructions */ @@ -364,9 +347,8 @@ INSTRUCTION(xor) INSTRUCTION(jid) { - UINT16 addr = (PC & 0x300) | (A << 4) | RAM_R(B); - - return (PC & 0x300) | ROM(addr); + UINT16 addr = (PC & 0x300) | (A << 4) | READ_M; + PC = (PC & 0x300) | ROM(addr); } /* @@ -385,9 +367,7 @@ INSTRUCTION(jid) INSTRUCTION(jmp) { - UINT8 a = ((opcode & 0x03) << 8) | ROM(++PC); - - return a; + PC = ((opcode & 0x03) << 8) | ROM(PC); } /* @@ -408,42 +388,27 @@ INSTRUCTION(jmp) Description: Jump within Page - -------------------------------------------- - - Mnemonic: JSRP - - Operand: a - Hex Code: -- - Binary: 1 0 a5 a4 a3 a2 a1 a0 - - Data Flow: PC + 1 -> SA -> SB -> SC - 0010 -> PC9:6 - a -> PC5:0 - - Description: Jump to Subroutine Page - */ INSTRUCTION(jp) { - UINT8 page = (PC >> 6) & 0x0f; + UINT8 op = ROM(prevPC); - if (page == 2 || page == 3) + if (((PC & 0x3E0) >= 0x80) && ((PC & 0x3E0) < 0x100)) //JP pages 2,3 { - UINT8 a = opcode & 0x7f; - return (PC & 0x30) | a; - } - else if ((opcode & 0xc0) == 0xc0) - { - UINT8 a = opcode & 0x3f; - return (PC & 0x3c0) | a; + PC = (UINT16)((PC & 0x380) | (op & 0x7F)); } else { - // JSRP - UINT8 a = opcode & 0x3f; - PUSH(PC + 1); - return 0x80 | a; + if ((op & 0xC0) == 0xC0) //JP other pages + { + PC = (UINT16)((PC & 0x3C0) | (op & 0x3F)); + } + else //JSRP + { + PUSH((UINT16)(PC)); + PC = (UINT16)(0x80 | (op & 0x3F)); + } } } @@ -462,14 +427,17 @@ INSTRUCTION(jp) */ - -INSTRUCTION(jsr) +INLINE void JSR(UINT8 a8) { - UINT16 a = ((opcode & 0x03) << 8) | ROM(++PC); PUSH(PC + 1); - return a; + PC = (a8 << 8) | ROM(PC); } +INSTRUCTION(jsr0) { JSR(0); } +INSTRUCTION(jsr1) { JSR(1); } +INSTRUCTION(jsr2) { JSR(2); } +INSTRUCTION(jsr3) { JSR(3); } + /* Mnemonic: RET @@ -486,8 +454,6 @@ INSTRUCTION(jsr) INSTRUCTION(ret) { POP(); - - return PC; } /* @@ -509,8 +475,6 @@ INSTRUCTION(retsk) { POP(); skip = 1; - - return PC; } /* Memory Reference Instructions */ @@ -531,9 +495,7 @@ INSTRUCTION(retsk) INSTRUCTION(camq) { - WRITE_Q((A << 4) | RAM_R(B)); - - return PC + 1; + WRITE_Q((A << 4) | READ_M); } /* @@ -557,10 +519,10 @@ INLINE void LD(UINT8 r) B = B ^ (r << 4); } -INSTRUCTION(ld0) { LD(0); return PC + 1; } -INSTRUCTION(ld1) { LD(1); return PC + 1; } -INSTRUCTION(ld2) { LD(2); return PC + 1; } -INSTRUCTION(ld3) { LD(3); return PC + 1; } +INSTRUCTION(ld0) { LD(0); } +INSTRUCTION(ld1) { LD(1); } +INSTRUCTION(ld2) { LD(2); } +INSTRUCTION(ld3) { LD(3); } /* @@ -579,11 +541,9 @@ INSTRUCTION(ld3) { LD(3); return PC + 1; } INSTRUCTION(lqid) { PUSH(PC + 1); - PC = (PC & 0x300) | (A << 4) | RAM_R(B); + PC = (UINT16)((PC & 0x300) | (A << 4) | READ_M); WRITE_Q(ROM(PC)); POP(); - - return PC; } /* @@ -614,10 +574,10 @@ INSTRUCTION(lqid) */ -INSTRUCTION(rmb0) { RAM_W(B, RAM_R(B) & 0xE); return PC + 1; } -INSTRUCTION(rmb1) { RAM_W(B, RAM_R(B) & 0xD); return PC + 1; } -INSTRUCTION(rmb2) { RAM_W(B, RAM_R(B) & 0xB); return PC + 1; } -INSTRUCTION(rmb3) { RAM_W(B, RAM_R(B) & 0x7); return PC + 1; } +INSTRUCTION(rmb0) { RAM_W(B, RAM_R(B) & 0xE); } +INSTRUCTION(rmb1) { RAM_W(B, RAM_R(B) & 0xD); } +INSTRUCTION(rmb2) { RAM_W(B, RAM_R(B) & 0xB); } +INSTRUCTION(rmb3) { RAM_W(B, RAM_R(B) & 0x7); } /* @@ -647,10 +607,10 @@ INSTRUCTION(rmb3) { RAM_W(B, RAM_R(B) & 0x7); return PC + 1; } */ -INSTRUCTION(smb0) { RAM_W(B, RAM_R(B) | 0x1); return PC + 1; } -INSTRUCTION(smb1) { RAM_W(B, RAM_R(B) | 0x2); return PC + 1; } -INSTRUCTION(smb2) { RAM_W(B, RAM_R(B) | 0x4); return PC + 1; } -INSTRUCTION(smb3) { RAM_W(B, RAM_R(B) | 0x8); return PC + 1; } +INSTRUCTION(smb0) { RAM_W(B, RAM_R(B) | 0x1); } +INSTRUCTION(smb1) { RAM_W(B, RAM_R(B) | 0x2); } +INSTRUCTION(smb2) { RAM_W(B, RAM_R(B) | 0x4); } +INSTRUCTION(smb3) { RAM_W(B, RAM_R(B) | 0x8); } /* @@ -676,8 +636,6 @@ INSTRUCTION(stii) Bd = (B & 0x0f) + 1; if (Bd > 15) Bd = 0; B = (B & 0x30) + Bd; - - return PC + 1; } /* @@ -704,8 +662,6 @@ INSTRUCTION(x) A = t; B = B ^ (r << 4); - - return PC + 1; } /* @@ -724,12 +680,10 @@ INSTRUCTION(x) INSTRUCTION(xad) { - UINT8 addr = ROM(++PC) & 0x3f; + UINT8 addr = ROM(PC++) & 0x3f; UINT8 t = A; A = RAM_R(addr); RAM_W(addr, t); - - return PC + 1; } /* @@ -764,8 +718,6 @@ INSTRUCTION(xds) B = (UINT8)(Br | (Bd & 0x0F)); if (Bd == 0xFF) skip = 1; - - return PC + 1; } /* @@ -800,8 +752,6 @@ INSTRUCTION(xis) B = (UINT8)(Br | (Bd & 0x0F)); if (Bd == 0x10) skip = 1; - - return PC + 1; } /* Register Reference Instructions */ @@ -822,8 +772,6 @@ INSTRUCTION(xis) INSTRUCTION(cab) { B = (B & 0x30) | A; - - return PC + 1; } /* @@ -842,8 +790,6 @@ INSTRUCTION(cab) INSTRUCTION(cba) { A = B & 0xF; - - return PC + 1; } /* @@ -868,76 +814,76 @@ INSTRUCTION(cba) INLINE void LBI(UINT8 r, UINT8 d) { B = (r << 4) | d; - skip_lbi = 1; + skipLBI = 1; } -INSTRUCTION(lbi0_0) { LBI(0,0); return PC + 1; } -INSTRUCTION(lbi0_1) { LBI(0,1); return PC + 1; } -INSTRUCTION(lbi0_2) { LBI(0,2); return PC + 1; } -INSTRUCTION(lbi0_3) { LBI(0,3); return PC + 1; } -INSTRUCTION(lbi0_4) { LBI(0,4); return PC + 1; } -INSTRUCTION(lbi0_5) { LBI(0,5); return PC + 1; } -INSTRUCTION(lbi0_6) { LBI(0,6); return PC + 1; } -INSTRUCTION(lbi0_7) { LBI(0,7); return PC + 1; } -INSTRUCTION(lbi0_8) { LBI(0,8); return PC + 1; } -INSTRUCTION(lbi0_9) { LBI(0,9); return PC + 1; } -INSTRUCTION(lbi0_10) { LBI(0,10); return PC + 1; } -INSTRUCTION(lbi0_11) { LBI(0,11); return PC + 1; } -INSTRUCTION(lbi0_12) { LBI(0,12); return PC + 1; } -INSTRUCTION(lbi0_13) { LBI(0,13); return PC + 1; } -INSTRUCTION(lbi0_14) { LBI(0,14); return PC + 1; } -INSTRUCTION(lbi0_15) { LBI(0,15); return PC + 1; } +INSTRUCTION(lbi0_0) { LBI(0,0); } +INSTRUCTION(lbi0_1) { LBI(0,1); } +INSTRUCTION(lbi0_2) { LBI(0,2); } +INSTRUCTION(lbi0_3) { LBI(0,3); } +INSTRUCTION(lbi0_4) { LBI(0,4); } +INSTRUCTION(lbi0_5) { LBI(0,5); } +INSTRUCTION(lbi0_6) { LBI(0,6); } +INSTRUCTION(lbi0_7) { LBI(0,7); } +INSTRUCTION(lbi0_8) { LBI(0,8); } +INSTRUCTION(lbi0_9) { LBI(0,9); } +INSTRUCTION(lbi0_10) { LBI(0,10); } +INSTRUCTION(lbi0_11) { LBI(0,11); } +INSTRUCTION(lbi0_12) { LBI(0,12); } +INSTRUCTION(lbi0_13) { LBI(0,13); } +INSTRUCTION(lbi0_14) { LBI(0,14); } +INSTRUCTION(lbi0_15) { LBI(0,15); } -INSTRUCTION(lbi1_0) { LBI(1,0); return PC + 1; } -INSTRUCTION(lbi1_1) { LBI(1,1); return PC + 1; } -INSTRUCTION(lbi1_2) { LBI(1,2); return PC + 1; } -INSTRUCTION(lbi1_3) { LBI(1,3); return PC + 1; } -INSTRUCTION(lbi1_4) { LBI(1,4); return PC + 1; } -INSTRUCTION(lbi1_5) { LBI(1,5); return PC + 1; } -INSTRUCTION(lbi1_6) { LBI(1,6); return PC + 1; } -INSTRUCTION(lbi1_7) { LBI(1,7); return PC + 1; } -INSTRUCTION(lbi1_8) { LBI(1,8); return PC + 1; } -INSTRUCTION(lbi1_9) { LBI(1,9); return PC + 1; } -INSTRUCTION(lbi1_10) { LBI(1,10); return PC + 1; } -INSTRUCTION(lbi1_11) { LBI(1,11); return PC + 1; } -INSTRUCTION(lbi1_12) { LBI(1,12); return PC + 1; } -INSTRUCTION(lbi1_13) { LBI(1,13); return PC + 1; } -INSTRUCTION(lbi1_14) { LBI(1,14); return PC + 1; } -INSTRUCTION(lbi1_15) { LBI(1,15); return PC + 1; } +INSTRUCTION(lbi1_0) { LBI(1,0); } +INSTRUCTION(lbi1_1) { LBI(1,1); } +INSTRUCTION(lbi1_2) { LBI(1,2); } +INSTRUCTION(lbi1_3) { LBI(1,3); } +INSTRUCTION(lbi1_4) { LBI(1,4); } +INSTRUCTION(lbi1_5) { LBI(1,5); } +INSTRUCTION(lbi1_6) { LBI(1,6); } +INSTRUCTION(lbi1_7) { LBI(1,7); } +INSTRUCTION(lbi1_8) { LBI(1,8); } +INSTRUCTION(lbi1_9) { LBI(1,9); } +INSTRUCTION(lbi1_10) { LBI(1,10); } +INSTRUCTION(lbi1_11) { LBI(1,11); } +INSTRUCTION(lbi1_12) { LBI(1,12); } +INSTRUCTION(lbi1_13) { LBI(1,13); } +INSTRUCTION(lbi1_14) { LBI(1,14); } +INSTRUCTION(lbi1_15) { LBI(1,15); } -INSTRUCTION(lbi2_0) { LBI(2,0); return PC + 1; } -INSTRUCTION(lbi2_1) { LBI(2,1); return PC + 1; } -INSTRUCTION(lbi2_2) { LBI(2,2); return PC + 1; } -INSTRUCTION(lbi2_3) { LBI(2,3); return PC + 1; } -INSTRUCTION(lbi2_4) { LBI(2,4); return PC + 1; } -INSTRUCTION(lbi2_5) { LBI(2,5); return PC + 1; } -INSTRUCTION(lbi2_6) { LBI(2,6); return PC + 1; } -INSTRUCTION(lbi2_7) { LBI(2,7); return PC + 1; } -INSTRUCTION(lbi2_8) { LBI(2,8); return PC + 1; } -INSTRUCTION(lbi2_9) { LBI(2,9); return PC + 1; } -INSTRUCTION(lbi2_10) { LBI(2,10); return PC + 1; } -INSTRUCTION(lbi2_11) { LBI(2,11); return PC + 1; } -INSTRUCTION(lbi2_12) { LBI(2,12); return PC + 1; } -INSTRUCTION(lbi2_13) { LBI(2,13); return PC + 1; } -INSTRUCTION(lbi2_14) { LBI(2,14); return PC + 1; } -INSTRUCTION(lbi2_15) { LBI(2,15); return PC + 1; } +INSTRUCTION(lbi2_0) { LBI(2,0); } +INSTRUCTION(lbi2_1) { LBI(2,1); } +INSTRUCTION(lbi2_2) { LBI(2,2); } +INSTRUCTION(lbi2_3) { LBI(2,3); } +INSTRUCTION(lbi2_4) { LBI(2,4); } +INSTRUCTION(lbi2_5) { LBI(2,5); } +INSTRUCTION(lbi2_6) { LBI(2,6); } +INSTRUCTION(lbi2_7) { LBI(2,7); } +INSTRUCTION(lbi2_8) { LBI(2,8); } +INSTRUCTION(lbi2_9) { LBI(2,9); } +INSTRUCTION(lbi2_10) { LBI(2,10); } +INSTRUCTION(lbi2_11) { LBI(2,11); } +INSTRUCTION(lbi2_12) { LBI(2,12); } +INSTRUCTION(lbi2_13) { LBI(2,13); } +INSTRUCTION(lbi2_14) { LBI(2,14); } +INSTRUCTION(lbi2_15) { LBI(2,15); } -INSTRUCTION(lbi3_0) { LBI(3,0); return PC + 1; } -INSTRUCTION(lbi3_1) { LBI(3,1); return PC + 1; } -INSTRUCTION(lbi3_2) { LBI(3,2); return PC + 1; } -INSTRUCTION(lbi3_3) { LBI(3,3); return PC + 1; } -INSTRUCTION(lbi3_4) { LBI(3,4); return PC + 1; } -INSTRUCTION(lbi3_5) { LBI(3,5); return PC + 1; } -INSTRUCTION(lbi3_6) { LBI(3,6); return PC + 1; } -INSTRUCTION(lbi3_7) { LBI(3,7); return PC + 1; } -INSTRUCTION(lbi3_8) { LBI(3,8); return PC + 1; } -INSTRUCTION(lbi3_9) { LBI(3,9); return PC + 1; } -INSTRUCTION(lbi3_10) { LBI(3,10); return PC + 1; } -INSTRUCTION(lbi3_11) { LBI(3,11); return PC + 1; } -INSTRUCTION(lbi3_12) { LBI(3,12); return PC + 1; } -INSTRUCTION(lbi3_13) { LBI(3,13); return PC + 1; } -INSTRUCTION(lbi3_14) { LBI(3,14); return PC + 1; } -INSTRUCTION(lbi3_15) { LBI(3,15); return PC + 1; } +INSTRUCTION(lbi3_0) { LBI(3,0); } +INSTRUCTION(lbi3_1) { LBI(3,1); } +INSTRUCTION(lbi3_2) { LBI(3,2); } +INSTRUCTION(lbi3_3) { LBI(3,3); } +INSTRUCTION(lbi3_4) { LBI(3,4); } +INSTRUCTION(lbi3_5) { LBI(3,5); } +INSTRUCTION(lbi3_6) { LBI(3,6); } +INSTRUCTION(lbi3_7) { LBI(3,7); } +INSTRUCTION(lbi3_8) { LBI(3,8); } +INSTRUCTION(lbi3_9) { LBI(3,9); } +INSTRUCTION(lbi3_10) { LBI(3,10); } +INSTRUCTION(lbi3_11) { LBI(3,11); } +INSTRUCTION(lbi3_12) { LBI(3,12); } +INSTRUCTION(lbi3_13) { LBI(3,13); } +INSTRUCTION(lbi3_14) { LBI(3,14); } +INSTRUCTION(lbi3_15) { LBI(3,15); } /* @@ -963,8 +909,6 @@ INSTRUCTION(lei) { OUT_L(0); } - - return PC + 1; } /* Test Instructions */ @@ -985,8 +929,6 @@ INSTRUCTION(lei) INSTRUCTION(skc) { if (C == 1) skip = 1; - - return PC + 1; } /* @@ -1005,8 +947,6 @@ INSTRUCTION(skc) INSTRUCTION(ske) { if (A == RAM_R(B)) skip = 1; - - return PC + 1; } /* @@ -1025,8 +965,6 @@ INSTRUCTION(ske) INSTRUCTION(skgz) { if (IN_G() == 0) skip = 1; - - return PC + 1; } /* @@ -1049,10 +987,10 @@ INSTRUCTION(skgz) */ -INSTRUCTION(skgbz0) { if (!BIT(IN_G(), 0)) skip = 1; return PC + 1; } -INSTRUCTION(skgbz1) { if (!BIT(IN_G(), 1)) skip = 1; return PC + 1; } -INSTRUCTION(skgbz2) { if (!BIT(IN_G(), 2)) skip = 1; return PC + 1; } -INSTRUCTION(skgbz3) { if (!BIT(IN_G(), 3)) skip = 1; return PC + 1; } +INSTRUCTION(skgbz0) { if (!BIT(IN_G(), 0)) skip = 1; } +INSTRUCTION(skgbz1) { if (!BIT(IN_G(), 1)) skip = 1; } +INSTRUCTION(skgbz2) { if (!BIT(IN_G(), 2)) skip = 1; } +INSTRUCTION(skgbz3) { if (!BIT(IN_G(), 3)) skip = 1; } /* @@ -1074,10 +1012,10 @@ INSTRUCTION(skgbz3) { if (!BIT(IN_G(), 3)) skip = 1; return PC + 1; } */ -INSTRUCTION(skmbz0) { if (!BIT(RAM_R(B), 0)) skip = 1; return PC + 1; } -INSTRUCTION(skmbz1) { if (!BIT(RAM_R(B), 1)) skip = 1; return PC + 1; } -INSTRUCTION(skmbz2) { if (!BIT(RAM_R(B), 2)) skip = 1; return PC + 1; } -INSTRUCTION(skmbz3) { if (!BIT(RAM_R(B), 3)) skip = 1; return PC + 1; } +INSTRUCTION(skmbz0) { if (!BIT(RAM_R(B), 0)) skip = 1; } +INSTRUCTION(skmbz1) { if (!BIT(RAM_R(B), 1)) skip = 1; } +INSTRUCTION(skmbz2) { if (!BIT(RAM_R(B), 2)) skip = 1; } +INSTRUCTION(skmbz3) { if (!BIT(RAM_R(B), 3)) skip = 1; } /* Input/Output Instructions */ @@ -1097,8 +1035,6 @@ INSTRUCTION(skmbz3) { if (!BIT(RAM_R(B), 3)) skip = 1; return PC + 1; } INSTRUCTION(ing) { A = IN_G(); - - return PC + 1; } /* @@ -1120,8 +1056,6 @@ INSTRUCTION(inl) UINT8 L = IN_L(); RAM_W(B, L >> 4); A = L & 0xF; - - return PC + 1; } /* @@ -1140,8 +1074,6 @@ INSTRUCTION(inl) INSTRUCTION(obd) { OUT_D(B & 0x0f); - - return PC + 1; } /* @@ -1160,8 +1092,6 @@ INSTRUCTION(obd) INSTRUCTION(omg) { WRITE_G(RAM_R(B)); - - return PC + 1; } /* @@ -1185,6 +1115,4 @@ INSTRUCTION(xas) A = t; SKL = C; - - return PC + 1; } diff --git a/src/emu/cpu/cop400/420ops.c b/src/emu/cpu/cop400/420ops.c index e1bafffbcf1..9ae0c8e15a6 100644 --- a/src/emu/cpu/cop400/420ops.c +++ b/src/emu/cpu/cop400/420ops.c @@ -30,8 +30,6 @@ Data Flow: A + 10 -> A - Skip Conditions: None - Description: Add Ten to A */ @@ -39,8 +37,6 @@ INSTRUCTION(adt) { A = (A + 10) & 0x0F; - - return PC + 1; } /* @@ -73,8 +69,6 @@ INSTRUCTION(casc) { C = 0; } - - return PC + 1; } /* Transfer-of-Control Instructions */ @@ -96,8 +90,6 @@ INSTRUCTION(cop420_ret) { POP(); skip = R.last_skip; - - return PC; } /* Memory Reference Instructions */ @@ -112,18 +104,14 @@ INSTRUCTION(cop420_ret) Data Flow: Q7:4 -> RAM(B) Q3:0 -> A - Skip Conditions: None - Description: Copy Q to RAM, A */ INSTRUCTION(cqma) { - RAM_W(B, Q >> 4); + WRITE_M(Q >> 4); A = Q & 0xF; - - return PC + 1; } /* @@ -145,8 +133,6 @@ INSTRUCTION(ldd) UINT8 rd = opcode & 0x3f; A = RAM_R(rd); - - return PC + 1; } /* Register Reference Instructions */ @@ -171,8 +157,6 @@ INSTRUCTION(xabr) A = (B & 0x30) >> 4; B = (Br << 4) + Bd; - - return PC + 1; } /* Test Instructions */ @@ -197,8 +181,6 @@ INSTRUCTION(skt) R.timerlatch = 0; skip = 1; } - - return PC + 1; } /* Input/Output Instructions */ @@ -216,12 +198,7 @@ INSTRUCTION(skt) */ -INSTRUCTION(inin) -{ - A = IN_IN(); - - return PC + 1; -} +INSTRUCTION(inin) { A = IN_IN(); } /* @@ -241,8 +218,6 @@ INSTRUCTION(inin) INSTRUCTION(cop402m_inin) { A = IN_IN() | 0x02; - - return PC + 1; } @@ -264,8 +239,6 @@ INSTRUCTION(inil) // NOT PROPERLY IMPLEMENTED A = (IN_IN() & 0x09) | 0x04; - - return PC + 1; } /* @@ -286,8 +259,6 @@ INSTRUCTION(inil) INSTRUCTION(cop421_inil) { // NOT IMPLEMENTED - - return PC + 1; } /* @@ -309,6 +280,4 @@ INSTRUCTION(ogi) UINT4 y = opcode & 0x0f; WRITE_G(y); - - return PC + 1; } diff --git a/src/emu/cpu/cop400/cop410.c b/src/emu/cpu/cop400/cop410.c index 7435da98835..3c8a6092495 100644 --- a/src/emu/cpu/cop400/cop410.c +++ b/src/emu/cpu/cop400/cop410.c @@ -25,7 +25,7 @@ /* The opcode table now is a combination of cycle counts and function pointers */ typedef struct { unsigned cycles; - UINT16 (*function) (UINT8 opcode); + void (*function) (UINT8 opcode); } s_opcode; #define UINT1 UINT8 @@ -46,11 +46,10 @@ typedef struct UINT9 SA, SB; UINT4 SIO; UINT1 SKL; + UINT8 skip, skipLBI; UINT8 G_mask; UINT8 D_mask; int last_si; - int skip; - int skip_lbi; } COP410_Regs; static COP410_Regs R; @@ -101,6 +100,13 @@ static const s_opcode opcode_23_map[256]= {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal } }; +static void cop410_op23(UINT8 opcode) +{ + UINT8 opcode23 = ROM(PC++); + + (*(opcode_23_map[opcode23].function))(opcode23); +} + static const s_opcode opcode_33_map[256]= { {1, illegal },{1, skgbz0 },{1, illegal },{1, skgbz2 },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, @@ -137,25 +143,31 @@ static const s_opcode opcode_33_map[256]= {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal } }; +static void cop410_op33(UINT8 opcode) +{ + UINT8 opcode33 = ROM(PC++); + + (*(opcode_33_map[opcode33].function))(opcode33); +} + static const s_opcode opcode_map[256]= { {1, clra },{1, skmbz0 },{1, xor },{1, skmbz2 },{1, xis },{1, ld0 },{1, x },{1, xds }, {1, lbi0_9 },{1, lbi0_10 },{1, lbi0_11 },{1, lbi0_12 },{1, lbi0_13 },{1, lbi0_14 },{1, lbi0_15 },{1, lbi0_0 }, {0, illegal },{1, skmbz1 },{0, illegal },{1, skmbz3 },{1, xis },{1, ld1 },{1, x },{1, xds }, {1, lbi1_9 },{1, lbi1_10 },{1, lbi1_11 },{1, lbi1_12 },{1, lbi1_13 },{1, lbi1_14 },{1, lbi1_15 },{1, lbi1_0 }, - {1, skc },{1, ske },{1, sc },{2, illegal },{1, xis },{1, ld2 },{1, x },{1, xds }, + {1, skc },{1, ske },{1, sc },{2, cop410_op23 },{1, xis },{1, ld2 },{1, x },{1, xds }, {1, lbi2_9 },{1, lbi2_10 },{1, lbi2_11 },{1, lbi2_12 },{1, lbi2_13 },{1, lbi2_14 },{1, lbi2_15 },{1, lbi2_0 }, - {1, asc },{1, add },{1, rc },{2, illegal },{1, xis },{1, ld3 },{1, x },{1, xds }, + {1, asc },{1, add },{1, rc },{2, cop410_op33 },{1, xis },{1, ld3 },{1, x },{1, xds }, {1, lbi3_9 },{1, lbi3_10 },{1, lbi3_11 },{1, lbi3_12 },{1, lbi3_13 },{1, lbi3_14 },{1, lbi3_15 },{1, lbi3_0 }, {1, comp },{0, illegal },{1, rmb2 },{1, rmb2 },{1, nop },{1, rmb1 },{1, smb2 },{1, smb1 }, {1, ret },{1, retsk },{0, illegal },{1, smb3 },{1, rmb0 },{1, smb0 },{1, cba },{1, xas }, {1, cab },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc }, {1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc }, {2, jmp },{2, jmp },{0, illegal },{0, illegal },{0, illegal },{0, illegal },{0, illegal },{0, illegal }, - {2, jsr },{2, jsr },{0, illegal },{0, illegal },{0, illegal },{0, illegal },{0, illegal },{0, illegal }, + {2, jsr0 },{2, jsr1 },{0, illegal },{0, illegal },{0, illegal },{0, illegal },{0, illegal },{0, illegal }, {1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii }, {1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii }, - {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, @@ -221,7 +233,7 @@ static void cop410_init(int index, int clock, const void *config, int (*irqcallb state_save_register_item("cop410", index, SIO); state_save_register_item("cop410", index, SKL); state_save_register_item("cop410", index, skip); - state_save_register_item("cop410", index, skip_lbi); + state_save_register_item("cop410", index, skipLBI); state_save_register_item("cop410", index, R.G_mask); state_save_register_item("cop410", index, R.D_mask); state_save_register_item("cop410", index, R.last_si); @@ -256,8 +268,6 @@ static void cop410_reset(void) static int cop410_execute(int cycles) { UINT8 opcode; - UINT16 (*function)(UINT8); - int is_lbi = 0; cop410_ICount = cycles; @@ -265,67 +275,50 @@ static int cop410_execute(int cycles) { prevPC = PC; - // fetch and decode + CALL_DEBUGGER(PC); opcode = ROM(PC); - switch (opcode) + if (skipLBI == 1) { - case 0x23: - opcode = ROM(++PC); - function = opcode_23_map[opcode].function; - break; - - case 0x33: - opcode = ROM(++PC); - function = opcode_33_map[opcode].function; - break; - - default: - function = opcode_map[opcode].function; - is_lbi = LBIops[opcode]; - break; - } - - // skip LBI? - - if (skip_lbi) - { - if (is_lbi) + if (LBIops[opcode] == 0) { - skip = 1; + skipLBI = 0; } - else - { - skip_lbi = 0; - } - } - - if (skip) - { - // skip - - if ((function == lqid) || (function == jid)) - { - cop410_ICount -= 1; - } - else - { + else { cop410_ICount -= opcode_map[opcode].cycles; + + PC += InstLen[opcode]; } - - PC++; - - skip = 0; } - else + + if (skipLBI == 0) { - // execute + int inst_cycles = opcode_map[opcode].cycles; + PC++; + (*(opcode_map[opcode].function))(opcode); + cop410_ICount -= inst_cycles; - CALL_DEBUGGER(PC); + // skip next instruction? - PC = function(opcode); - cop410_ICount -= opcode_map[opcode].cycles; + if (skip == 1) + { + void *function = opcode_map[ROM(PC)].function; + + opcode = ROM(PC); + + if ((function == lqid) || (function == jid)) + { + cop410_ICount -= 1; + } + else + { + cop410_ICount -= opcode_map[opcode].cycles; + } + PC += InstLen[opcode]; + + skip = 0; + } } } while (cop410_ICount > 0); diff --git a/src/emu/cpu/cop400/cop420.c b/src/emu/cpu/cop400/cop420.c index a6fb0ea464d..dde7abc5eb3 100644 --- a/src/emu/cpu/cop400/cop420.c +++ b/src/emu/cpu/cop400/cop420.c @@ -26,7 +26,7 @@ /* The opcode table now is a combination of cycle counts and function pointers */ typedef struct { unsigned cycles; - UINT16 (*function) (UINT8 opcode); + void (*function) (UINT8 opcode); } s_opcode; #define UINT1 UINT8 @@ -47,14 +47,14 @@ typedef struct UINT10 SA, SB, SC; UINT4 SIO; UINT1 SKL; + UINT8 skip, skipLBI; UINT1 timerlatch; UINT16 counter; UINT8 G_mask; UINT8 D_mask; UINT4 IL; int last_si; - int skip, last_skip; - int skip_lbi; + int last_skip; } COP420_Regs; static COP420_Regs R; @@ -81,7 +81,6 @@ static const s_opcode opcode_23_map[256]= {1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd }, {1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd }, {1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd },{1, ldd }, - {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, @@ -90,7 +89,6 @@ static const s_opcode opcode_23_map[256]= {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, - {1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad }, {1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad }, {1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad }, @@ -99,7 +97,6 @@ static const s_opcode opcode_23_map[256]= {1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad }, {1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad }, {1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad },{1, xad }, - {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, @@ -110,6 +107,13 @@ static const s_opcode opcode_23_map[256]= {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal } }; +static void cop420_op23(UINT8 opcode) +{ + UINT8 opcode23 = ROM(PC++); + + (*(opcode_23_map[opcode23].function))(opcode23); +} + static const s_opcode opcode_33_map[256]= { {1, inil },{1, skgbz0 },{1, illegal },{1, skgbz2 },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, @@ -120,7 +124,6 @@ static const s_opcode opcode_33_map[256]= {1, inin },{1, illegal },{1, ing },{1, illegal },{1, cqma },{1, illegal },{1, inl },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, omg },{1, illegal },{1, camq },{1, illegal },{1, obd },{1, illegal }, - {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, ogi },{1, ogi },{1, ogi },{1, ogi },{1, ogi },{1, ogi },{1, ogi },{1, ogi }, @@ -129,7 +132,6 @@ static const s_opcode opcode_33_map[256]= {1, lei },{1, lei },{1, lei },{1, lei },{1, lei },{1, lei },{1, lei },{1, lei }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, - {1, illegal },{1, lbi0_1 },{1, lbi0_2 },{1, lbi0_3 },{1, lbi0_4 },{1, lbi0_5 },{1, lbi0_6 },{1, lbi0_7 }, {1, lbi0_8 },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, lbi1_1 },{1, lbi1_2 },{1, lbi1_3 },{1, lbi1_4 },{1, lbi1_5 },{1, lbi1_6 },{1, lbi1_7 }, @@ -138,7 +140,6 @@ static const s_opcode opcode_33_map[256]= {1, lbi2_8 },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, lbi3_1 },{1, lbi3_2 },{1, lbi3_3 },{1, lbi3_4 },{1, lbi3_5 },{1, lbi3_6 },{1, lbi3_7 }, {1, lbi3_8 },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, - {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, @@ -149,26 +150,31 @@ static const s_opcode opcode_33_map[256]= {1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal },{1, illegal } }; +static void cop420_op33(UINT8 opcode) +{ + UINT8 opcode33 = ROM(PC++); + + (*(opcode_33_map[opcode33].function))(opcode33); +} + static const s_opcode opcode_map[256]= { {1, clra },{1, skmbz0 },{1, xor },{1, skmbz2 },{1, xis },{1, ld0 },{1, x },{1, xds }, {1, lbi0_9 },{1, lbi0_10 },{1, lbi0_11 },{1, lbi0_12 },{1, lbi0_13 },{1, lbi0_14 },{1, lbi0_15 },{1, lbi0_0 }, {1, casc },{1, skmbz1 },{1, xabr },{1, skmbz3 },{1, xis },{1, ld1 },{1, x },{1, xds }, {1, lbi1_9 },{1, lbi1_10 },{1, lbi1_11 },{1, lbi1_12 },{1, lbi1_13 },{1, lbi1_14 },{1, lbi1_15 },{1, lbi1_0 }, - {1, skc },{1, ske },{1, sc },{2, illegal },{1, xis },{1, ld2 },{1, x },{1, xds }, + {1, skc },{1, ske },{1, sc },{2, cop420_op23 },{1, xis },{1, ld2 },{1, x },{1, xds }, {1, lbi2_9 },{1, lbi2_10 },{1, lbi2_11 },{1, lbi2_12 },{1, lbi2_13 },{1, lbi2_14 },{1, lbi2_15 },{1, lbi2_0 }, - {1, asc },{1, add },{1, rc },{2, illegal },{1, xis },{1, ld3 },{1, x },{1, xds }, + {1, asc },{1, add },{1, rc },{2, cop420_op33 },{1, xis },{1, ld3 },{1, x },{1, xds }, {1, lbi3_9 },{1, lbi3_10 },{1, lbi3_11 },{1, lbi3_12 },{1, lbi3_13 },{1, lbi3_14 },{1, lbi3_15 },{1, lbi3_0 }, - {1, comp },{1, skt },{1, rmb2 },{1, rmb3 },{1, nop },{1, rmb1 },{1, smb2 },{1, smb1 }, {1, cop420_ret },{1, retsk },{1, adt },{1, smb3 },{1, rmb0 },{1, smb0 },{1, cba },{1, xas }, {1, cab },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc }, {1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc },{1, aisc }, - {2, jmp },{2, jmp },{2, jmp },{2, jmp },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, - {2, jsr },{2, jsr },{2, jsr },{2, jsr },{1, illegal },{1, illegal },{1, illegal },{1, illegal }, + {2, jmp },{2, jmp },{2, jmp },{2, jmp },{0, illegal },{0, illegal },{0, illegal },{0, illegal }, + {2, jsr0 },{2, jsr1 },{2, jsr2 },{2, jsr3 },{0, illegal },{0, illegal },{0, illegal },{0, illegal }, {1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii }, {1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii },{1, stii }, - {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, @@ -177,7 +183,6 @@ static const s_opcode opcode_map[256]= {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{2, lqid }, - {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, {1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp },{1, jp }, @@ -268,7 +273,7 @@ static void cop420_init(int index, int clock, const void *config, int (*irqcallb state_save_register_item("cop420", index, SIO); state_save_register_item("cop420", index, SKL); state_save_register_item("cop420", index, skip); - state_save_register_item("cop420", index, skip_lbi); + state_save_register_item("cop420", index, skipLBI); state_save_register_item("cop420", index, R.timerlatch); state_save_register_item("cop420", index, R.counter); state_save_register_item("cop420", index, R.G_mask); @@ -307,124 +312,9 @@ static void cop420_reset(void) WRITE_G(0); } -static int cop420_execute(int cycles) -{ - UINT8 opcode; - UINT16 (*function)(UINT8); - int is_lbi = 0; - - cop420_ICount = cycles; - - do - { - prevPC = PC; - - // fetch and decode - - opcode = ROM(PC); - - switch (opcode) - { - case 0x23: - opcode = ROM(++PC); - function = opcode_23_map[opcode].function; - break; - - case 0x33: - opcode = ROM(++PC); - function = opcode_33_map[opcode].function; - is_lbi = LBIops33[opcode]; - break; - - default: - function = opcode_map[opcode].function; - is_lbi = LBIops[opcode]; - break; - } - - // check interrupt - - if (!skip_lbi && BIT(EN, 1)) - { - UINT8 in = IN_IN(); - - if (BIT(IL, 1) && !BIT(in, 1)) - { - if ((function != jp) && (function != jmp) && (function != jsr)) - { - // disable interrupt - - EN &= ~0x02; - - // store skip logic - - R.last_skip = skip; - skip = 0; - - // push next PC - - PUSH(PC + 1); - - // jump to interrupt service routine - - PC = 0x0ff; - - continue; - } - } - - IL = in; - } - - // skip LBI? - - if (skip_lbi) - { - if (is_lbi) - { - skip = 1; - } - else - { - skip_lbi = 0; - } - } - - if (skip) - { - // skip - - if ((function == lqid) || (function == jid)) - { - cop420_ICount -= 1; - } - else - { - cop420_ICount -= opcode_map[opcode].cycles; - } - - PC++; - - skip = 0; - } - else - { - // execute - - CALL_DEBUGGER(PC); - - PC = function(opcode); - cop420_ICount -= opcode_map[opcode].cycles; - } - } while (cop420_ICount > 0); - - return cycles - cop420_ICount; -} - /**************************************************************************** * Execute cycles CPU cycles. Return number of cycles really executed ****************************************************************************/ - /* static int cop420_execute(int cycles) { UINT8 opcode; @@ -439,7 +329,7 @@ static int cop420_execute(int cycles) opcode = ROM(PC); - if (skip_lbi == 1) + if (skipLBI == 1) { int is_lbi = 0; @@ -454,7 +344,7 @@ static int cop420_execute(int cycles) if (is_lbi == 0) { - skip_lbi = 0; + skipLBI = 0; } else { @@ -464,15 +354,15 @@ static int cop420_execute(int cycles) } } - if (skip_lbi == 0) + if (skipLBI == 0) { int inst_cycles = opcode_map[opcode].cycles; - + + PC++; + (*(opcode_map[opcode].function))(opcode); cop420_ICount -= inst_cycles; - PC++; - // check for interrupt if (BIT(EN, 1)) @@ -483,7 +373,7 @@ static int cop420_execute(int cycles) { void *function = opcode_map[ROM(PC)].function; - if ((function != jp) && (function != jmp) && (function != jsr)) + if ((function != jp) && (function != jmp) && (function != jsr0) && (function != jsr1) && (function != jsr2) && (function != jsr3)) { // store skip logic R.last_skip = skip; @@ -519,9 +409,8 @@ static int cop420_execute(int cycles) { cop420_ICount -= opcode_map[opcode].cycles; } - PC += InstLen[opcode]; - + skip = 0; } } @@ -529,7 +418,7 @@ static int cop420_execute(int cycles) return cycles - cop420_ICount; } -*/ + /**************************************************************************** * Get all registers in given buffer ****************************************************************************/ @@ -699,7 +588,7 @@ void cop422_get_info(UINT32 state, cpuinfo *info) } void cop402_get_info(UINT32 state, cpuinfo *info) -{ +{ // COP402 is a ROMless version of the COP420 switch (state) @@ -717,7 +606,7 @@ void cop402_get_info(UINT32 state, cpuinfo *info) } void cop444_get_info(UINT32 state, cpuinfo *info) -{ +{ // COP444 is functionally equivalent to COP420, but with twice the RAM/ROM switch (state) @@ -737,7 +626,7 @@ void cop444_get_info(UINT32 state, cpuinfo *info) } void cop445_get_info(UINT32 state, cpuinfo *info) -{ +{ // COP445 is a 24-pin package version of the COP444, lacking the IN ports switch (state) @@ -754,7 +643,7 @@ void cop445_get_info(UINT32 state, cpuinfo *info) } void cop404_get_info(UINT32 state, cpuinfo *info) -{ +{ // COP404 is a ROMless version of the COP444 switch (state)