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Port Happy's branch-and-link fix from mips3 interpreter to DRC, nw

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therealmogminer@gmail.com 2016-04-12 19:20:06 +02:00
parent 207abac3ed
commit e28147eef5
1 changed files with 16 additions and 7 deletions
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23
src/devices/cpu/mips/mips3drc.cpp
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@ -2331,11 +2331,15 @@ int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler,
case 0x02: /* BLTZL */
case 0x10: /* BLTZAL */
case 0x12: /* BLTZALL */
if (opswitch & 0x10)
{
UML_DMOV(block, R64(31), (INT32)(desc->pc + 8));
}
if (RSREG != 0)
{
UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0
UML_JMPc(block, COND_GE, skip = compiler->labelnum++); // jmp skip,GE
generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
generate_delay_slot_and_branch(block, compiler, desc, 0);
// <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
}
@ -2345,17 +2349,22 @@ int mips3_device::generate_regimm(drcuml_block *block, compiler_state *compiler,
case 0x03: /* BGEZL */
case 0x11: /* BGEZAL */
case 0x13: /* BGEZALL */
if (opswitch & 0x10)
{
UML_DMOV(block, R64(31), (INT32)(desc->pc + 8));
}
if (RSREG != 0)
{
UML_DCMP(block, R64(RSREG), 0); // dcmp <rsreg>,0
UML_JMPc(block, COND_L, skip = compiler->labelnum++); // jmp skip,L
generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
// <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
UML_JMPc(block, COND_L, skip = compiler->labelnum++); // jmp skip,L
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
UML_LABEL(block, skip); // skip:
}
else
generate_delay_slot_and_branch(block, compiler, desc, (opswitch & 0x10) ? 31 : 0);
// <next instruction + hashjmp>
{
generate_delay_slot_and_branch(block, compiler, desc, 0); // <next instruction + hashjmp>
}
return TRUE;
case 0x08: /* TGEI */