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ssystem3: add notes, add i/o (nw)
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@ -75,7 +75,7 @@ void md4330b_device::update_q()
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u32 out = m_shift;
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if (m_tc)
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out = ~out;
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out &= (1 << m_qmax) - 1;
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out &= (u64(1) << m_qmax) - 1;
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m_write_q(0, out);
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}
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@ -3,8 +3,53 @@
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// thanks-to:Berger
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/******************************************************************************
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SciSys / Novag Chess Champion: Super System III (aka MK III), distributed by
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both SciSys and Novag. Which company was responsible for which part of the
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manufacturing chain is unknown. The software is by SciSys (no mention of Novag
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in the ROM, it has "COPYRIGHT SCISYS LTD 1979").
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This is their 1st original product. MK II was licensed from Commodore, and
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MK I was, to put it bluntly, a bootleg. The chess engine is by Mike Johnson,
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with support from David Levy.
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Hardware notes: (main unit)
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- Synertek 6502A @ 2MHz (4MHz XTAL)
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- Synertek 6522
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- 8KB ROM (2*Synertek 2332)
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- 1KB RAM (2*HM472114P-3)
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- MD4332BE + a bunch of TTL for the LCD
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- 13 buttons, 4 switches, no leds or sensorboard
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- connectors for: PSU, Power Pack, Chess Unit, Printer Unit
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Chess Unit:
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- PCB label: Radofin XM-2057-0C
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- Fairchild F6808P CPU @ ?MHz (M6808 compatible)
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- Fairchild F6821P PIA
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- C28A97M 4KB ROM(2332), 128x8 RAM(F6810P)
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- 2*HLCD0438, chessboard LCD
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Printer Unit:
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- unknown hardware, assume own CPU like the chess unit
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PSU ("permanent storage unit"?) is probably just a 256x4 battery-backed RAM
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module, not sure why it was so expensive (~180DM).
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A chess clock accessory was also announced but unreleased.
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SciSys Super System IV is on similar hardware.
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TODO:
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- WIP
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- 6522 ACR register is initialized with 0xe3. Meaning: PA and PB inputs are set
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to latch mode, but the program then never clocks the latch, it functions as if
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it meant to write 0xe0. Maybe 6522 CA1 pin emulation is wrong? Documentation
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says it's edge-triggered, but here it's tied to VCC. I added a trivial hack to
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work around this, see rom defs.
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- 6522 timer runs too fast, currently worked around by clocking it at 1MHz. PB6/PB7
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was measured 997Hz on real device, it's 1989Hz on MAME at 2MHz, both 50% duty cycle.
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- 2nd 7474 /2 clock divider on each 4000-7fff access, this also applies to 6522 clock
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(doesn't affect chess calculation speed, only I/O access, eg. beeper pitch).
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Should be doable to add, but 6522 device doesn't support live clock changes.
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- add chessboard lcd and printer
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******************************************************************************/
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@ -12,7 +57,7 @@ TODO:
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#include "cpu/m6502/m6502.h"
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#include "machine/6522via.h"
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#include "machine/nvram.h"
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#include "machine/timer.h"
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#include "machine/clock.h"
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#include "sound/dac.h"
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#include "sound/volt_reg.h"
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#include "video/md4330b.h"
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@ -33,6 +78,7 @@ public:
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ssystem3_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_via(*this, "via"),
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m_lcd(*this, "lcd"),
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m_display(*this, "display"),
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m_dac(*this, "dac"),
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@ -48,19 +94,42 @@ protected:
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private:
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// devices/pointers
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required_device<cpu_device> m_maincpu;
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required_device<via6522_device> m_via;
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required_device<md4332b_device> m_lcd;
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required_device<pwm_display_device> m_display;
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required_device<dac_bit_interface> m_dac;
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required_ioport_array<4> m_inputs;
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required_ioport_array<4+1> m_inputs;
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// address maps
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void main_map(address_map &map);
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// I/O handlers
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DECLARE_WRITE_LINE_MEMBER(update_lcd);
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DECLARE_WRITE32_MEMBER(lcd_q_w);
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DECLARE_WRITE8_MEMBER(input_w);
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DECLARE_READ8_MEMBER(input_r);
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DECLARE_WRITE8_MEMBER(control_w);
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DECLARE_READ8_MEMBER(control_r);
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u8 m_inp_mux;
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u8 m_control;
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u8 m_shift;
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u32 m_lcd_q;
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};
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void ssystem3_state::machine_start()
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{
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// zerofill
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m_inp_mux = 0;
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m_control = 0;
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m_shift = 0;
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m_lcd_q = 0;
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// register for savestates
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save_item(NAME(m_inp_mux));
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save_item(NAME(m_control));
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save_item(NAME(m_shift));
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save_item(NAME(m_lcd_q));
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}
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@ -69,6 +138,82 @@ void ssystem3_state::machine_start()
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I/O
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******************************************************************************/
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// MD4332B LCD
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WRITE_LINE_MEMBER(ssystem3_state::update_lcd)
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{
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// update on falling edge
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if (!state)
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{
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// temporary
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output().set_value("digit0", m_lcd_q >> 0 & 0xff);
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output().set_value("digit1", m_lcd_q >> 8 & 0xff);
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output().set_value("digit2", m_lcd_q >> 16 & 0xff);
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output().set_value("digit3", m_lcd_q >> 24 & 0xff);
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}
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}
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WRITE32_MEMBER(ssystem3_state::lcd_q_w)
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{
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m_lcd_q = data;
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}
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// 6522 VIA
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WRITE8_MEMBER(ssystem3_state::input_w)
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{
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// PA0-PA7: input mux
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m_inp_mux = ~data;
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}
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READ8_MEMBER(ssystem3_state::input_r)
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{
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u8 data = m_inp_mux;
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// PA1-PA3: multiplexed inputs from PA4-PA7
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// PA0: blocked by diodes
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for (int i = 0; i < 4; i++)
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if (BIT(m_inp_mux, i+4))
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data |= m_inputs[i]->read() & 0xe;
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// PA4-PA7: multiplexed inputs from PA0-PA3
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for (int i = 0; i < 4; i++)
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if (m_inp_mux & m_inputs[i]->read())
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data |= 1 << (i+4);
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return ~data;
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}
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WRITE8_MEMBER(ssystem3_state::control_w)
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{
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// PB0: speaker out
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m_dac->write(~data & m_inputs[4]->read() & 1);
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// PB1: LCD DI
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// PB2: LCD CLK
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m_lcd->di_w(BIT(data, 1));
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m_lcd->clk_w(BIT(data, 2));
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// PB2 also clocks a 4015B
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// DA: LCD DO, DB: Q3A
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if (data & ~m_control & 4)
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m_shift = m_shift << 1 | m_lcd->do_r();
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// PB3: device serial out
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// PB7: tied to PB6 (pulse timer 2)
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m_via->write_pb6(BIT(data, 7));
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m_control = data;
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}
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READ8_MEMBER(ssystem3_state::control_r)
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{
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// PB4: device busy
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// PB5: device attached?
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return 0xff;
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}
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@ -78,9 +223,9 @@ void ssystem3_state::machine_start()
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void ssystem3_state::main_map(address_map &map)
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{
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map(0x0000, 0x03ff).ram();
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map(0x6000, 0x600f).m("via", FUNC(via6522_device::map));
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map(0x8000, 0x9fff).rom().mirror(0x6000);
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map(0x0000, 0x03ff).mirror(0x3c00).ram();
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map(0x6000, 0x600f).mirror(0x1ff0).m(m_via, FUNC(via6522_device::map));
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map(0x8000, 0x9fff).mirror(0x6000).rom();
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}
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@ -91,28 +236,33 @@ void ssystem3_state::main_map(address_map &map)
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static INPUT_PORTS_START( ssystem3 )
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PORT_START("IN.0")
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_1)
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_2)
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_3)
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_4)
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_9) PORT_CODE(KEYCODE_9_PAD) PORT_NAME("9 / EP / C SQ")
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_ENTER) PORT_CODE(KEYCODE_ENTER_PAD) PORT_NAME("Enter")
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_0) PORT_CODE(KEYCODE_0_PAD) PORT_NAME("0 / MD / C Board")
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PORT_START("IN.1")
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_5)
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_6)
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_7)
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_8)
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_UNUSED)
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_6) PORT_CODE(KEYCODE_6_PAD) PORT_CODE(KEYCODE_F) PORT_NAME("F 6 / Knight / Clock")
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_5) PORT_CODE(KEYCODE_5_PAD) PORT_CODE(KEYCODE_E) PORT_CODE(KEYCODE_LEFT) PORT_NAME("E 5 / Bishop / Left")
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_DEL) PORT_CODE(KEYCODE_BACKSPACE) PORT_NAME("CE / Interrupt")
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PORT_START("IN.2")
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Q)
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_W)
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_E)
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_R)
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_N) PORT_NAME("New Game")
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_7) PORT_CODE(KEYCODE_7_PAD) PORT_CODE(KEYCODE_G) PORT_CODE(KEYCODE_RIGHT) PORT_NAME("G 7 / Pawn / Right")
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_4) PORT_CODE(KEYCODE_4_PAD) PORT_CODE(KEYCODE_D) PORT_NAME("D 4 / Rook / #")
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_1) PORT_CODE(KEYCODE_1_PAD) PORT_CODE(KEYCODE_A) PORT_NAME("A 1 / White")
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PORT_START("IN.3")
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_T)
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Y)
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_U)
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_I)
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PORT_BIT(0x01, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_T) PORT_NAME("Time") // not a toggle switch
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PORT_BIT(0x02, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_8) PORT_CODE(KEYCODE_8_PAD) PORT_CODE(KEYCODE_H) PORT_NAME("H 8 / Black")
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PORT_BIT(0x04, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_3) PORT_CODE(KEYCODE_3_PAD) PORT_CODE(KEYCODE_C) PORT_NAME("C 3 / Queen / #50")
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PORT_BIT(0x08, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_2) PORT_CODE(KEYCODE_2_PAD) PORT_CODE(KEYCODE_B) PORT_NAME("B 2 / King / FP")
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PORT_START("IN.4")
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PORT_CONFNAME( 0x01, 0x01, "Sound" )
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PORT_CONFSETTING( 0x00, DEF_STR( Off ) )
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PORT_CONFSETTING( 0x01, DEF_STR( On ) )
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INPUT_PORTS_END
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@ -127,12 +277,22 @@ void ssystem3_state::ssystem3(machine_config &config)
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M6502(config, m_maincpu, 4_MHz_XTAL / 2);
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m_maincpu->set_addrmap(AS_PROGRAM, &ssystem3_state::main_map);
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VIA6522(config, "via", 4_MHz_XTAL / 2);
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VIA6522(config, m_via, 4_MHz_XTAL / 4); // WRONG! should be 2MHz
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m_via->writepa_handler().set(FUNC(ssystem3_state::input_w));
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m_via->readpa_handler().set(FUNC(ssystem3_state::input_r));
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m_via->writepb_handler().set(FUNC(ssystem3_state::control_w));
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m_via->readpb_handler().set(FUNC(ssystem3_state::control_r));
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//NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
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/* video hardware */
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MD4332B(config, m_lcd);
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m_lcd->write_q().set(FUNC(ssystem3_state::lcd_q_w));
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clock_device &tc_clock(CLOCK(config, "tc_clock", 50)); // from power supply
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tc_clock.signal_handler().set(m_lcd, FUNC(md4332b_device::tc_w));
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tc_clock.signal_handler().append(FUNC(ssystem3_state::update_lcd));
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PWM_DISPLAY(config, m_display).set_size(4, 4);
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//config.set_default_layout(layout_saitek_ssystem3);
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@ -152,6 +312,9 @@ ROM_START( ssystem3 )
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ROM_REGION( 0x10000, "maincpu", 0 )
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ROM_LOAD("c19081e_ss-3-lrom.u4", 0x8000, 0x1000, CRC(9ea46ed3) SHA1(34eef85b356efbea6ddac1d1705b104fc8e2731a) ) // 2332
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ROM_LOAD("c19082_ss-3-hrom.u5", 0x9000, 0x1000, CRC(52741e0b) SHA1(2a7b950f9810c5a14a1b9d5e6b2bd93da621662e) ) // "
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// HACK! 6522 ACR register setup
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ROM_FILL(0x946d, 1, 0xe0) // was 0xe3
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ROM_END
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} // anonymous namespace
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