mirror of
https://github.com/holub/mame
synced 2025-10-06 09:00:04 +03:00
v30mz.c: Converted to c++. [Wilbert Pol]
This commit is contained in:
Wilbert Pol
parent
ab27740da1
commit
e2dc17d3bd
4
.gitattributes
vendored
4
.gitattributes
vendored
@ -581,10 +581,6 @@ src/emu/cpu/upd7810/7810ops.c svneol=native#text/plain
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src/emu/cpu/upd7810/7810tbl.c svneol=native#text/plain
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src/emu/cpu/upd7810/upd7810.c svneol=native#text/plain
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src/emu/cpu/upd7810/upd7810.h svneol=native#text/plain
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src/emu/cpu/v30mz/nec.h svneol=native#text/plain
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src/emu/cpu/v30mz/necea.h svneol=native#text/plain
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src/emu/cpu/v30mz/necinstr.h svneol=native#text/plain
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src/emu/cpu/v30mz/necmodrm.h svneol=native#text/plain
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src/emu/cpu/v30mz/v30mz.c svneol=native#text/plain
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src/emu/cpu/v30mz/v30mz.h svneol=native#text/plain
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src/emu/cpu/v60/am.c svneol=native#text/plain
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@ -1298,11 +1298,7 @@ $(CPUOBJ)/nec/v25sfr.o: $(CPUSRC)/nec/v25sfr.c \
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$(CPUSRC)/nec/v25priv.h
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$(CPUOBJ)/v30mz/v30mz.o: $(CPUSRC)/v30mz/v30mz.c \
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$(CPUSRC)/v30mz/v30mz.h \
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$(CPUSRC)/v30mz/necmodrm.h \
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$(CPUSRC)/v30mz/necinstr.h \
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$(CPUSRC)/v30mz/necea.h \
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$(CPUSRC)/v30mz/nec.h
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$(CPUSRC)/v30mz/v30mz.h
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@ -1,23 +0,0 @@
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/* ASG 971222 -- rewrote this interface */
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#ifndef __NECINTRF_H__
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#define __NECINTRF_H__
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typedef struct _nec_config nec_config;
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struct _nec_config
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{
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const UINT8* v25v35_decryptiontable; // internal decryption table
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};
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enum
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{
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NEC_PC=0,
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NEC_IP, NEC_AW, NEC_CW, NEC_DW, NEC_BW, NEC_SP, NEC_BP, NEC_IX, NEC_IY,
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NEC_FLAGS, NEC_ES, NEC_CS, NEC_SS, NEC_DS,
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NEC_VECTOR, NEC_PENDING
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};
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/* Public functions */
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DECLARE_LEGACY_CPU_DEVICE(V30MZ, v30mz);
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#endif /* __NECINTRF_H__ */
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@ -1,56 +0,0 @@
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static unsigned EA_000(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[BW]+cpustate->regs.w[IX]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_001(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[BW]+cpustate->regs.w[IY]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_002(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[BP]+cpustate->regs.w[IX]; cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_003(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[BP]+cpustate->regs.w[IY]; cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_004(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[IX]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_005(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[IY]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_006(v30mz_state *cpustate) { cpustate->eo=FETCH; cpustate->eo+=FETCH<<8; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_007(v30mz_state *cpustate) { cpustate->eo=cpustate->regs.w[BW]; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_100(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[BW]+cpustate->regs.w[IX]+(INT8)FETCH); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_101(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[BW]+cpustate->regs.w[IY]+(INT8)FETCH); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_102(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[BP]+cpustate->regs.w[IX]+(INT8)FETCH); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_103(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[BP]+cpustate->regs.w[IY]+(INT8)FETCH); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_104(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[IX]+(INT8)FETCH); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_105(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[IY]+(INT8)FETCH); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_106(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[BP]+(INT8)FETCH); cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_107(v30mz_state *cpustate) { cpustate->eo=(cpustate->regs.w[BW]+(INT8)FETCH); cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_200(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[BW]+cpustate->regs.w[IX]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_201(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[BW]+cpustate->regs.w[IY]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_202(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[BP]+cpustate->regs.w[IX]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_203(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[BP]+cpustate->regs.w[IY]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_204(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[IX]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_205(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[IY]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_206(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[BP]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(SS)+cpustate->eo; return cpustate->ea; }
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static unsigned EA_207(v30mz_state *cpustate) { cpustate->e16=FETCH; cpustate->e16+=FETCH<<8; cpustate->eo=cpustate->regs.w[BW]+(INT16)cpustate->e16; cpustate->ea=DefaultBase(DS)+cpustate->eo; return cpustate->ea; }
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static unsigned (*const GetEA[192])(v30mz_state *cpustate)={
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_000, EA_001, EA_002, EA_003, EA_004, EA_005, EA_006, EA_007,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_100, EA_101, EA_102, EA_103, EA_104, EA_105, EA_106, EA_107,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207,
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EA_200, EA_201, EA_202, EA_203, EA_204, EA_205, EA_206, EA_207
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};
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@ -1,507 +0,0 @@
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static void i_add_br8(v30mz_state *cpustate);
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static void i_add_wr16(v30mz_state *cpustate);
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static void i_add_r8b(v30mz_state *cpustate);
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static void i_add_r16w(v30mz_state *cpustate);
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static void i_add_ald8(v30mz_state *cpustate);
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static void i_add_axd16(v30mz_state *cpustate);
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static void i_push_es(v30mz_state *cpustate);
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static void i_pop_es(v30mz_state *cpustate);
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static void i_or_br8(v30mz_state *cpustate);
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static void i_or_r8b(v30mz_state *cpustate);
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static void i_or_wr16(v30mz_state *cpustate);
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static void i_or_r16w(v30mz_state *cpustate);
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static void i_or_ald8(v30mz_state *cpustate);
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static void i_or_axd16(v30mz_state *cpustate);
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static void i_push_cs(v30mz_state *cpustate);
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static void i_pre_nec(v30mz_state *cpustate);
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static void i_adc_br8(v30mz_state *cpustate);
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static void i_adc_wr16(v30mz_state *cpustate);
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static void i_adc_r8b(v30mz_state *cpustate);
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static void i_adc_r16w(v30mz_state *cpustate);
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static void i_adc_ald8(v30mz_state *cpustate);
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static void i_adc_axd16(v30mz_state *cpustate);
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static void i_push_ss(v30mz_state *cpustate);
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static void i_pop_ss(v30mz_state *cpustate);
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static void i_sbb_br8(v30mz_state *cpustate);
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static void i_sbb_wr16(v30mz_state *cpustate);
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static void i_sbb_r8b(v30mz_state *cpustate);
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static void i_sbb_r16w(v30mz_state *cpustate);
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static void i_sbb_ald8(v30mz_state *cpustate);
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static void i_sbb_axd16(v30mz_state *cpustate);
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static void i_push_ds(v30mz_state *cpustate);
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static void i_pop_ds(v30mz_state *cpustate);
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static void i_and_br8(v30mz_state *cpustate);
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static void i_and_r8b(v30mz_state *cpustate);
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static void i_and_wr16(v30mz_state *cpustate);
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static void i_and_r16w(v30mz_state *cpustate);
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static void i_and_ald8(v30mz_state *cpustate);
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static void i_and_axd16(v30mz_state *cpustate);
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static void i_es(v30mz_state *cpustate);
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static void i_daa(v30mz_state *cpustate);
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static void i_sub_br8(v30mz_state *cpustate);
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static void i_sub_wr16(v30mz_state *cpustate);
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static void i_sub_r8b(v30mz_state *cpustate);
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static void i_sub_r16w(v30mz_state *cpustate);
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static void i_sub_ald8(v30mz_state *cpustate);
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static void i_sub_axd16(v30mz_state *cpustate);
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static void i_cs(v30mz_state *cpustate);
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static void i_das(v30mz_state *cpustate);
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static void i_xor_br8(v30mz_state *cpustate);
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static void i_xor_r8b(v30mz_state *cpustate);
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static void i_xor_wr16(v30mz_state *cpustate);
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static void i_xor_r16w(v30mz_state *cpustate);
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static void i_xor_ald8(v30mz_state *cpustate);
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static void i_xor_axd16(v30mz_state *cpustate);
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static void i_ss(v30mz_state *cpustate);
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static void i_aaa(v30mz_state *cpustate);
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static void i_cmp_br8(v30mz_state *cpustate);
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static void i_cmp_wr16(v30mz_state *cpustate);
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static void i_cmp_r8b(v30mz_state *cpustate);
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static void i_cmp_r16w(v30mz_state *cpustate);
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static void i_cmp_ald8(v30mz_state *cpustate);
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static void i_cmp_axd16(v30mz_state *cpustate);
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static void i_ds(v30mz_state *cpustate);
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static void i_aas(v30mz_state *cpustate);
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static void i_inc_ax(v30mz_state *cpustate);
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static void i_inc_cx(v30mz_state *cpustate);
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static void i_inc_dx(v30mz_state *cpustate);
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static void i_inc_bx(v30mz_state *cpustate);
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static void i_inc_sp(v30mz_state *cpustate);
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static void i_inc_bp(v30mz_state *cpustate);
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static void i_inc_si(v30mz_state *cpustate);
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static void i_inc_di(v30mz_state *cpustate);
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static void i_dec_ax(v30mz_state *cpustate);
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static void i_dec_cx(v30mz_state *cpustate);
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static void i_dec_dx(v30mz_state *cpustate);
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static void i_dec_bx(v30mz_state *cpustate);
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static void i_dec_sp(v30mz_state *cpustate);
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static void i_dec_bp(v30mz_state *cpustate);
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static void i_dec_si(v30mz_state *cpustate);
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static void i_dec_di(v30mz_state *cpustate);
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static void i_push_ax(v30mz_state *cpustate);
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static void i_push_cx(v30mz_state *cpustate);
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static void i_push_dx(v30mz_state *cpustate);
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static void i_push_bx(v30mz_state *cpustate);
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static void i_push_sp(v30mz_state *cpustate);
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static void i_push_bp(v30mz_state *cpustate);
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static void i_push_si(v30mz_state *cpustate);
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static void i_push_di(v30mz_state *cpustate);
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static void i_pop_ax(v30mz_state *cpustate);
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static void i_pop_cx(v30mz_state *cpustate);
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static void i_pop_dx(v30mz_state *cpustate);
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static void i_pop_bx(v30mz_state *cpustate);
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static void i_pop_sp(v30mz_state *cpustate);
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static void i_pop_bp(v30mz_state *cpustate);
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static void i_pop_si(v30mz_state *cpustate);
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static void i_pop_di(v30mz_state *cpustate);
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static void i_pusha(v30mz_state *cpustate);
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static void i_popa(v30mz_state *cpustate);
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static void i_chkind(v30mz_state *cpustate);
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static void i_repnc(v30mz_state *cpustate);
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static void i_repc(v30mz_state *cpustate);
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static void i_push_d16(v30mz_state *cpustate);
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static void i_imul_d16(v30mz_state *cpustate);
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static void i_push_d8(v30mz_state *cpustate);
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static void i_imul_d8(v30mz_state *cpustate);
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static void i_insb(v30mz_state *cpustate);
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static void i_insw(v30mz_state *cpustate);
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static void i_outsb(v30mz_state *cpustate);
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static void i_outsw(v30mz_state *cpustate);
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static void i_jo(v30mz_state *cpustate);
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static void i_jno(v30mz_state *cpustate);
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static void i_jc(v30mz_state *cpustate);
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static void i_jnc(v30mz_state *cpustate);
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static void i_jz(v30mz_state *cpustate);
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static void i_jnz(v30mz_state *cpustate);
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static void i_jce(v30mz_state *cpustate);
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static void i_jnce(v30mz_state *cpustate);
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static void i_js(v30mz_state *cpustate);
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static void i_jns(v30mz_state *cpustate);
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static void i_jp(v30mz_state *cpustate);
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static void i_jnp(v30mz_state *cpustate);
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static void i_jl(v30mz_state *cpustate);
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static void i_jnl(v30mz_state *cpustate);
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static void i_jle(v30mz_state *cpustate);
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static void i_jnle(v30mz_state *cpustate);
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static void i_80pre(v30mz_state *cpustate);
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static void i_82pre(v30mz_state *cpustate);
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static void i_81pre(v30mz_state *cpustate);
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static void i_83pre(v30mz_state *cpustate);
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static void i_test_br8(v30mz_state *cpustate);
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static void i_test_wr16(v30mz_state *cpustate);
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||||
static void i_xchg_br8(v30mz_state *cpustate);
|
||||
static void i_xchg_wr16(v30mz_state *cpustate);
|
||||
static void i_mov_br8(v30mz_state *cpustate);
|
||||
static void i_mov_r8b(v30mz_state *cpustate);
|
||||
static void i_mov_wr16(v30mz_state *cpustate);
|
||||
static void i_mov_r16w(v30mz_state *cpustate);
|
||||
static void i_mov_wsreg(v30mz_state *cpustate);
|
||||
static void i_lea(v30mz_state *cpustate);
|
||||
static void i_mov_sregw(v30mz_state *cpustate);
|
||||
static void i_invalid(v30mz_state *cpustate);
|
||||
static void i_popw(v30mz_state *cpustate);
|
||||
static void i_nop(v30mz_state *cpustate);
|
||||
static void i_xchg_axcx(v30mz_state *cpustate);
|
||||
static void i_xchg_axdx(v30mz_state *cpustate);
|
||||
static void i_xchg_axbx(v30mz_state *cpustate);
|
||||
static void i_xchg_axsp(v30mz_state *cpustate);
|
||||
static void i_xchg_axbp(v30mz_state *cpustate);
|
||||
static void i_xchg_axsi(v30mz_state *cpustate);
|
||||
static void i_xchg_axdi(v30mz_state *cpustate);
|
||||
static void i_cbw(v30mz_state *cpustate);
|
||||
static void i_cwd(v30mz_state *cpustate);
|
||||
static void i_call_far(v30mz_state *cpustate);
|
||||
static void i_pushf(v30mz_state *cpustate);
|
||||
static void i_popf(v30mz_state *cpustate);
|
||||
static void i_sahf(v30mz_state *cpustate);
|
||||
static void i_lahf(v30mz_state *cpustate);
|
||||
static void i_mov_aldisp(v30mz_state *cpustate);
|
||||
static void i_mov_axdisp(v30mz_state *cpustate);
|
||||
static void i_mov_dispal(v30mz_state *cpustate);
|
||||
static void i_mov_dispax(v30mz_state *cpustate);
|
||||
static void i_movsb(v30mz_state *cpustate);
|
||||
static void i_movsw(v30mz_state *cpustate);
|
||||
static void i_cmpsb(v30mz_state *cpustate);
|
||||
static void i_cmpsw(v30mz_state *cpustate);
|
||||
static void i_test_ald8(v30mz_state *cpustate);
|
||||
static void i_test_axd16(v30mz_state *cpustate);
|
||||
static void i_stosb(v30mz_state *cpustate);
|
||||
static void i_stosw(v30mz_state *cpustate);
|
||||
static void i_lodsb(v30mz_state *cpustate);
|
||||
static void i_lodsw(v30mz_state *cpustate);
|
||||
static void i_scasb(v30mz_state *cpustate);
|
||||
static void i_scasw(v30mz_state *cpustate);
|
||||
static void i_mov_ald8(v30mz_state *cpustate);
|
||||
static void i_mov_cld8(v30mz_state *cpustate);
|
||||
static void i_mov_dld8(v30mz_state *cpustate);
|
||||
static void i_mov_bld8(v30mz_state *cpustate);
|
||||
static void i_mov_ahd8(v30mz_state *cpustate);
|
||||
static void i_mov_chd8(v30mz_state *cpustate);
|
||||
static void i_mov_dhd8(v30mz_state *cpustate);
|
||||
static void i_mov_bhd8(v30mz_state *cpustate);
|
||||
static void i_mov_axd16(v30mz_state *cpustate);
|
||||
static void i_mov_cxd16(v30mz_state *cpustate);
|
||||
static void i_mov_dxd16(v30mz_state *cpustate);
|
||||
static void i_mov_bxd16(v30mz_state *cpustate);
|
||||
static void i_mov_spd16(v30mz_state *cpustate);
|
||||
static void i_mov_bpd16(v30mz_state *cpustate);
|
||||
static void i_mov_sid16(v30mz_state *cpustate);
|
||||
static void i_mov_did16(v30mz_state *cpustate);
|
||||
static void i_rotshft_bd8(v30mz_state *cpustate);
|
||||
static void i_rotshft_wd8(v30mz_state *cpustate);
|
||||
static void i_ret_d16(v30mz_state *cpustate);
|
||||
static void i_ret(v30mz_state *cpustate);
|
||||
static void i_les_dw(v30mz_state *cpustate);
|
||||
static void i_lds_dw(v30mz_state *cpustate);
|
||||
static void i_mov_bd8(v30mz_state *cpustate);
|
||||
static void i_mov_wd16(v30mz_state *cpustate);
|
||||
static void i_enter(v30mz_state *cpustate);
|
||||
static void i_leave(v30mz_state *cpustate);
|
||||
static void i_retf_d16(v30mz_state *cpustate);
|
||||
static void i_retf(v30mz_state *cpustate);
|
||||
static void i_int3(v30mz_state *cpustate);
|
||||
static void i_int(v30mz_state *cpustate);
|
||||
static void i_into(v30mz_state *cpustate);
|
||||
static void i_iret(v30mz_state *cpustate);
|
||||
static void i_rotshft_b(v30mz_state *cpustate);
|
||||
static void i_rotshft_w(v30mz_state *cpustate);
|
||||
static void i_rotshft_bcl(v30mz_state *cpustate);
|
||||
static void i_rotshft_wcl(v30mz_state *cpustate);
|
||||
static void i_aam(v30mz_state *cpustate);
|
||||
static void i_aad(v30mz_state *cpustate);
|
||||
static void i_setalc(v30mz_state *cpustate);
|
||||
static void i_trans(v30mz_state *cpustate);
|
||||
static void i_fpo(v30mz_state *cpustate);
|
||||
static void i_loopne(v30mz_state *cpustate);
|
||||
static void i_loope(v30mz_state *cpustate);
|
||||
static void i_loop(v30mz_state *cpustate);
|
||||
static void i_jcxz(v30mz_state *cpustate);
|
||||
static void i_inal(v30mz_state *cpustate);
|
||||
static void i_inax(v30mz_state *cpustate);
|
||||
static void i_outal(v30mz_state *cpustate);
|
||||
static void i_outax(v30mz_state *cpustate);
|
||||
static void i_call_d16(v30mz_state *cpustate);
|
||||
static void i_jmp_d16(v30mz_state *cpustate);
|
||||
static void i_jmp_far(v30mz_state *cpustate);
|
||||
static void i_jmp_d8(v30mz_state *cpustate);
|
||||
static void i_inaldx(v30mz_state *cpustate);
|
||||
static void i_inaxdx(v30mz_state *cpustate);
|
||||
static void i_outdxal(v30mz_state *cpustate);
|
||||
static void i_outdxax(v30mz_state *cpustate);
|
||||
static void i_lock(v30mz_state *cpustate);
|
||||
static void i_repne(v30mz_state *cpustate);
|
||||
static void i_repe(v30mz_state *cpustate);
|
||||
static void i_hlt(v30mz_state *cpustate);
|
||||
static void i_cmc(v30mz_state *cpustate);
|
||||
static void i_f6pre(v30mz_state *cpustate);
|
||||
static void i_f7pre(v30mz_state *cpustate);
|
||||
static void i_clc(v30mz_state *cpustate);
|
||||
static void i_stc(v30mz_state *cpustate);
|
||||
static void i_di(v30mz_state *cpustate);
|
||||
static void i_ei(v30mz_state *cpustate);
|
||||
static void i_cld(v30mz_state *cpustate);
|
||||
static void i_std(v30mz_state *cpustate);
|
||||
static void i_fepre(v30mz_state *cpustate);
|
||||
static void i_ffpre(v30mz_state *cpustate);
|
||||
|
||||
static void i_wait(v30mz_state *cpustate);
|
||||
|
||||
static void (*const nec_instruction[256])(v30mz_state *cpustate) =
|
||||
{
|
||||
i_add_br8, /* 0x00 */
|
||||
i_add_wr16, /* 0x01 */
|
||||
i_add_r8b, /* 0x02 */
|
||||
i_add_r16w, /* 0x03 */
|
||||
i_add_ald8, /* 0x04 */
|
||||
i_add_axd16, /* 0x05 */
|
||||
i_push_es, /* 0x06 */
|
||||
i_pop_es, /* 0x07 */
|
||||
i_or_br8, /* 0x08 */
|
||||
i_or_wr16, /* 0x09 */
|
||||
i_or_r8b, /* 0x0a */
|
||||
i_or_r16w, /* 0x0b */
|
||||
i_or_ald8, /* 0x0c */
|
||||
i_or_axd16, /* 0x0d */
|
||||
i_push_cs, /* 0x0e */
|
||||
i_pre_nec /* 0x0f */,
|
||||
i_adc_br8, /* 0x10 */
|
||||
i_adc_wr16, /* 0x11 */
|
||||
i_adc_r8b, /* 0x12 */
|
||||
i_adc_r16w, /* 0x13 */
|
||||
i_adc_ald8, /* 0x14 */
|
||||
i_adc_axd16, /* 0x15 */
|
||||
i_push_ss, /* 0x16 */
|
||||
i_pop_ss, /* 0x17 */
|
||||
i_sbb_br8, /* 0x18 */
|
||||
i_sbb_wr16, /* 0x19 */
|
||||
i_sbb_r8b, /* 0x1a */
|
||||
i_sbb_r16w, /* 0x1b */
|
||||
i_sbb_ald8, /* 0x1c */
|
||||
i_sbb_axd16, /* 0x1d */
|
||||
i_push_ds, /* 0x1e */
|
||||
i_pop_ds, /* 0x1f */
|
||||
i_and_br8, /* 0x20 */
|
||||
i_and_wr16, /* 0x21 */
|
||||
i_and_r8b, /* 0x22 */
|
||||
i_and_r16w, /* 0x23 */
|
||||
i_and_ald8, /* 0x24 */
|
||||
i_and_axd16, /* 0x25 */
|
||||
i_es, /* 0x26 */
|
||||
i_daa, /* 0x27 */
|
||||
i_sub_br8, /* 0x28 */
|
||||
i_sub_wr16, /* 0x29 */
|
||||
i_sub_r8b, /* 0x2a */
|
||||
i_sub_r16w, /* 0x2b */
|
||||
i_sub_ald8, /* 0x2c */
|
||||
i_sub_axd16, /* 0x2d */
|
||||
i_cs, /* 0x2e */
|
||||
i_das, /* 0x2f */
|
||||
i_xor_br8, /* 0x30 */
|
||||
i_xor_wr16, /* 0x31 */
|
||||
i_xor_r8b, /* 0x32 */
|
||||
i_xor_r16w, /* 0x33 */
|
||||
i_xor_ald8, /* 0x34 */
|
||||
i_xor_axd16, /* 0x35 */
|
||||
i_ss, /* 0x36 */
|
||||
i_aaa, /* 0x37 */
|
||||
i_cmp_br8, /* 0x38 */
|
||||
i_cmp_wr16, /* 0x39 */
|
||||
i_cmp_r8b, /* 0x3a */
|
||||
i_cmp_r16w, /* 0x3b */
|
||||
i_cmp_ald8, /* 0x3c */
|
||||
i_cmp_axd16, /* 0x3d */
|
||||
i_ds, /* 0x3e */
|
||||
i_aas, /* 0x3f */
|
||||
i_inc_ax, /* 0x40 */
|
||||
i_inc_cx, /* 0x41 */
|
||||
i_inc_dx, /* 0x42 */
|
||||
i_inc_bx, /* 0x43 */
|
||||
i_inc_sp, /* 0x44 */
|
||||
i_inc_bp, /* 0x45 */
|
||||
i_inc_si, /* 0x46 */
|
||||
i_inc_di, /* 0x47 */
|
||||
i_dec_ax, /* 0x48 */
|
||||
i_dec_cx, /* 0x49 */
|
||||
i_dec_dx, /* 0x4a */
|
||||
i_dec_bx, /* 0x4b */
|
||||
i_dec_sp, /* 0x4c */
|
||||
i_dec_bp, /* 0x4d */
|
||||
i_dec_si, /* 0x4e */
|
||||
i_dec_di, /* 0x4f */
|
||||
i_push_ax, /* 0x50 */
|
||||
i_push_cx, /* 0x51 */
|
||||
i_push_dx, /* 0x52 */
|
||||
i_push_bx, /* 0x53 */
|
||||
i_push_sp, /* 0x54 */
|
||||
i_push_bp, /* 0x55 */
|
||||
i_push_si, /* 0x56 */
|
||||
i_push_di, /* 0x57 */
|
||||
i_pop_ax, /* 0x58 */
|
||||
i_pop_cx, /* 0x59 */
|
||||
i_pop_dx, /* 0x5a */
|
||||
i_pop_bx, /* 0x5b */
|
||||
i_pop_sp, /* 0x5c */
|
||||
i_pop_bp, /* 0x5d */
|
||||
i_pop_si, /* 0x5e */
|
||||
i_pop_di, /* 0x5f */
|
||||
i_pusha, /* 0x60 */
|
||||
i_popa, /* 0x61 */
|
||||
i_chkind, /* 0x62 */
|
||||
i_invalid, /* 0x63 */
|
||||
i_repnc, /* 0x64 */
|
||||
i_repc, /* 0x65 */
|
||||
i_invalid, /* 0x66 */
|
||||
i_invalid, /* 0x67 */
|
||||
i_push_d16, /* 0x68 */
|
||||
i_imul_d16, /* 0x69 */
|
||||
i_push_d8, /* 0x6a */
|
||||
i_imul_d8, /* 0x6b */
|
||||
i_insb, /* 0x6c */
|
||||
i_insw, /* 0x6d */
|
||||
i_outsb, /* 0x6e */
|
||||
i_outsw, /* 0x6f */
|
||||
i_jo, /* 0x70 */
|
||||
i_jno, /* 0x71 */
|
||||
i_jc, /* 0x72 */
|
||||
i_jnc, /* 0x73 */
|
||||
i_jz, /* 0x74 */
|
||||
i_jnz, /* 0x75 */
|
||||
i_jce, /* 0x76 */
|
||||
i_jnce, /* 0x77 */
|
||||
i_js, /* 0x78 */
|
||||
i_jns, /* 0x79 */
|
||||
i_jp, /* 0x7a */
|
||||
i_jnp, /* 0x7b */
|
||||
i_jl, /* 0x7c */
|
||||
i_jnl, /* 0x7d */
|
||||
i_jle, /* 0x7e */
|
||||
i_jnle, /* 0x7f */
|
||||
i_80pre, /* 0x80 */
|
||||
i_81pre, /* 0x81 */
|
||||
i_82pre, /* 0x82 */
|
||||
i_83pre, /* 0x83 */
|
||||
i_test_br8, /* 0x84 */
|
||||
i_test_wr16, /* 0x85 */
|
||||
i_xchg_br8, /* 0x86 */
|
||||
i_xchg_wr16, /* 0x87 */
|
||||
i_mov_br8, /* 0x88 */
|
||||
i_mov_wr16, /* 0x89 */
|
||||
i_mov_r8b, /* 0x8a */
|
||||
i_mov_r16w, /* 0x8b */
|
||||
i_mov_wsreg, /* 0x8c */
|
||||
i_lea, /* 0x8d */
|
||||
i_mov_sregw, /* 0x8e */
|
||||
i_popw, /* 0x8f */
|
||||
i_nop, /* 0x90 */
|
||||
i_xchg_axcx, /* 0x91 */
|
||||
i_xchg_axdx, /* 0x92 */
|
||||
i_xchg_axbx, /* 0x93 */
|
||||
i_xchg_axsp, /* 0x94 */
|
||||
i_xchg_axbp, /* 0x95 */
|
||||
i_xchg_axsi, /* 0x97 */
|
||||
i_xchg_axdi, /* 0x97 */
|
||||
i_cbw, /* 0x98 */
|
||||
i_cwd, /* 0x99 */
|
||||
i_call_far, /* 0x9a */
|
||||
i_wait, /* 0x9b */
|
||||
i_pushf, /* 0x9c */
|
||||
i_popf, /* 0x9d */
|
||||
i_sahf, /* 0x9e */
|
||||
i_lahf, /* 0x9f */
|
||||
i_mov_aldisp, /* 0xa0 */
|
||||
i_mov_axdisp, /* 0xa1 */
|
||||
i_mov_dispal, /* 0xa2 */
|
||||
i_mov_dispax, /* 0xa3 */
|
||||
i_movsb, /* 0xa4 */
|
||||
i_movsw, /* 0xa5 */
|
||||
i_cmpsb, /* 0xa6 */
|
||||
i_cmpsw, /* 0xa7 */
|
||||
i_test_ald8, /* 0xa8 */
|
||||
i_test_axd16, /* 0xa9 */
|
||||
i_stosb, /* 0xaa */
|
||||
i_stosw, /* 0xab */
|
||||
i_lodsb, /* 0xac */
|
||||
i_lodsw, /* 0xad */
|
||||
i_scasb, /* 0xae */
|
||||
i_scasw, /* 0xaf */
|
||||
i_mov_ald8, /* 0xb0 */
|
||||
i_mov_cld8, /* 0xb1 */
|
||||
i_mov_dld8, /* 0xb2 */
|
||||
i_mov_bld8, /* 0xb3 */
|
||||
i_mov_ahd8, /* 0xb4 */
|
||||
i_mov_chd8, /* 0xb5 */
|
||||
i_mov_dhd8, /* 0xb6 */
|
||||
i_mov_bhd8, /* 0xb7 */
|
||||
i_mov_axd16, /* 0xb8 */
|
||||
i_mov_cxd16, /* 0xb9 */
|
||||
i_mov_dxd16, /* 0xba */
|
||||
i_mov_bxd16, /* 0xbb */
|
||||
i_mov_spd16, /* 0xbc */
|
||||
i_mov_bpd16, /* 0xbd */
|
||||
i_mov_sid16, /* 0xbe */
|
||||
i_mov_did16, /* 0xbf */
|
||||
i_rotshft_bd8, /* 0xc0 */
|
||||
i_rotshft_wd8, /* 0xc1 */
|
||||
i_ret_d16, /* 0xc2 */
|
||||
i_ret, /* 0xc3 */
|
||||
i_les_dw, /* 0xc4 */
|
||||
i_lds_dw, /* 0xc5 */
|
||||
i_mov_bd8, /* 0xc6 */
|
||||
i_mov_wd16, /* 0xc7 */
|
||||
i_enter, /* 0xc8 */
|
||||
i_leave, /* 0xc9 */
|
||||
i_retf_d16, /* 0xca */
|
||||
i_retf, /* 0xcb */
|
||||
i_int3, /* 0xcc */
|
||||
i_int, /* 0xcd */
|
||||
i_into, /* 0xce */
|
||||
i_iret, /* 0xcf */
|
||||
i_rotshft_b, /* 0xd0 */
|
||||
i_rotshft_w, /* 0xd1 */
|
||||
i_rotshft_bcl, /* 0xd2 */
|
||||
i_rotshft_wcl, /* 0xd3 */
|
||||
i_aam, /* 0xd4 */
|
||||
i_aad, /* 0xd5 */
|
||||
i_setalc,
|
||||
i_trans, /* 0xd7 */
|
||||
i_fpo, /* 0xd8 */
|
||||
i_fpo, /* 0xd9 */
|
||||
i_fpo, /* 0xda */
|
||||
i_fpo, /* 0xdb */
|
||||
i_fpo, /* 0xdc */
|
||||
i_fpo, /* 0xdd */
|
||||
i_fpo, /* 0xde */
|
||||
i_fpo, /* 0xdf */
|
||||
i_loopne, /* 0xe0 */
|
||||
i_loope, /* 0xe1 */
|
||||
i_loop, /* 0xe2 */
|
||||
i_jcxz, /* 0xe3 */
|
||||
i_inal, /* 0xe4 */
|
||||
i_inax, /* 0xe5 */
|
||||
i_outal, /* 0xe6 */
|
||||
i_outax, /* 0xe7 */
|
||||
i_call_d16, /* 0xe8 */
|
||||
i_jmp_d16, /* 0xe9 */
|
||||
i_jmp_far, /* 0xea */
|
||||
i_jmp_d8, /* 0xeb */
|
||||
i_inaldx, /* 0xec */
|
||||
i_inaxdx, /* 0xed */
|
||||
i_outdxal, /* 0xee */
|
||||
i_outdxax, /* 0xef */
|
||||
i_lock, /* 0xf0 */
|
||||
i_invalid, /* 0xf1 */
|
||||
i_repne, /* 0xf2 */
|
||||
i_repe, /* 0xf3 */
|
||||
i_hlt, /* 0xf4 */
|
||||
i_cmc, /* 0xf5 */
|
||||
i_f6pre, /* 0xf6 */
|
||||
i_f7pre, /* 0xf7 */
|
||||
i_clc, /* 0xf8 */
|
||||
i_stc, /* 0xf9 */
|
||||
i_di, /* 0xfa */
|
||||
i_ei, /* 0xfb */
|
||||
i_cld, /* 0xfc */
|
||||
i_std, /* 0xfd */
|
||||
i_fepre, /* 0xfe */
|
||||
i_ffpre /* 0xff */
|
||||
};
|
||||
@ -1,104 +0,0 @@
|
||||
static struct {
|
||||
struct {
|
||||
WREGS w[256];
|
||||
BREGS b[256];
|
||||
} reg;
|
||||
struct {
|
||||
WREGS w[256];
|
||||
BREGS b[256];
|
||||
} RM;
|
||||
} Mod_RM;
|
||||
|
||||
#define RegWord(ModRM) cpustate->regs.w[Mod_RM.reg.w[ModRM]]
|
||||
#define RegByte(ModRM) cpustate->regs.b[Mod_RM.reg.b[ModRM]]
|
||||
|
||||
#define GetRMWord(ModRM) \
|
||||
((ModRM) >= 0xc0 ? cpustate->regs.w[Mod_RM.RM.w[ModRM]] : ( (*GetEA[ModRM])(cpustate), ReadWord( cpustate->ea ) ))
|
||||
|
||||
#define PutbackRMWord(ModRM,val) \
|
||||
{ \
|
||||
if (ModRM >= 0xc0) cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val; \
|
||||
else WriteWord(cpustate->ea,val); \
|
||||
}
|
||||
|
||||
#define GetnextRMWord ReadWord((cpustate->ea&0xf0000)|((cpustate->ea+2)&0xffff))
|
||||
|
||||
#define PutRMWord(ModRM,val) \
|
||||
{ \
|
||||
if (ModRM >= 0xc0) \
|
||||
cpustate->regs.w[Mod_RM.RM.w[ModRM]]=val; \
|
||||
else { \
|
||||
(*GetEA[ModRM])(cpustate); \
|
||||
WriteWord( cpustate->ea ,val); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PutImmRMWord(ModRM) \
|
||||
{ \
|
||||
UINT16 val; \
|
||||
if (ModRM >= 0xc0) \
|
||||
FETCHWORD(cpustate->regs.w[Mod_RM.RM.w[ModRM]]) \
|
||||
else { \
|
||||
(*GetEA[ModRM])(cpustate); \
|
||||
FETCHWORD(val) \
|
||||
WriteWord( cpustate->ea , val); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define GetRMByte(ModRM) \
|
||||
((ModRM) >= 0xc0 ? cpustate->regs.b[Mod_RM.RM.b[ModRM]] : ReadByte( (*GetEA[ModRM])(cpustate) ))
|
||||
|
||||
#define PutRMByte(ModRM,val) \
|
||||
{ \
|
||||
if (ModRM >= 0xc0) \
|
||||
cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val; \
|
||||
else \
|
||||
WriteByte( (*GetEA[ModRM])(cpustate) ,val); \
|
||||
}
|
||||
|
||||
#define PutImmRMByte(ModRM) \
|
||||
{ \
|
||||
if (ModRM >= 0xc0) \
|
||||
cpustate->regs.b[Mod_RM.RM.b[ModRM]]=FETCH; \
|
||||
else { \
|
||||
(*GetEA[ModRM])(cpustate); \
|
||||
WriteByte( cpustate->ea , FETCH ); \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PutbackRMByte(ModRM,val) \
|
||||
{ \
|
||||
if (ModRM >= 0xc0) \
|
||||
cpustate->regs.b[Mod_RM.RM.b[ModRM]]=val; \
|
||||
else \
|
||||
WriteByte(cpustate->ea,val); \
|
||||
}
|
||||
|
||||
#define DEF_br8 \
|
||||
UINT32 ModRM = FETCH,src,dst; \
|
||||
src = RegByte(ModRM); \
|
||||
dst = GetRMByte(ModRM)
|
||||
|
||||
#define DEF_wr16 \
|
||||
UINT32 ModRM = FETCH,src,dst; \
|
||||
src = RegWord(ModRM); \
|
||||
dst = GetRMWord(ModRM)
|
||||
|
||||
#define DEF_r8b \
|
||||
UINT32 ModRM = FETCH,src,dst; \
|
||||
dst = RegByte(ModRM); \
|
||||
src = GetRMByte(ModRM)
|
||||
|
||||
#define DEF_r16w \
|
||||
UINT32 ModRM = FETCH,src,dst; \
|
||||
dst = RegWord(ModRM); \
|
||||
src = GetRMWord(ModRM)
|
||||
|
||||
#define DEF_ald8 \
|
||||
UINT32 src = FETCH; \
|
||||
UINT32 dst = cpustate->regs.b[AL]
|
||||
|
||||
#define DEF_axd16 \
|
||||
UINT32 src = FETCH; \
|
||||
UINT32 dst = cpustate->regs.w[AW]; \
|
||||
src += (FETCH << 8)
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,358 +1,226 @@
|
||||
typedef enum { ES, CS, SS, DS } SREGS;
|
||||
typedef enum { AW, CW, DW, BW, SP, BP, IX, IY } WREGS;
|
||||
|
||||
#define NEC_NMI_INT_VECTOR 2
|
||||
|
||||
typedef enum {
|
||||
AL = NATIVE_ENDIAN_VALUE_LE_BE(0x0, 0x1),
|
||||
AH = NATIVE_ENDIAN_VALUE_LE_BE(0x1, 0x0),
|
||||
CL = NATIVE_ENDIAN_VALUE_LE_BE(0x2, 0x3),
|
||||
CH = NATIVE_ENDIAN_VALUE_LE_BE(0x3, 0x2),
|
||||
DL = NATIVE_ENDIAN_VALUE_LE_BE(0x4, 0x5),
|
||||
DH = NATIVE_ENDIAN_VALUE_LE_BE(0x5, 0x4),
|
||||
BL = NATIVE_ENDIAN_VALUE_LE_BE(0x6, 0x7),
|
||||
BH = NATIVE_ENDIAN_VALUE_LE_BE(0x7, 0x6),
|
||||
SPL = NATIVE_ENDIAN_VALUE_LE_BE(0x8, 0x9),
|
||||
SPH = NATIVE_ENDIAN_VALUE_LE_BE(0x9, 0x8),
|
||||
BPL = NATIVE_ENDIAN_VALUE_LE_BE(0xa, 0xb),
|
||||
BPH = NATIVE_ENDIAN_VALUE_LE_BE(0xb, 0xa),
|
||||
IXL = NATIVE_ENDIAN_VALUE_LE_BE(0xc, 0xd),
|
||||
IXH = NATIVE_ENDIAN_VALUE_LE_BE(0xd, 0xc),
|
||||
IYL = NATIVE_ENDIAN_VALUE_LE_BE(0xe, 0xf),
|
||||
IYH = NATIVE_ENDIAN_VALUE_LE_BE(0xf, 0xe)
|
||||
} BREGS;
|
||||
#ifndef __V30MZ_H__
|
||||
#define __V30MZ_H__
|
||||
|
||||
|
||||
/* parameter x = result, y = source 1, z = source 2 */
|
||||
typedef struct _nec_config nec_config;
|
||||
struct _nec_config
|
||||
{
|
||||
const UINT8* v25v35_decryptiontable; // internal decryption table
|
||||
};
|
||||
|
||||
#define SetTF(x) (cpustate->TF = (x))
|
||||
#define SetIF(x) (cpustate->IF = (x))
|
||||
#define SetDF(x) (cpustate->DF = (x))
|
||||
#define SetMD(x) (cpustate->MF = (x)) /* OB [19.07.99] Mode Flag V30 */
|
||||
|
||||
#define SetCFB(x) (cpustate->CarryVal = (x) & 0x100)
|
||||
#define SetCFW(x) (cpustate->CarryVal = (x) & 0x10000)
|
||||
#define SetAF(x,y,z) (cpustate->AuxVal = ((x) ^ ((y) ^ (z))) & 0x10)
|
||||
#define SetSF(x) (cpustate->SignVal = (x))
|
||||
#define SetZF(x) (cpustate->ZeroVal = (x))
|
||||
#define SetPF(x) (cpustate->ParityVal = (x))
|
||||
|
||||
#define SetSZPF_Byte(x) (cpustate->SignVal=cpustate->ZeroVal=cpustate->ParityVal=(INT8)(x))
|
||||
#define SetSZPF_Word(x) (cpustate->SignVal=cpustate->ZeroVal=cpustate->ParityVal=(INT16)(x))
|
||||
|
||||
#define SetOFW_Add(x,y,z) (cpustate->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x8000)
|
||||
#define SetOFB_Add(x,y,z) (cpustate->OverVal = ((x) ^ (y)) & ((x) ^ (z)) & 0x80)
|
||||
#define SetOFW_Sub(x,y,z) (cpustate->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x8000)
|
||||
#define SetOFB_Sub(x,y,z) (cpustate->OverVal = ((z) ^ (y)) & ((z) ^ (x)) & 0x80)
|
||||
|
||||
#define ADDB { UINT32 res=dst+src; SetCFB(res); SetOFB_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(UINT8)res; }
|
||||
#define ADDW { UINT32 res=dst+src; SetCFW(res); SetOFW_Add(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(UINT16)res; }
|
||||
|
||||
#define SUBB { UINT32 res=dst-src; SetCFB(res); SetOFB_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Byte(res); dst=(UINT8)res; }
|
||||
#define SUBW { UINT32 res=dst-src; SetCFW(res); SetOFW_Sub(res,src,dst); SetAF(res,src,dst); SetSZPF_Word(res); dst=(UINT16)res; }
|
||||
|
||||
#define ORB dst|=src; cpustate->CarryVal=cpustate->OverVal=cpustate->AuxVal=0; SetSZPF_Byte(dst)
|
||||
#define ORW dst|=src; cpustate->CarryVal=cpustate->OverVal=cpustate->AuxVal=0; SetSZPF_Word(dst)
|
||||
|
||||
#define ANDB dst&=src; cpustate->CarryVal=cpustate->OverVal=cpustate->AuxVal=0; SetSZPF_Byte(dst)
|
||||
#define ANDW dst&=src; cpustate->CarryVal=cpustate->OverVal=cpustate->AuxVal=0; SetSZPF_Word(dst)
|
||||
|
||||
#define XORB dst^=src; cpustate->CarryVal=cpustate->OverVal=cpustate->AuxVal=0; SetSZPF_Byte(dst)
|
||||
#define XORW dst^=src; cpustate->CarryVal=cpustate->OverVal=cpustate->AuxVal=0; SetSZPF_Word(dst)
|
||||
|
||||
#define CF (cpustate->CarryVal!=0)
|
||||
#define SF (cpustate->SignVal<0)
|
||||
#define ZF (cpustate->ZeroVal==0)
|
||||
#define PF parity_table[(UINT8)cpustate->ParityVal]
|
||||
#define AF (cpustate->AuxVal!=0)
|
||||
#define OF (cpustate->OverVal!=0)
|
||||
#define MD (cpustate->MF!=0)
|
||||
|
||||
/************************************************************************/
|
||||
|
||||
#define SegBase(Seg) (cpustate->sregs[Seg] << 4)
|
||||
|
||||
#define DefaultBase(Seg) ((cpustate->seg_prefix && (Seg==DS || Seg==SS)) ? cpustate->prefix_base : cpustate->sregs[Seg] << 4)
|
||||
|
||||
#define GetMemB(Seg,Off) ((UINT8)cpustate->program->read_byte((DefaultBase(Seg)+(Off))))
|
||||
#define GetMemW(Seg,Off) ((UINT16) cpustate->program->read_byte((DefaultBase(Seg)+(Off))) + (cpustate->program->read_byte((DefaultBase(Seg)+((Off)+1)))<<8) )
|
||||
|
||||
#define PutMemB(Seg,Off,x) { cpustate->program->write_byte((DefaultBase(Seg)+(Off)),(x)); }
|
||||
#define PutMemW(Seg,Off,x) { PutMemB(Seg,Off,(x)&0xff); PutMemB(Seg,(Off)+1,(UINT8)((x)>>8)); }
|
||||
|
||||
/* Todo: Remove these later - plus readword could overflow */
|
||||
#define ReadByte(ea) ((UINT8)cpustate->program->read_byte((ea)))
|
||||
#define ReadWord(ea) (cpustate->program->read_byte((ea))+(cpustate->program->read_byte(((ea)+1))<<8))
|
||||
#define WriteByte(ea,val) { cpustate->program->write_byte((ea),val); }
|
||||
#define WriteWord(ea,val) { cpustate->program->write_byte((ea),(UINT8)(val)); cpustate->program->write_byte(((ea)+1),(val)>>8); }
|
||||
|
||||
#define read_port(port) cpustate->io->read_byte(port)
|
||||
#define write_port(port,val) cpustate->io->write_byte(port,val)
|
||||
|
||||
#define FETCH (cpustate->direct->read_raw_byte((cpustate->sregs[CS]<<4)+cpustate->ip++))
|
||||
#define FETCHOP (cpustate->direct->read_decrypted_byte((cpustate->sregs[CS]<<4)+cpustate->ip++))
|
||||
#define FETCHWORD(var) { var=cpustate->direct->read_raw_byte((((cpustate->sregs[CS]<<4)+cpustate->ip)))+(cpustate->direct->read_raw_byte((((cpustate->sregs[CS]<<4)+cpustate->ip+1)))<<8); cpustate->ip+=2; }
|
||||
#define PUSH(val) { cpustate->regs.w[SP]-=2; WriteWord((((cpustate->sregs[SS]<<4)+cpustate->regs.w[SP])),val); }
|
||||
#define POP(var) { var = ReadWord((((cpustate->sregs[SS]<<4)+cpustate->regs.w[SP]))); cpustate->regs.w[SP]+=2; }
|
||||
#define PEEK(addr) ((UINT8)cpustate->direct->read_raw_byte(addr))
|
||||
#define PEEKOP(addr) ((UINT8)cpustate->direct->read_decrypted_byte(addr))
|
||||
|
||||
#define GetModRM UINT32 ModRM=cpustate->direct->read_raw_byte((cpustate->sregs[CS]<<4)+cpustate->ip++)
|
||||
|
||||
/* Cycle count macros:
|
||||
CLK - cycle count is the same on all processors
|
||||
CLKS - cycle count differs between processors, list all counts
|
||||
CLKW - cycle count for word read/write differs for odd/even source/destination address
|
||||
CLKM - cycle count for reg/mem instructions
|
||||
CLKR - cycle count for reg/mem instructions with different counts for odd/even addresses
|
||||
enum
|
||||
{
|
||||
NEC_PC=0,
|
||||
NEC_IP, NEC_AW, NEC_CW, NEC_DW, NEC_BW, NEC_SP, NEC_BP, NEC_IX, NEC_IY,
|
||||
NEC_FLAGS, NEC_ES, NEC_CS, NEC_SS, NEC_DS,
|
||||
NEC_VECTOR, NEC_PENDING
|
||||
};
|
||||
|
||||
|
||||
Prefetch & buswait time is not emulated.
|
||||
Extra cycles for PUSH'ing or POP'ing registers to odd addresses is not emulated.
|
||||
*/
|
||||
/////////////////////////////////////////////////////////////////
|
||||
|
||||
#define CLK(v30mz) { cpustate->icount-=v30mz; }
|
||||
#define CLKM(v30mz,v30mzm) { cpustate->icount-=( ModRM >=0xc0 )?v30mz:v30mzm; }
|
||||
extern const device_type V30MZ;
|
||||
|
||||
/************************************************************************/
|
||||
#define CompressFlags() (UINT16)(CF | (PF << 2) | (AF << 4) | (ZF << 6) \
|
||||
| (SF << 7) | (cpustate->TF << 8) | (cpustate->IF << 9) \
|
||||
| (cpustate->DF << 10) | (OF << 11)| (MD << 15))
|
||||
class v30mz_cpu_device : public cpu_device
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
v30mz_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
#define ExpandFlags(f) \
|
||||
{ \
|
||||
cpustate->CarryVal = (f) & 1; \
|
||||
cpustate->ParityVal = !((f) & 4); \
|
||||
cpustate->AuxVal = (f) & 16; \
|
||||
cpustate->ZeroVal = !((f) & 64); \
|
||||
cpustate->SignVal = (f) & 128 ? -1 : 0; \
|
||||
cpustate->TF = ((f) & 256) == 256; \
|
||||
cpustate->IF = ((f) & 512) == 512; \
|
||||
cpustate->DF = ((f) & 1024) == 1024; \
|
||||
cpustate->OverVal = (f) & 2048; \
|
||||
cpustate->MF = ((f) & 0x8000) == 0x8000; \
|
||||
}
|
||||
protected:
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
#define IncWordReg(Reg) \
|
||||
unsigned tmp = (unsigned)cpustate->regs.w[Reg]; \
|
||||
unsigned tmp1 = tmp+1; \
|
||||
cpustate->OverVal = (tmp == 0x7fff); \
|
||||
SetAF(tmp1,tmp,1); \
|
||||
SetSZPF_Word(tmp1); \
|
||||
cpustate->regs.w[Reg]=tmp1
|
||||
// device_execute_interface overrides
|
||||
virtual UINT32 execute_min_cycles() const { return 1; }
|
||||
virtual UINT32 execute_max_cycles() const { return 80; }
|
||||
virtual UINT32 execute_input_lines() const { return 1; }
|
||||
virtual void execute_run();
|
||||
virtual void execute_set_input(int inputnum, int state);
|
||||
|
||||
#define DecWordReg(Reg) \
|
||||
unsigned tmp = (unsigned)cpustate->regs.w[Reg]; \
|
||||
unsigned tmp1 = tmp-1; \
|
||||
cpustate->OverVal = (tmp == 0x8000); \
|
||||
SetAF(tmp1,tmp,1); \
|
||||
SetSZPF_Word(tmp1); \
|
||||
cpustate->regs.w[Reg]=tmp1
|
||||
// device_memory_interface overrides
|
||||
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : NULL ); }
|
||||
|
||||
#define JMP(flag) \
|
||||
int tmp = (int)((INT8)FETCH); \
|
||||
if (flag) \
|
||||
{ \
|
||||
cpustate->ip = (UINT16)(cpustate->ip+tmp); \
|
||||
cpustate->icount-=10; \
|
||||
return; \
|
||||
}
|
||||
// device_state_interface overrides
|
||||
void state_string_export(const device_state_entry &entry, astring &string);
|
||||
|
||||
#define ADJ4(param1,param2) \
|
||||
if (AF || ((cpustate->regs.b[AL] & 0xf) > 9)) \
|
||||
{ \
|
||||
UINT16 tmp; \
|
||||
tmp = cpustate->regs.b[AL] + param1; \
|
||||
cpustate->regs.b[AL] = tmp; \
|
||||
cpustate->AuxVal = 1; \
|
||||
cpustate->CarryVal |= tmp & 0x100; \
|
||||
} \
|
||||
if (CF || (cpustate->regs.b[AL]>0x9f)) \
|
||||
{ \
|
||||
cpustate->regs.b[AL] += param2; \
|
||||
cpustate->CarryVal = 1; \
|
||||
} \
|
||||
SetSZPF_Byte(cpustate->regs.b[AL])
|
||||
// device_disasm_interface overrides
|
||||
virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
|
||||
virtual UINT32 disasm_max_opcode_bytes() const { return 6; }
|
||||
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
|
||||
|
||||
#define ADJB(param1,param2) \
|
||||
if (AF || ((cpustate->regs.b[AL] & 0xf) > 9)) \
|
||||
{ \
|
||||
cpustate->regs.b[AL] += param1; \
|
||||
cpustate->regs.b[AH] += param2; \
|
||||
cpustate->AuxVal = 1; \
|
||||
cpustate->CarryVal = 1; \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
cpustate->AuxVal = 0; \
|
||||
cpustate->CarryVal = 0; \
|
||||
} \
|
||||
cpustate->regs.b[AL] &= 0x0F
|
||||
void interrupt(int int_num);
|
||||
|
||||
#define BITOP_BYTE \
|
||||
ModRM = FETCH; \
|
||||
if (ModRM >= 0xc0) { \
|
||||
tmp=cpustate->regs.b[Mod_RM.RM.b[ModRM]]; \
|
||||
} \
|
||||
else { \
|
||||
(*GetEA[ModRM])(cpustate); \
|
||||
tmp=ReadByte(cpustate->ea); \
|
||||
}
|
||||
inline UINT32 pc();
|
||||
// Accessing memory and io
|
||||
inline UINT8 read_byte(UINT32 addr);
|
||||
inline UINT16 read_word(UINT32 addr);
|
||||
inline void write_byte(UINT32 addr, UINT8 data);
|
||||
inline void write_word(UINT32 addr, UINT16 data);
|
||||
inline UINT8 read_port(UINT16 port);
|
||||
inline void write_port(UINT16 port, UINT8 data);
|
||||
|
||||
#define BITOP_WORD \
|
||||
ModRM = FETCH; \
|
||||
if (ModRM >= 0xc0) { \
|
||||
tmp=cpustate->regs.w[Mod_RM.RM.w[ModRM]]; \
|
||||
} \
|
||||
else { \
|
||||
(*GetEA[ModRM])(cpustate); \
|
||||
tmp=ReadWord(cpustate->ea); \
|
||||
}
|
||||
// Executing instructions
|
||||
inline UINT8 fetch_op();
|
||||
inline UINT8 fetch();
|
||||
inline UINT16 fetch_word();
|
||||
inline UINT8 repx_op();
|
||||
|
||||
#define BIT_NOT \
|
||||
if (tmp & (1<<tmp2)) \
|
||||
tmp &= ~(1<<tmp2); \
|
||||
else \
|
||||
tmp |= (1<<tmp2)
|
||||
// Cycles passed while executing instructions
|
||||
inline void CLK(UINT32 cycles);
|
||||
inline void CLKM(UINT32 cycles_reg, UINT32 cycles_mem);
|
||||
|
||||
#define XchgAWReg(Reg) \
|
||||
UINT16 tmp; \
|
||||
tmp = cpustate->regs.w[Reg]; \
|
||||
cpustate->regs.w[Reg] = cpustate->regs.w[AW]; \
|
||||
cpustate->regs.w[AW] = tmp
|
||||
// Memory handling while executing instructions
|
||||
inline UINT32 default_base(int seg);
|
||||
inline UINT32 get_ea();
|
||||
inline void PutbackRMByte(UINT8 data);
|
||||
inline void PutbackRMWord(UINT16 data);
|
||||
inline void RegByte(UINT8 data);
|
||||
inline void RegWord(UINT16 data);
|
||||
inline UINT8 RegByte();
|
||||
inline UINT16 RegWord();
|
||||
inline UINT16 GetRMWord();
|
||||
inline UINT16 GetnextRMWord();
|
||||
inline UINT8 GetRMByte();
|
||||
inline void PutMemB(int seg, UINT16 offset, UINT8 data);
|
||||
inline void PutMemW(int seg, UINT16 offset, UINT16 data);
|
||||
inline UINT8 GetMemB(int seg, UINT16 offset);
|
||||
inline UINT16 GetMemW(int seg, UINT16 offset);
|
||||
inline void PutImmRMWord();
|
||||
inline void PutRMWord(UINT16 val);
|
||||
inline void PutRMByte(UINT8 val);
|
||||
inline void PutImmRMByte();
|
||||
inline void DEF_br8();
|
||||
inline void DEF_wr16();
|
||||
inline void DEF_r8b();
|
||||
inline void DEF_r16w();
|
||||
inline void DEF_ald8();
|
||||
inline void DEF_axd16();
|
||||
|
||||
#define ROL_BYTE cpustate->CarryVal = dst & 0x80; dst = (dst << 1)+CF
|
||||
#define ROL_WORD cpustate->CarryVal = dst & 0x8000; dst = (dst << 1)+CF
|
||||
#define ROR_BYTE cpustate->CarryVal = dst & 0x1; dst = (dst >> 1)+(CF<<7)
|
||||
#define ROR_WORD cpustate->CarryVal = dst & 0x1; dst = (dst >> 1)+(CF<<15)
|
||||
#define ROLC_BYTE dst = (dst << 1) + CF; SetCFB(dst)
|
||||
#define ROLC_WORD dst = (dst << 1) + CF; SetCFW(dst)
|
||||
#define RORC_BYTE dst = (CF<<8)+dst; cpustate->CarryVal = dst & 0x01; dst >>= 1
|
||||
#define RORC_WORD dst = (CF<<16)+dst; cpustate->CarryVal = dst & 0x01; dst >>= 1
|
||||
#define SHL_BYTE(c) cpustate->icount-=c; dst <<= c; SetCFB(dst); SetSZPF_Byte(dst); PutbackRMByte(ModRM,(UINT8)dst)
|
||||
#define SHL_WORD(c) cpustate->icount-=c; dst <<= c; SetCFW(dst); SetSZPF_Word(dst); PutbackRMWord(ModRM,(UINT16)dst)
|
||||
#define SHR_BYTE(c) cpustate->icount-=c; dst >>= c-1; cpustate->CarryVal = dst & 0x1; dst >>= 1; SetSZPF_Byte(dst); PutbackRMByte(ModRM,(UINT8)dst)
|
||||
#define SHR_WORD(c) cpustate->icount-=c; dst >>= c-1; cpustate->CarryVal = dst & 0x1; dst >>= 1; SetSZPF_Word(dst); PutbackRMWord(ModRM,(UINT16)dst)
|
||||
#define SHRA_BYTE(c) cpustate->icount-=c; dst = ((INT8)dst) >> (c-1); cpustate->CarryVal = dst & 0x1; dst = ((INT8)((UINT8)dst)) >> 1; SetSZPF_Byte(dst); PutbackRMByte(ModRM,(UINT8)dst)
|
||||
#define SHRA_WORD(c) cpustate->icount-=c; dst = ((INT16)dst) >> (c-1); cpustate->CarryVal = dst & 0x1; dst = ((INT16)((UINT16)dst)) >> 1; SetSZPF_Word(dst); PutbackRMWord(ModRM,(UINT16)dst)
|
||||
// Flags
|
||||
inline void set_CFB(UINT32 x);
|
||||
inline void set_CFW(UINT32 x);
|
||||
inline void set_AF(UINT32 x,UINT32 y,UINT32 z);
|
||||
inline void set_SF(UINT32 x);
|
||||
inline void set_ZF(UINT32 x);
|
||||
inline void set_PF(UINT32 x);
|
||||
inline void set_SZPF_Byte(UINT32 x);
|
||||
inline void set_SZPF_Word(UINT32 x);
|
||||
inline void set_OFW_Add(UINT32 x,UINT32 y,UINT32 z);
|
||||
inline void set_OFB_Add(UINT32 x,UINT32 y,UINT32 z);
|
||||
inline void set_OFW_Sub(UINT32 x,UINT32 y,UINT32 z);
|
||||
inline void set_OFB_Sub(UINT32 x,UINT32 y,UINT32 z);
|
||||
inline UINT16 CompressFlags();
|
||||
inline void ExpandFlags(UINT16 f);
|
||||
|
||||
#define DIVUB \
|
||||
uresult = cpustate->regs.w[AW]; \
|
||||
uresult2 = uresult % tmp; \
|
||||
if ((uresult /= tmp) > 0xff) { \
|
||||
nec_interrupt(cpustate,0); break; \
|
||||
} else { \
|
||||
cpustate->regs.b[AL] = uresult; \
|
||||
cpustate->regs.b[AH] = uresult2; \
|
||||
}
|
||||
// rep instructions
|
||||
inline void i_insb();
|
||||
inline void i_insw();
|
||||
inline void i_outsb();
|
||||
inline void i_outsw();
|
||||
inline void i_movsb();
|
||||
inline void i_movsw();
|
||||
inline void i_cmpsb();
|
||||
inline void i_cmpsw();
|
||||
inline void i_stosb();
|
||||
inline void i_stosw();
|
||||
inline void i_lodsb();
|
||||
inline void i_lodsw();
|
||||
inline void i_scasb();
|
||||
inline void i_scasw();
|
||||
inline void i_popf();
|
||||
|
||||
#define DIVB \
|
||||
result = (INT16)cpustate->regs.w[AW]; \
|
||||
result2 = result % (INT16)((INT8)tmp); \
|
||||
if ((result /= (INT16)((INT8)tmp)) > 0xff) { \
|
||||
nec_interrupt(cpustate,0); break; \
|
||||
} else { \
|
||||
cpustate->regs.b[AL] = result; \
|
||||
cpustate->regs.b[AH] = result2; \
|
||||
}
|
||||
// sub implementations
|
||||
inline void ADDB();
|
||||
inline void ADDW();
|
||||
inline void SUBB();
|
||||
inline void SUBW();
|
||||
inline void ORB();
|
||||
inline void ORW();
|
||||
inline void ANDB();
|
||||
inline void ANDW();
|
||||
inline void XORB();
|
||||
inline void XORW();
|
||||
inline void ROL_BYTE();
|
||||
inline void ROL_WORD();
|
||||
inline void ROR_BYTE();
|
||||
inline void ROR_WORD();
|
||||
inline void ROLC_BYTE();
|
||||
inline void ROLC_WORD();
|
||||
inline void RORC_BYTE();
|
||||
inline void RORC_WORD();
|
||||
inline void SHL_BYTE(UINT8 c);
|
||||
inline void SHL_WORD(UINT8 c);
|
||||
inline void SHR_BYTE(UINT8 c);
|
||||
inline void SHR_WORD(UINT8 c);
|
||||
inline void SHRA_BYTE(UINT8 c);
|
||||
inline void SHRA_WORD(UINT8 c);
|
||||
inline void XchgAWReg(UINT8 reg);
|
||||
inline void IncWordReg(UINT8 reg);
|
||||
inline void DecWordReg(UINT8 reg);
|
||||
inline void PUSH(UINT16 data);
|
||||
inline UINT16 POP();
|
||||
inline void JMP(bool cond);
|
||||
inline void ADJ4(INT8 param1, INT8 param2);
|
||||
inline void ADJB(INT8 param1, INT8 param2);
|
||||
|
||||
#define DIVUW \
|
||||
uresult = (((UINT32)cpustate->regs.w[DW]) << 16) | cpustate->regs.w[AW];\
|
||||
uresult2 = uresult % tmp; \
|
||||
if ((uresult /= tmp) > 0xffff) { \
|
||||
nec_interrupt(cpustate,0); break; \
|
||||
} else { \
|
||||
cpustate->regs.w[AW]=uresult; \
|
||||
cpustate->regs.w[DW]=uresult2; \
|
||||
}
|
||||
protected:
|
||||
address_space_config m_program_config;
|
||||
address_space_config m_io_config;
|
||||
|
||||
#define DIVW \
|
||||
result = ((UINT32)cpustate->regs.w[DW] << 16) + cpustate->regs.w[AW]; \
|
||||
result2 = result % (INT32)((INT16)tmp); \
|
||||
if ((result /= (INT32)((INT16)tmp)) > 0xffff) { \
|
||||
nec_interrupt(cpustate,0); break; \
|
||||
} else { \
|
||||
cpustate->regs.w[AW]=result; \
|
||||
cpustate->regs.w[DW]=result2; \
|
||||
}
|
||||
union
|
||||
{ /* eight general registers */
|
||||
UINT16 w[8]; /* viewed as 16 bits registers */
|
||||
UINT8 b[16]; /* or as 8 bit registers */
|
||||
} m_regs;
|
||||
UINT16 m_sregs[4];
|
||||
|
||||
#define ADD4S { \
|
||||
int i,v1,v2,result; \
|
||||
int count = (cpustate->regs.b[CL]+1)/2; \
|
||||
unsigned di = cpustate->regs.w[IY]; \
|
||||
unsigned si = cpustate->regs.w[IX]; \
|
||||
if (cpustate->seg_prefix) logerror("%06x: Warning: seg_prefix defined for add4s\n",PC(cpustate)); \
|
||||
cpustate->ZeroVal = cpustate->CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
cpustate->icount-=19; \
|
||||
tmp = GetMemB(DS, si); \
|
||||
tmp2 = GetMemB(ES, di); \
|
||||
v1 = (tmp>>4)*10 + (tmp&0xf); \
|
||||
v2 = (tmp2>>4)*10 + (tmp2&0xf); \
|
||||
result = v1+v2+cpustate->CarryVal; \
|
||||
cpustate->CarryVal = result > 99 ? 1 : 0; \
|
||||
result = result % 100; \
|
||||
v1 = ((result/10)<<4) | (result % 10); \
|
||||
PutMemB(ES, di,v1); \
|
||||
if (v1) cpustate->ZeroVal = 1; \
|
||||
si++; \
|
||||
di++; \
|
||||
} \
|
||||
}
|
||||
UINT16 m_ip;
|
||||
|
||||
#define SUB4S { \
|
||||
int count = (cpustate->regs.b[CL]+1)/2; \
|
||||
int i,v1,v2,result; \
|
||||
unsigned di = cpustate->regs.w[IY]; \
|
||||
unsigned si = cpustate->regs.w[IX]; \
|
||||
if (cpustate->seg_prefix) logerror("%06x: Warning: seg_prefix defined for sub4s\n",PC(cpustate)); \
|
||||
cpustate->ZeroVal = cpustate->CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
cpustate->icount-=19; \
|
||||
tmp = GetMemB(ES, di); \
|
||||
tmp2 = GetMemB(DS, si); \
|
||||
v1 = (tmp>>4)*10 + (tmp&0xf); \
|
||||
v2 = (tmp2>>4)*10 + (tmp2&0xf); \
|
||||
if (v1 < (v2+cpustate->CarryVal)) { \
|
||||
v1+=100; \
|
||||
result = v1-(v2+cpustate->CarryVal); \
|
||||
cpustate->CarryVal = 1; \
|
||||
} else { \
|
||||
result = v1-(v2+cpustate->CarryVal); \
|
||||
cpustate->CarryVal = 0; \
|
||||
} \
|
||||
v1 = ((result/10)<<4) | (result % 10); \
|
||||
PutMemB(ES, di,v1); \
|
||||
if (v1) cpustate->ZeroVal = 1; \
|
||||
si++; \
|
||||
di++; \
|
||||
} \
|
||||
}
|
||||
INT32 m_SignVal;
|
||||
UINT32 m_AuxVal, m_OverVal, m_ZeroVal, m_CarryVal, m_ParityVal; /* 0 or non-0 valued flags */
|
||||
UINT8 m_TF, m_IF, m_DF, m_MF; /* 0 or 1 valued flags */ /* OB[19.07.99] added Mode Flag V30 */
|
||||
UINT32 m_int_vector;
|
||||
UINT32 m_pending_irq;
|
||||
UINT32 m_nmi_state;
|
||||
UINT32 m_irq_state;
|
||||
UINT8 m_no_interrupt;
|
||||
UINT8 m_fire_trap;
|
||||
|
||||
#define CMP4S { \
|
||||
int count = (cpustate->regs.b[CL]+1)/2; \
|
||||
int i,v1,v2,result; \
|
||||
unsigned di = cpustate->regs.w[IY]; \
|
||||
unsigned si = cpustate->regs.w[IX]; \
|
||||
if (cpustate->seg_prefix) logerror("%06x: Warning: seg_prefix defined for cmp4s\n",PC(cpustate)); \
|
||||
cpustate->ZeroVal = cpustate->CarryVal = 0; \
|
||||
for (i=0;i<count;i++) { \
|
||||
cpustate->icount-=19; \
|
||||
tmp = GetMemB(ES, di); \
|
||||
tmp2 = GetMemB(DS, si); \
|
||||
v1 = (tmp>>4)*10 + (tmp&0xf); \
|
||||
v2 = (tmp2>>4)*10 + (tmp2&0xf); \
|
||||
if (v1 < (v2+cpustate->CarryVal)) { \
|
||||
v1+=100; \
|
||||
result = v1-(v2+cpustate->CarryVal); \
|
||||
cpustate->CarryVal = 1; \
|
||||
} else { \
|
||||
result = v1-(v2+cpustate->CarryVal); \
|
||||
cpustate->CarryVal = 0; \
|
||||
} \
|
||||
v1 = ((result/10)<<4) | (result % 10); \
|
||||
if (v1) cpustate->ZeroVal = 1; \
|
||||
si++; \
|
||||
di++; \
|
||||
} \
|
||||
}
|
||||
device_irq_acknowledge_callback m_irq_callback;
|
||||
address_space *m_program;
|
||||
direct_read_data *m_direct;
|
||||
address_space *m_io;
|
||||
int m_icount;
|
||||
|
||||
UINT32 m_prefix_base; /* base address of the latest prefix segment */
|
||||
bool m_seg_prefix; /* prefix segment indicator */
|
||||
bool m_seg_prefix_next; /* prefix segment for next instruction */
|
||||
|
||||
UINT32 m_ea;
|
||||
UINT16 m_eo;
|
||||
UINT16 m_e16;
|
||||
|
||||
// Used during execution of instructions
|
||||
UINT8 m_modrm;
|
||||
UINT32 m_dst;
|
||||
UINT32 m_src;
|
||||
UINT32 m_pc;
|
||||
|
||||
// Lookup tables
|
||||
UINT8 m_parity_table[256];
|
||||
struct {
|
||||
struct {
|
||||
int w[256];
|
||||
int b[256];
|
||||
} reg;
|
||||
struct {
|
||||
int w[256];
|
||||
int b[256];
|
||||
} RM;
|
||||
} m_Mod_RM;
|
||||
};
|
||||
|
||||
|
||||
#endif /* __V30MZ_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user