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https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
dectalk comment consolidation and clarification, and removed speculation (n/w)
This commit is contained in:
Lord-Nightmare
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f3108058b1
commit
e3c70ce502
@ -135,29 +135,8 @@ DTC-01 LEDs
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* It will then write currently loaded settings to nvram and execute a store, so do it after the defaults are loaded
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* $1a7ae - default nvram image, without checksum (0x80 bytes)
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*******************************************************************************/
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/*the 68k memory map is such:
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0x000000-0x007fff: E22 low, E8 high
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0x008000-0x00ffff: E21 low, E7 high
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0x010000-0x017fff: E20 low, E6 high
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0x018000-0x01ffff: E19 low, E5 high
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0x020000-0x027fff: E18 low, E4 high
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0x028000-0x02ffff: E17 low, E3 high
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0x030000-0x037fff: E16 low, E2 high
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0x038000-0x03ffff: E15 low, E1 high
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mirrrored at 0x040000-0x07ffff
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ram/nvram/speech mapping:
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0x080000-0x083fff: e36 low, e49 high
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0x084000-0x087fff: e35 low, e48 high
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0x088000-0x08bfff: e34 low, e47 high
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0x08c000-0x08ffff: e33 low, e46 high
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0x090000-0x093fff: e32 low, e45 high
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0x094000-0x097fff: LED/SW/NVR
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0x098000-0x09bfff: 2681 DUART
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0x09c000-0x09ffff: DTMF and TMS32010 (TLC, SPC)
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mirrored at 0x0a0000-0x0fffff x3
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entire space mirrored at 0x100000-0x7fffff
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0x800000-0xffffff is open bus?
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/*
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interrupts:
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68k has an interrupt priority decoder attached to it:
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TLC is INT level 4
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@ -784,9 +763,19 @@ READ_LINE_MEMBER(dectalk_state::spc_semaphore_r)// Return state of d-latch 74ls7
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Address maps (x = ignored; * = selects address within this range)
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68k address map:
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a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 (a0 via UDS/LDS)
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0 x x x 0 x * * * * * * * * * * * * * * * * * * R ROM
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0 x x x 1 x x 0 * * * * * * * * * * * * * * * * RW RAM (first 4 chip pairs)
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0 x x x 1 x x 1 0 0 * * * * * * * * * * * * * * RW RAM (last chip pair)
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0 x x x 0 x 0 0 0 * * * * * * * * * * * * * * a R ROM a=0:E8, a=1:E22
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0 x x x 0 x 0 0 1 * * * * * * * * * * * * * * a R ROM E7,E21
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0 x x x 0 x 0 1 0 * * * * * * * * * * * * * * a R ROM E6,E20
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0 x x x 0 x 0 1 1 * * * * * * * * * * * * * * a R ROM E5,E19
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0 x x x 0 x 1 0 0 * * * * * * * * * * * * * * a R ROM E4,E18
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0 x x x 0 x 1 0 1 * * * * * * * * * * * * * * a R ROM E3,E17
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0 x x x 0 x 1 1 0 * * * * * * * * * * * * * * a R ROM E2,E16
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0 x x x 0 x 1 1 1 * * * * * * * * * * * * * * a R ROM E1,E15
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0 x x x 1 x x 0 0 0 * * * * * * * * * * * * * a RW RAM E36,E49
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0 x x x 1 x x 0 0 1 * * * * * * * * * * * * * a RW RAM E35,E48
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0 x x x 1 x x 0 1 0 * * * * * * * * * * * * * a RW RAM E34,E47
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0 x x x 1 x x 0 1 1 * * * * * * * * * * * * * a RW RAM E33,E46
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0 x x x 1 x x 1 0 0 * * * * * * * * * * * * * a RW RAM E32,E45
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0 x x x 1 x x 1 0 1 x x x x x x x x x x x x x 0 W Status LED <d7-d0>
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0 x x x 1 x x 1 0 1 x x x x 0 * * * * * * * * 1 RW NVRAM (read/write volatile ram, does not store to eeprom)
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0 x x x 1 x x 1 0 1 x x x x 1 * * * * * * * * 1 RW NVRAM (all reads do /recall from eeprom, all writes do /store to eeprom)
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@ -795,6 +784,7 @@ a23 a22 a21 a20 a19 a18 a17 a16 a15 a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4
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0 x x x 1 x x 1 1 1 x x x x x x x x x x x 0 1 0? W SPC fifo write (clocks fifo)
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0 x x x 1 x x 1 1 1 x x x x x x x x x x x 1 0 * RW TLC flags: ring detect (readonly, d15), ring detected irq enable (readwrite, d14), answer phone (readwrite, d8), tone detected (readonly, d7), tone detected irq enable (readwrite, d6) [see schematic sheet 6]
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0 x x x 1 x x 1 1 1 x x x x x x x x x x x 1 1 * R TLC tone chip read, reads on bits d0-d7 only, d4-d7 are tied low; d15-d8 are probably open bus
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1 x x x x x x x x x x x x x x x x x x x x x x x OPEN BUS
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*/
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@ -961,13 +951,6 @@ ROM_START( dectalk )
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ROMX_LOAD("23-106e5.e1", 0x38000, 0x4000, CRC(a389ab31) SHA1(355348bfc96a04193136cdde3418366e6476c3ca), ROM_SKIP(1) | ROM_BIOS(1)) // Label: "SP8510106E5" @ E1
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ROMX_LOAD("23-098e5.e15", 0x38001, 0x4000, CRC(3d8910e7) SHA1(01921e77b46c2d4845023605239c45ffa4a35872), ROM_SKIP(1) | ROM_BIOS(1)) // Label: "SP8510098E5" @ E15
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/* the undumped 2.0 (beta?) version likely has roms:
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23-091e5.e22, 23-092e5.e21, 23-093e5.e20, 23-094e5.e19,
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23-099e5.e8, 23-100e5.e7, 23-101e5.e6, 23-102e5.e5
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and shares the 23-103e5 thru 106e5, and 095e5 thru 098e5 roms with
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the 2.0 version above
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*/
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// DECtalk DTC-01 firmware v1.8 (first half: 05Dec83 tag; second half: 11Oct83 tag), all roms are 27128 eproms
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ROM_SYSTEM_BIOS( 1, "v18", "DTC-01 Version 1.8")
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ROMX_LOAD("23-063e5.e8", 0x00000, 0x4000, CRC(9f5ca045) SHA1(1b1b9c1e092c44329b385fb04001e13422eb8d39), ROM_SKIP(1) | ROM_BIOS(2))
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@ -988,18 +971,16 @@ ROM_START( dectalk )
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ROMX_LOAD("23-037e5.e15", 0x38001, 0x4000, CRC(d62ab309) SHA1(a743a23625feadf6e46ef889e2bb04af88589992), ROM_SKIP(1) | ROM_BIOS(2))
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ROM_REGION(0x2000,"dsp", 0)
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// NEWER/final? firmware 'later 2.0'; this firmware DOES WORK.
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// Final? firmware from 2.0 dectalk firmware units; this firmware clips with the 1.8 dectalk firmware
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// this firmware seems to have some leftover test garbage mapped into its space, which is not present on the dtc-01 board
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// it writes 0x0000 to 0x90 on start
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// it writes a sequence of values to 0xFF down to 0xE9
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// it wants something readable mapped at 0x08 or else it waits for an interrupt
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// Is this the same firmware as on the tms320P15 on the dtc-07 or a backported variant of such?
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// it writes 0x0000 to 0x90 on start, and it writes a sequence of values to 0xFF down to 0xE9
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// it also wants something readable mapped at 0x08 (for debug purposes?) or else it waits for an interrupt (as the older firmware always does)
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ROM_LOAD16_BYTE("23-410f4.e70", 0x000, 0x800, CRC(121e2ec3) SHA1(3fabe018d0e0b478093951cb20501853358faa18))
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ROM_LOAD16_BYTE("23-409f4.e69", 0x001, 0x800, CRC(61f67c79) SHA1(9a13426c92f879f2953f180f805990a91c37ac43))
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// DECtalk DTC-01 'klsyn' tms32010 firmware 'earlier 2.0', both proms are 82s191 equivalent; this firmware DOES WORK.
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// older dsp firmware from earlier dectalk firmware 2.0 units, both proms are 82s191 equivalent; this firmware clips with the 1.8 dectalk firmware
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ROM_LOAD16_BYTE("23-205f4.e70", 0x000, 0x800, CRC(ed76a3ad) SHA1(3136bae243ef48721e21c66fde70dab5fc3c21d0)) // Label: "LM8506205F4 // M1-76161-5" @ E70
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ROM_LOAD16_BYTE("23-204f4.e69", 0x001, 0x800, CRC(79bb54ff) SHA1(9409f90f7a397b041e4440341f2d7934cb479285)) // Label: "LM8504204F4 // 78S191" @ E69
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// older dsp firmware from dectalk firmware 1.8; this firmware DOES WORK, and even works with 2.0 dectalk firmware! its a bit quieter than the others, though.
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// older dsp firmware from dectalk firmware 1.8 units; while this firmware works with 2.0 dectalk firmware, its a bit quieter than the proper one.
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ROM_LOAD16_BYTE("23-166f4.e70", 0x000, 0x800, CRC(2d036ffc) SHA1(e8c25ca092dde2dc0aec73921af806026bdfbbc3)) // HM1-76161-5
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ROM_LOAD16_BYTE("23-165f4.e69", 0x001, 0x800, CRC(a3019ca4) SHA1(249f269c38f7f44edb6d025bcc867c8ca0de3e9c)) // HM1-76161-5
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