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"Pointer"-ified the 6502

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* a perfect candidate for a code merge. Replication all over the place.
This commit is contained in:
Couriersud 2008-11-07 00:07:57 +00:00
parent 42c486632b
commit e4550f0b66
17 changed files with 697 additions and 609 deletions
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308
src/emu/cpu/m6502/m4510.c
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@ -120,9 +120,9 @@ z: xxxx address bits a19 .. a16 for memory accesses with a15 1 ?
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
typedef struct {
void (*const *insn)(void); /* pointer to the function pointer table */
typedef struct _m4510_Regs m4510_Regs;
struct _m4510_Regs {
void (*const *insn)(m4510_Regs *); /* pointer to the function pointer table */
PAIR ppc; /* previous program counter */
PAIR pc; /* program counter */
PAIR sp; /* stack pointer (always 100 - 1FF) */
@ -141,8 +141,11 @@ typedef struct {
UINT8 irq_state;
UINT16 low, high;
UINT32 mem[8];
cpu_irq_callback irq_callback;
const device_config *device;
int icount;
read8_machine_func rdmem_id; /* readmem callback for indexed instructions */
write8_machine_func wrmem_id; /* writemem callback for indexed instructions */
@ -150,46 +153,58 @@ typedef struct {
UINT8 port;
UINT8 (*port_read)(void);
void (*port_write)(UINT8 data);
} m4510_Regs;
};
static int m4510_ICount = 0;
static m4510_Regs m4510;
static void *token;
/***************************************************************
* include the opcode macros, functions and tables
***************************************************************/
INLINE int m4510_cpu_readop(void)
INLINE int m4510_cpu_readop(m4510_Regs *m4510)
{
register UINT16 t=m4510.pc.w.l++;
register UINT16 t=m4510->pc.w.l++;
return cpu_readop(M4510_MEM(t));
}
INLINE int m4510_cpu_readop_arg(void)
INLINE int m4510_cpu_readop_arg(m4510_Regs *m4510)
{
register UINT16 t=m4510.pc.w.l++;
register UINT16 t=m4510->pc.w.l++;
return cpu_readop_arg(M4510_MEM(t));
}
#define M4510
#include "t65ce02.c"
static READ8_HANDLER( default_rdmem_id ) { return program_read_byte_8le(M4510_MEM(offset)); }
static WRITE8_HANDLER( default_wrmem_id ) { program_write_byte_8le(M4510_MEM(offset), data); }
static READ8_HANDLER( default_rdmem_id )
{
m4510_Regs *m4510 = token;
return program_read_byte_8le(M4510_MEM(offset));
}
static WRITE8_HANDLER( default_wrmem_id )
{
m4510_Regs *m4510 = token;
program_write_byte_8le(M4510_MEM(offset), data);
}
static CPU_INIT( m4510 )
{
m4510.interrupt_inhibit = 0;
m4510.rdmem_id = default_rdmem_id;
m4510.wrmem_id = default_wrmem_id;
m4510.irq_callback = irqcallback;
m4510.device = device;
m4510_Regs *m4510 = device->token;
token = device->token;
m4510->interrupt_inhibit = 0;
m4510->rdmem_id = default_rdmem_id;
m4510->wrmem_id = default_wrmem_id;
m4510->irq_callback = irqcallback;
m4510->device = device;
}
static CPU_RESET( m4510 )
{
m4510.insn = insn4510;
m4510_Regs *m4510 = device->token;
m4510->insn = insn4510;
/* wipe out the rest of the m65ce02 structure */
/* read the reset vector into PC */
@ -198,23 +213,23 @@ static CPU_RESET( m4510 )
PCH = RDMEM(M4510_RST_VEC+1);
/* after reset in 6502 compatibility mode */
m4510.sp.d = 0x01ff; /* high byte descriped in databook */
m4510.z = 0;
m4510->sp.d = 0x01ff; /* high byte descriped in databook */
m4510->z = 0;
B = 0;
m4510.p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
m4510.interrupt_inhibit = 0;
m4510.pending_irq = 0; /* nonzero if an IRQ is pending */
m4510.after_cli = 0; /* pending IRQ and last insn cleared I */
m4510.irq_callback = NULL;
m4510->p = F_E|F_B|F_I|F_Z; /* set E, I and Z flags */
m4510->interrupt_inhibit = 0;
m4510->pending_irq = 0; /* nonzero if an IRQ is pending */
m4510->after_cli = 0; /* pending IRQ and last insn cleared I */
m4510->irq_callback = NULL;
/* don't know */
m4510.high=0x8200;
m4510.mem[7]=0x20000;
m4510->high=0x8200;
m4510->mem[7]=0x20000;
CHANGE_PC;
m4510.port = 0xff;
m4510.ddr = 0x00;
m4510->port = 0xff;
m4510->ddr = 0x00;
}
static CPU_EXIT( m4510 )
@ -224,26 +239,26 @@ static CPU_EXIT( m4510 )
static void m4510_get_context (void *dst)
{
if( dst )
*(m4510_Regs*)dst = m4510;
}
static void m4510_set_context (void *src)
{
m4510_Regs *m4510;
if( src )
{
m4510 = *(m4510_Regs*)src;
token = src;
m4510 = token;
CHANGE_PC;
}
}
INLINE void m4510_take_irq(void)
INLINE void m4510_take_irq(m4510_Regs *m4510)
{
if(( !(P & F_I) ) && (m4510.interrupt_inhibit == 0))
if(( !(P & F_I) ) && (m4510->interrupt_inhibit == 0))
{
EAD = M4510_IRQ_VEC;
m4510_ICount -= 7;
m4510->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -252,15 +267,17 @@ INLINE void m4510_take_irq(void)
PCH = RDMEM(EAD+1);
LOG(("M4510#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m4510.irq_callback) (*m4510.irq_callback)(m4510.device, 0);
if (m4510->irq_callback) (*m4510->irq_callback)(m4510->device, 0);
CHANGE_PC;
}
m4510.pending_irq = 0;
m4510->pending_irq = 0;
}
static CPU_EXECUTE( m4510 )
{
m4510_ICount = cycles;
m4510_Regs *m4510 = token;
m4510->icount = cycles;
CHANGE_PC;
@ -272,21 +289,21 @@ static CPU_EXECUTE( m4510 )
debugger_instruction_hook(Machine, PCD);
/* if an irq is pending, take it now */
if( m4510.pending_irq )
m4510_take_irq();
if( m4510->pending_irq )
m4510_take_irq(m4510);
op = RDOP();
(*insn4510[op])();
(*insn4510[op])(m4510);
/* check if the I flag was just reset (interrupts enabled) */
if( m4510.after_cli )
if( m4510->after_cli )
{
LOG(("M4510#%d after_cli was >0", cpu_getactivecpu()));
m4510.after_cli = 0;
if (m4510.irq_state != CLEAR_LINE)
m4510->after_cli = 0;
if (m4510->irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m4510.pending_irq = 1;
m4510->pending_irq = 1;
}
else
{
@ -294,25 +311,25 @@ static CPU_EXECUTE( m4510 )
}
}
else
if( m4510.pending_irq )
m4510_take_irq();
if( m4510->pending_irq )
m4510_take_irq(m4510);
} while (m4510_ICount > 0);
} while (m4510->icount > 0);
return cycles - m4510_ICount;
return cycles - m4510->icount;
}
static void m4510_set_irq_line(int irqline, int state)
static void m4510_set_irq_line(m4510_Regs *m4510, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m4510.nmi_state == state) return;
m4510.nmi_state = state;
if (m4510->nmi_state == state) return;
m4510->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(("M4510#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M4510_NMI_VEC;
m4510_ICount -= 7;
m4510->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -325,33 +342,34 @@ static void m4510_set_irq_line(int irqline, int state)
}
else
{
m4510.irq_state = state;
m4510->irq_state = state;
if( state != CLEAR_LINE )
{
LOG(("M4510#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m4510.pending_irq = 1;
m4510->pending_irq = 1;
}
}
}
static UINT8 m4510_get_port(void)
static UINT8 m4510_get_port(m4510_Regs *m4510)
{
return (m4510.port & m4510.ddr) | (m4510.ddr ^ 0xff);
return (m4510->port & m4510->ddr) | (m4510->ddr ^ 0xff);
}
static READ8_HANDLER( m4510_read_0000 )
{
UINT8 result = 0x00;
m4510_Regs *m4510 = token;
switch(offset)
{
case 0x0000: /* DDR */
result = m4510.ddr;
result = m4510->ddr;
break;
case 0x0001: /* Data Port */
if (m4510.port_read)
result = m4510.port_read();
result = (m4510.ddr & m4510.port) | (~m4510.ddr & result);
if (m4510->port_read)
result = m4510->port_read();
result = (m4510->ddr & m4510->port) | (~m4510->ddr & result);
break;
}
return result;
@ -359,18 +377,20 @@ static READ8_HANDLER( m4510_read_0000 )
static WRITE8_HANDLER( m4510_write_0000 )
{
m4510_Regs *m4510 = token;
switch(offset)
{
case 0x0000: /* DDR */
m4510.ddr = data;
m4510->ddr = data;
break;
case 0x0001: /* Data Port */
m4510.port = data;
m4510->port = data;
break;
}
if (m4510.port_write)
m4510.port_write(m4510_get_port());
if (m4510->port_write)
m4510->port_write(m4510_get_port(m4510));
}
static ADDRESS_MAP_START(m4510_mem, ADDRESS_SPACE_PROGRAM, 8)
@ -379,6 +399,8 @@ ADDRESS_MAP_END
static int m4510_translate(int space, int intention, offs_t *addr)
{
m4510_Regs *m4510 = token;
if (space == ADDRESS_SPACE_PROGRAM)
*addr = M4510_MEM(*addr);
return TRUE;
@ -390,40 +412,42 @@ static int m4510_translate(int space, int intention, offs_t *addr)
static void m4510_set_info(UINT32 state, cpuinfo *info)
{
m4510_Regs *m4510 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: m4510_set_irq_line(M4510_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m4510_set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: m4510_set_irq_line(m4510, M4510_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m4510_set_irq_line(m4510, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_REGISTER + M4510_PC: m4510.pc.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_PC: m4510->pc.w.l = info->i; break;
case CPUINFO_INT_SP: SPL = info->i; break;
case CPUINFO_INT_REGISTER + M4510_S: m4510.sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_P: m4510.p = info->i; break;
case CPUINFO_INT_REGISTER + M4510_A: m4510.a = info->i; break;
case CPUINFO_INT_REGISTER + M4510_X: m4510.x = info->i; break;
case CPUINFO_INT_REGISTER + M4510_Y: m4510.y = info->i; break;
case CPUINFO_INT_REGISTER + M4510_Z: m4510.z = info->i; break;
case CPUINFO_INT_REGISTER + M4510_B: m4510.zp.b.h = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM_LOW: m4510.low = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM_HIGH: m4510.high = info->i; break;
case CPUINFO_INT_REGISTER + M4510_EA: m4510.ea.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_ZP: m4510.zp.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM0: m4510.mem[0] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM1: m4510.mem[1] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM2: m4510.mem[2] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM3: m4510.mem[3] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM4: m4510.mem[4] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM5: m4510.mem[5] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM6: m4510.mem[6] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM7: m4510.mem[7] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_S: m4510->sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_P: m4510->p = info->i; break;
case CPUINFO_INT_REGISTER + M4510_A: m4510->a = info->i; break;
case CPUINFO_INT_REGISTER + M4510_X: m4510->x = info->i; break;
case CPUINFO_INT_REGISTER + M4510_Y: m4510->y = info->i; break;
case CPUINFO_INT_REGISTER + M4510_Z: m4510->z = info->i; break;
case CPUINFO_INT_REGISTER + M4510_B: m4510->zp.b.h = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM_LOW: m4510->low = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM_HIGH: m4510->high = info->i; break;
case CPUINFO_INT_REGISTER + M4510_EA: m4510->ea.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_ZP: m4510->zp.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM0: m4510->mem[0] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM1: m4510->mem[1] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM2: m4510->mem[2] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM3: m4510->mem[3] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM4: m4510->mem[4] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM5: m4510->mem[5] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM6: m4510->mem[6] = info->i; break;
case CPUINFO_INT_REGISTER + M4510_MEM7: m4510->mem[7] = info->i; break;
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: m4510.rdmem_id = (read8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: m4510.wrmem_id = (write8_machine_func) info->f; break;
case CPUINFO_PTR_M6510_PORTREAD: m4510.port_read = (UINT8 (*)(void)) info->f; break;
case CPUINFO_PTR_M6510_PORTWRITE: m4510.port_write = (void (*)(UINT8)) info->f; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: m4510->rdmem_id = (read8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: m4510->wrmem_id = (write8_machine_func) info->f; break;
case CPUINFO_PTR_M6510_PORTREAD: m4510->port_read = (UINT8 (*)(void)) info->f; break;
case CPUINFO_PTR_M6510_PORTWRITE: m4510->port_write = (void (*)(UINT8)) info->f; break;
}
}
@ -435,6 +459,8 @@ static void m4510_set_info(UINT32 state, cpuinfo *info)
void m4510_get_info(UINT32 state, cpuinfo *info)
{
m4510_Regs *m4510 = token;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
@ -461,34 +487,34 @@ void m4510_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: info->i = m4510.irq_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = m4510.nmi_state; break;
case CPUINFO_INT_INPUT_STATE + M4510_IRQ_LINE: info->i = m4510->irq_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = m4510->nmi_state; break;
case CPUINFO_INT_PREVIOUSPC: info->i = m4510.ppc.w.l; break;
case CPUINFO_INT_PREVIOUSPC: info->i = m4510->ppc.w.l; break;
case CPUINFO_INT_PC: info->i = PCD; break;
case CPUINFO_INT_REGISTER + M4510_PC: info->i = m4510.pc.w.l; break;
case CPUINFO_INT_REGISTER + M4510_PC: info->i = m4510->pc.w.l; break;
case CPUINFO_INT_SP: info->i = SPL; break;
case CPUINFO_INT_REGISTER + M4510_S: info->i = m4510.sp.b.l; break;
case CPUINFO_INT_REGISTER + M4510_P: info->i = m4510.p; break;
case CPUINFO_INT_REGISTER + M4510_A: info->i = m4510.a; break;
case CPUINFO_INT_REGISTER + M4510_X: info->i = m4510.x; break;
case CPUINFO_INT_REGISTER + M4510_Y: info->i = m4510.y; break;
case CPUINFO_INT_REGISTER + M4510_Z: info->i = m4510.z; break;
case CPUINFO_INT_REGISTER + M4510_B: info->i = m4510.zp.b.h; break;
case CPUINFO_INT_REGISTER + M4510_MEM_LOW: info->i = m4510.low; break;
case CPUINFO_INT_REGISTER + M4510_MEM_HIGH: info->i = m4510.high; break;
case CPUINFO_INT_REGISTER + M4510_EA: info->i = m4510.ea.w.l; break;
case CPUINFO_INT_REGISTER + M4510_ZP: info->i = m4510.zp.w.l; break;
case CPUINFO_INT_REGISTER + M4510_MEM0: info->i = m4510.mem[0]; break;
case CPUINFO_INT_REGISTER + M4510_MEM1: info->i = m4510.mem[1]; break;
case CPUINFO_INT_REGISTER + M4510_MEM2: info->i = m4510.mem[2]; break;
case CPUINFO_INT_REGISTER + M4510_MEM3: info->i = m4510.mem[3]; break;
case CPUINFO_INT_REGISTER + M4510_MEM4: info->i = m4510.mem[4]; break;
case CPUINFO_INT_REGISTER + M4510_MEM5: info->i = m4510.mem[5]; break;
case CPUINFO_INT_REGISTER + M4510_MEM6: info->i = m4510.mem[6]; break;
case CPUINFO_INT_REGISTER + M4510_MEM7: info->i = m4510.mem[7]; break;
case CPUINFO_INT_M6510_PORT: info->i = m4510_get_port(); break;
case CPUINFO_INT_REGISTER + M4510_S: info->i = m4510->sp.b.l; break;
case CPUINFO_INT_REGISTER + M4510_P: info->i = m4510->p; break;
case CPUINFO_INT_REGISTER + M4510_A: info->i = m4510->a; break;
case CPUINFO_INT_REGISTER + M4510_X: info->i = m4510->x; break;
case CPUINFO_INT_REGISTER + M4510_Y: info->i = m4510->y; break;
case CPUINFO_INT_REGISTER + M4510_Z: info->i = m4510->z; break;
case CPUINFO_INT_REGISTER + M4510_B: info->i = m4510->zp.b.h; break;
case CPUINFO_INT_REGISTER + M4510_MEM_LOW: info->i = m4510->low; break;
case CPUINFO_INT_REGISTER + M4510_MEM_HIGH: info->i = m4510->high; break;
case CPUINFO_INT_REGISTER + M4510_EA: info->i = m4510->ea.w.l; break;
case CPUINFO_INT_REGISTER + M4510_ZP: info->i = m4510->zp.w.l; break;
case CPUINFO_INT_REGISTER + M4510_MEM0: info->i = m4510->mem[0]; break;
case CPUINFO_INT_REGISTER + M4510_MEM1: info->i = m4510->mem[1]; break;
case CPUINFO_INT_REGISTER + M4510_MEM2: info->i = m4510->mem[2]; break;
case CPUINFO_INT_REGISTER + M4510_MEM3: info->i = m4510->mem[3]; break;
case CPUINFO_INT_REGISTER + M4510_MEM4: info->i = m4510->mem[4]; break;
case CPUINFO_INT_REGISTER + M4510_MEM5: info->i = m4510->mem[5]; break;
case CPUINFO_INT_REGISTER + M4510_MEM6: info->i = m4510->mem[6]; break;
case CPUINFO_INT_REGISTER + M4510_MEM7: info->i = m4510->mem[7]; break;
case CPUINFO_INT_M6510_PORT: info->i = m4510_get_port(m4510); break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = m4510_set_info; break;
@ -500,13 +526,13 @@ void m4510_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(m4510); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = m4510_dasm; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m4510_ICount; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m4510->icount; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP: info->internal_map8 = address_map_m4510_mem; break;
case CPUINFO_PTR_TRANSLATE: info->translate = m4510_translate; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m4510.rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m4510.wrmem_id; break;
case CPUINFO_PTR_M6510_PORTREAD: info->f = (genf *) m4510.port_read; break;
case CPUINFO_PTR_M6510_PORTWRITE: info->f = (genf *) m4510.port_write; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m4510->rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m4510->wrmem_id; break;
case CPUINFO_PTR_M6510_PORTREAD: info->f = (genf *) m4510->port_read; break;
case CPUINFO_PTR_M6510_PORTWRITE: info->f = (genf *) m4510->port_write; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "M4510"); break;
@ -517,28 +543,28 @@ void m4510_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c",
m4510.p & 0x80 ? 'N':'.',
m4510.p & 0x40 ? 'V':'.',
m4510.p & 0x20 ? 'R':'.',
m4510.p & 0x10 ? 'B':'.',
m4510.p & 0x08 ? 'D':'.',
m4510.p & 0x04 ? 'I':'.',
m4510.p & 0x02 ? 'Z':'.',
m4510.p & 0x01 ? 'C':'.');
m4510->p & 0x80 ? 'N':'.',
m4510->p & 0x40 ? 'V':'.',
m4510->p & 0x20 ? 'R':'.',
m4510->p & 0x10 ? 'B':'.',
m4510->p & 0x08 ? 'D':'.',
m4510->p & 0x04 ? 'I':'.',
m4510->p & 0x02 ? 'Z':'.',
m4510->p & 0x01 ? 'C':'.');
break;
case CPUINFO_STR_REGISTER + M4510_PC: sprintf(info->s, "PC:%04X", m4510.pc.w.l); break;
case CPUINFO_STR_REGISTER + M4510_S: sprintf(info->s, "S:%02X", m4510.sp.b.l); break;
case CPUINFO_STR_REGISTER + M4510_P: sprintf(info->s, "P:%02X", m4510.p); break;
case CPUINFO_STR_REGISTER + M4510_A: sprintf(info->s, "A:%02X", m4510.a); break;
case CPUINFO_STR_REGISTER + M4510_X: sprintf(info->s, "X:%02X", m4510.x); break;
case CPUINFO_STR_REGISTER + M4510_Y: sprintf(info->s, "Y:%02X", m4510.y); break;
case CPUINFO_STR_REGISTER + M4510_Z: sprintf(info->s, "Z:%02X", m4510.z); break;
case CPUINFO_STR_REGISTER + M4510_B: sprintf(info->s, "B:%02X", m4510.zp.b.h); break;
case CPUINFO_STR_REGISTER + M4510_MEM_LOW: sprintf(info->s, "M0:%01X", m4510.low); break;
case CPUINFO_STR_REGISTER + M4510_MEM_HIGH: sprintf(info->s, "M1:%01X", m4510.high); break;
case CPUINFO_STR_REGISTER + M4510_EA: sprintf(info->s, "EA:%04X", m4510.ea.w.l); break;
case CPUINFO_STR_REGISTER + M4510_ZP: sprintf(info->s, "ZP:%03X", m4510.zp.w.l); break;
case CPUINFO_STR_REGISTER + M4510_PC: sprintf(info->s, "PC:%04X", m4510->pc.w.l); break;
case CPUINFO_STR_REGISTER + M4510_S: sprintf(info->s, "S:%02X", m4510->sp.b.l); break;
case CPUINFO_STR_REGISTER + M4510_P: sprintf(info->s, "P:%02X", m4510->p); break;
case CPUINFO_STR_REGISTER + M4510_A: sprintf(info->s, "A:%02X", m4510->a); break;
case CPUINFO_STR_REGISTER + M4510_X: sprintf(info->s, "X:%02X", m4510->x); break;
case CPUINFO_STR_REGISTER + M4510_Y: sprintf(info->s, "Y:%02X", m4510->y); break;
case CPUINFO_STR_REGISTER + M4510_Z: sprintf(info->s, "Z:%02X", m4510->z); break;
case CPUINFO_STR_REGISTER + M4510_B: sprintf(info->s, "B:%02X", m4510->zp.b.h); break;
case CPUINFO_STR_REGISTER + M4510_MEM_LOW: sprintf(info->s, "M0:%01X", m4510->low); break;
case CPUINFO_STR_REGISTER + M4510_MEM_HIGH: sprintf(info->s, "M1:%01X", m4510->high); break;
case CPUINFO_STR_REGISTER + M4510_EA: sprintf(info->s, "EA:%04X", m4510->ea.w.l); break;
case CPUINFO_STR_REGISTER + M4510_ZP: sprintf(info->s, "ZP:%03X", m4510->zp.w.l); break;
}
}

412
src/emu/cpu/m6502/m6502.c
View File

@ -53,10 +53,11 @@
/****************************************************************************
* The 6502 registers.
****************************************************************************/
typedef struct
typedef struct _m6502_Regs m6502_Regs;
struct _m6502_Regs
{
UINT8 subtype; /* currently selected cpu sub type */
void (*const *insn)(void); /* pointer to the function pointer table */
void (*const *insn)(m6502_Regs *); /* pointer to the function pointer table */
PAIR ppc; /* previous program counter */
PAIR pc; /* program counter */
PAIR sp; /* stack pointer (always 100 - 1FF) */
@ -71,8 +72,12 @@ typedef struct
UINT8 nmi_state;
UINT8 irq_state;
UINT8 so_state;
cpu_irq_callback irq_callback;
const device_config *device;
int int_occured;
int icount;
read8_machine_func rdmem_id; /* readmem callback for indexed instructions */
write8_machine_func wrmem_id; /* writemem callback for indexed instructions */
@ -83,12 +88,11 @@ typedef struct
void (*port_write)(UINT8 direction, UINT8 data);
#endif
} m6502_Regs;
};
static int m6502_IntOccured = 0;
static int m6502_ICount = 0;
static m6502_Regs m6502;
static void *token;
//static m6502_Regs *m6502;
static READ8_HANDLER( default_rdmem_id ) { return program_read_byte_8le(offset); }
static WRITE8_HANDLER( default_wdmem_id ) { program_write_byte_8le(offset, data); }
@ -128,33 +132,36 @@ static WRITE8_HANDLER( default_wdmem_id ) { program_write_byte_8le(offset, data)
*
*****************************************************************************/
static void m6502_common_init(const device_config *device, int index, int clock, const void *config, cpu_irq_callback irqcallback, UINT8 subtype, void (*const *insn)(void), const char *type)
static void m6502_common_init(const device_config *device, int index, int clock, const void *config, cpu_irq_callback irqcallback, UINT8 subtype, void (*const *insn)(m6502_Regs *m6502), const char *type)
{
memset(&m6502, 0, sizeof(m6502));
m6502.irq_callback = irqcallback;
m6502.device = device;
m6502.subtype = subtype;
m6502.insn = insn;
m6502.rdmem_id = default_rdmem_id;
m6502.wrmem_id = default_wdmem_id;
m6502_Regs *m6502 = device->token;
state_save_register_item(type, index, m6502.pc.w.l);
state_save_register_item(type, index, m6502.sp.w.l);
state_save_register_item(type, index, m6502.p);
state_save_register_item(type, index, m6502.a);
state_save_register_item(type, index, m6502.x);
state_save_register_item(type, index, m6502.y);
state_save_register_item(type, index, m6502.pending_irq);
state_save_register_item(type, index, m6502.after_cli);
state_save_register_item(type, index, m6502.nmi_state);
state_save_register_item(type, index, m6502.irq_state);
state_save_register_item(type, index, m6502.so_state);
token = device->token; // temporary
m6502->irq_callback = irqcallback;
m6502->device = device;
m6502->subtype = subtype;
m6502->insn = insn;
m6502->rdmem_id = default_rdmem_id;
m6502->wrmem_id = default_wdmem_id;
state_save_register_item(type, index, m6502->pc.w.l);
state_save_register_item(type, index, m6502->sp.w.l);
state_save_register_item(type, index, m6502->p);
state_save_register_item(type, index, m6502->a);
state_save_register_item(type, index, m6502->x);
state_save_register_item(type, index, m6502->y);
state_save_register_item(type, index, m6502->pending_irq);
state_save_register_item(type, index, m6502->after_cli);
state_save_register_item(type, index, m6502->nmi_state);
state_save_register_item(type, index, m6502->irq_state);
state_save_register_item(type, index, m6502->so_state);
#if (HAS_M6510) || (HAS_M6510T) || (HAS_M8502) || (HAS_M7501)
if (subtype == SUBTYPE_6510)
{
state_save_register_item(type, index, m6502.port);
state_save_register_item(type, index, m6502.ddr);
state_save_register_item(type, index, m6502->port);
state_save_register_item(type, index, m6502->ddr);
}
#endif
}
@ -166,17 +173,18 @@ static CPU_INIT( m6502 )
static CPU_RESET( m6502 )
{
m6502_Regs *m6502 = device->token;
/* wipe out the rest of the m6502 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6502_RST_VEC);
PCH = RDMEM(M6502_RST_VEC+1);
m6502.sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
m6502.p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502.pending_irq = 0; /* nonzero if an IRQ is pending */
m6502.after_cli = 0; /* pending IRQ and last insn cleared I */
m6502.irq_state = 0;
m6502.nmi_state = 0;
m6502->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
m6502->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502->pending_irq = 0; /* nonzero if an IRQ is pending */
m6502->after_cli = 0; /* pending IRQ and last insn cleared I */
m6502->irq_state = 0;
m6502->nmi_state = 0;
change_pc(PCD);
}
@ -188,25 +196,26 @@ static CPU_EXIT( m6502 )
static void m6502_get_context (void *dst)
{
if( dst )
*(m6502_Regs*)dst = m6502;
}
static void m6502_set_context (void *src)
{
m6502_Regs *m6502;
if( src )
{
m6502 = *(m6502_Regs*)src;
token = src;
m6502 = token;
change_pc(PCD);
}
}
INLINE void m6502_take_irq(void)
INLINE void m6502_take_irq(m6502_Regs *m6502)
{
if( !(P & F_I) )
{
EAD = M6502_IRQ_VEC;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -215,15 +224,17 @@ INLINE void m6502_take_irq(void)
PCH = RDMEM(EAD+1);
LOG(("M6502#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502.irq_callback) (*m6502.irq_callback)(m6502.device, 0);
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502.pending_irq = 0;
m6502->pending_irq = 0;
}
static CPU_EXECUTE( m6502 )
{
m6502_ICount = cycles;
m6502_Regs *m6502 = device->token;
m6502->icount = cycles;
change_pc(PCD);
@ -235,21 +246,21 @@ static CPU_EXECUTE( m6502 )
debugger_instruction_hook(Machine, PCD);
/* if an irq is pending, take it now */
if( m6502.pending_irq )
m6502_take_irq();
if( m6502->pending_irq )
m6502_take_irq(m6502);
op = RDOP();
(*m6502.insn[op])();
(*m6502->insn[op])(m6502);
/* check if the I flag was just reset (interrupts enabled) */
if( m6502.after_cli )
if( m6502->after_cli )
{
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
m6502.after_cli = 0;
if (m6502.irq_state != CLEAR_LINE)
m6502->after_cli = 0;
if (m6502->irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m6502.pending_irq = 1;
m6502->pending_irq = 1;
}
else
{
@ -257,34 +268,34 @@ static CPU_EXECUTE( m6502 )
}
}
else {
if ( m6502.pending_irq == 2 ) {
if ( m6502_IntOccured - m6502_ICount > 1 ) {
m6502.pending_irq = 1;
if ( m6502->pending_irq == 2 ) {
if ( m6502->int_occured - m6502->icount > 1 ) {
m6502->pending_irq = 1;
}
}
if( m6502.pending_irq == 1 )
m6502_take_irq();
if ( m6502.pending_irq == 2 ) {
m6502.pending_irq = 1;
if( m6502->pending_irq == 1 )
m6502_take_irq(m6502);
if ( m6502->pending_irq == 2 ) {
m6502->pending_irq = 1;
}
}
} while (m6502_ICount > 0);
} while (m6502->icount > 0);
return cycles - m6502_ICount;
return cycles - m6502->icount;
}
static void m6502_set_irq_line(int irqline, int state)
static void m6502_set_irq_line(m6502_Regs *m6502, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m6502.nmi_state == state) return;
m6502.nmi_state = state;
if (m6502->nmi_state == state) return;
m6502->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M6502_NMI_VEC;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -299,21 +310,21 @@ static void m6502_set_irq_line(int irqline, int state)
{
if( irqline == M6502_SET_OVERFLOW )
{
if( m6502.so_state && !state )
if( m6502->so_state && !state )
{
LOG(( "M6502#%d set overflow\n", cpu_getactivecpu()));
P|=F_V;
}
m6502.so_state=state;
m6502->so_state=state;
return;
}
m6502.irq_state = state;
m6502->irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m6502.pending_irq = 1;
// m6502.pending_irq = 2;
m6502_IntOccured = m6502_ICount;
m6502->pending_irq = 1;
// m6502->pending_irq = 2;
m6502->int_occured = m6502->icount;
}
}
}
@ -334,9 +345,11 @@ static CPU_INIT( n2a03 )
Bit 7 of address $4011 (the PSG's DPCM control register), when set,
causes an IRQ to be generated. This function allows the IRQ to be called
from the PSG core when such an occasion arises. */
void n2a03_irq(void)
void n2a03_irq()
{
m6502_take_irq();
m6502_Regs *m6502 = token;
m6502_take_irq(m6502);
}
#endif
@ -353,29 +366,32 @@ static CPU_INIT( m6510 )
static CPU_RESET( m6510 )
{
m6502_Regs *m6502 = device->token;
CPU_RESET_CALL(m6502);
m6502.port = 0xff;
m6502.ddr = 0x00;
m6502->port = 0xff;
m6502->ddr = 0x00;
}
static UINT8 m6510_get_port(void)
static UINT8 m6510_get_port(m6502_Regs *m6502)
{
return (m6502.port & m6502.ddr) | (m6502.ddr ^ 0xff);
return (m6502->port & m6502->ddr) | (m6502->ddr ^ 0xff);
}
static READ8_HANDLER( m6510_read_0000 )
{
m6502_Regs *m6502 = token;
UINT8 result = 0x00;
switch(offset)
{
case 0x0000: /* DDR */
result = m6502.ddr;
result = m6502->ddr;
break;
case 0x0001: /* Data Port */
if (m6502.port_read)
result = m6502.port_read( m6502.ddr );
result = (m6502.ddr & m6502.port) | (~m6502.ddr & result);
if (m6502->port_read)
result = m6502->port_read( m6502->ddr );
result = (m6502->ddr & m6502->port) | (~m6502->ddr & result);
break;
}
return result;
@ -383,18 +399,20 @@ static READ8_HANDLER( m6510_read_0000 )
static WRITE8_HANDLER( m6510_write_0000 )
{
m6502_Regs *m6502 = token;
switch(offset)
{
case 0x0000: /* DDR */
m6502.ddr = data;
m6502->ddr = data;
break;
case 0x0001: /* Data Port */
m6502.port = data;
m6502->port = data;
break;
}
if (m6502.port_write)
m6502.port_write( m6502.ddr, m6502.port & m6502.ddr );
if (m6502->port_write)
m6502->port_write( m6502->ddr, m6502->port & m6502->ddr );
}
static ADDRESS_MAP_START(m6510_mem, ADDRESS_SPACE_PROGRAM, 8)
@ -416,16 +434,18 @@ static CPU_INIT( m65c02 )
static CPU_RESET( m65c02 )
{
m6502_Regs *m6502 = device->token;
CPU_RESET_CALL(m6502);
P &=~F_D;
}
INLINE void m65c02_take_irq(void)
INLINE void m65c02_take_irq(m6502_Regs *m6502)
{
if( !(P & F_I) )
{
EAD = M6502_IRQ_VEC;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -434,15 +454,17 @@ INLINE void m65c02_take_irq(void)
PCH = RDMEM(EAD+1);
LOG(("M65c02#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502.irq_callback) (*m6502.irq_callback)(m6502.device, 0);
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502.pending_irq = 0;
m6502->pending_irq = 0;
}
static CPU_EXECUTE( m65c02 )
{
m6502_ICount = cycles;
m6502_Regs *m6502 = device->token;
m6502->icount = cycles;
change_pc(PCD);
@ -454,22 +476,22 @@ static CPU_EXECUTE( m65c02 )
debugger_instruction_hook(Machine, PCD);
op = RDOP();
(*m6502.insn[op])();
(*m6502->insn[op])(m6502);
/* if an irq is pending, take it now */
if( m6502.pending_irq )
m65c02_take_irq();
if( m6502->pending_irq )
m65c02_take_irq(m6502);
/* check if the I flag was just reset (interrupts enabled) */
if( m6502.after_cli )
if( m6502->after_cli )
{
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
m6502.after_cli = 0;
if (m6502.irq_state != CLEAR_LINE)
m6502->after_cli = 0;
if (m6502->irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m6502.pending_irq = 1;
m6502->pending_irq = 1;
}
else
{
@ -477,25 +499,25 @@ static CPU_EXECUTE( m65c02 )
}
}
else
if( m6502.pending_irq )
m65c02_take_irq();
if( m6502->pending_irq )
m65c02_take_irq(m6502);
} while (m6502_ICount > 0);
} while (m6502->icount > 0);
return cycles - m6502_ICount;
return cycles - m6502->icount;
}
static void m65c02_set_irq_line(int irqline, int state)
static void m65c02_set_irq_line(m6502_Regs *m6502, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m6502.nmi_state == state) return;
m6502.nmi_state = state;
if (m6502->nmi_state == state) return;
m6502->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M6502_NMI_VEC;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -507,7 +529,7 @@ static void m65c02_set_irq_line(int irqline, int state)
}
}
else
m6502_set_irq_line(irqline,state);
m6502_set_irq_line(m6502, irqline,state);
}
#endif
@ -534,27 +556,29 @@ static CPU_INIT( deco16 )
static CPU_RESET( deco16 )
{
m6502_Regs *m6502 = device->token;
CPU_RESET_CALL(m6502);
m6502.subtype = SUBTYPE_DECO16;
m6502.insn = insndeco16;
m6502->subtype = SUBTYPE_DECO16;
m6502->insn = insndeco16;
PCL = RDMEM(DECO16_RST_VEC+1);
PCH = RDMEM(DECO16_RST_VEC);
m6502.sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
m6502.p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502.pending_irq = 0; /* nonzero if an IRQ is pending */
m6502.after_cli = 0; /* pending IRQ and last insn cleared I */
m6502->sp.d = 0x01ff; /* stack pointer starts at page 1 offset FF */
m6502->p = F_T|F_I|F_Z|F_B|(P&F_D); /* set T, I and Z flags */
m6502->pending_irq = 0; /* nonzero if an IRQ is pending */
m6502->after_cli = 0; /* pending IRQ and last insn cleared I */
change_pc(PCD);
}
INLINE void deco16_take_irq(void)
INLINE void deco16_take_irq(m6502_Regs *m6502)
{
if( !(P & F_I) )
{
EAD = DECO16_IRQ_VEC;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -563,23 +587,23 @@ INLINE void deco16_take_irq(void)
PCH = RDMEM(EAD);
LOG(("M6502#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6502.irq_callback) (*m6502.irq_callback)(m6502.device, 0);
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6502.pending_irq = 0;
m6502->pending_irq = 0;
}
static void deco16_set_irq_line(int irqline, int state)
static void deco16_set_irq_line(m6502_Regs *m6502, int irqline, int state)
{
if (irqline == INPUT_LINE_NMI)
{
if (m6502.nmi_state == state) return;
m6502.nmi_state = state;
if (m6502->nmi_state == state) return;
m6502->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = DECO16_NMI_VEC;
m6502_ICount -= 7;
m6502->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -594,26 +618,28 @@ static void deco16_set_irq_line(int irqline, int state)
{
if( irqline == M6502_SET_OVERFLOW )
{
if( m6502.so_state && !state )
if( m6502->so_state && !state )
{
LOG(( "M6502#%d set overflow\n", cpu_getactivecpu()));
P|=F_V;
}
m6502.so_state=state;
m6502->so_state=state;
return;
}
m6502.irq_state = state;
m6502->irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6502#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m6502.pending_irq = 1;
m6502->pending_irq = 1;
}
}
}
static CPU_EXECUTE( deco16 )
{
m6502_ICount = cycles;
m6502_Regs *m6502 = device->token;
m6502->icount = cycles;
change_pc(PCD);
@ -625,22 +651,22 @@ static CPU_EXECUTE( deco16 )
debugger_instruction_hook(Machine, PCD);
op = RDOP();
(*m6502.insn[op])();
(*m6502->insn[op])(m6502);
/* if an irq is pending, take it now */
if( m6502.pending_irq )
deco16_take_irq();
if( m6502->pending_irq )
deco16_take_irq(m6502);
/* check if the I flag was just reset (interrupts enabled) */
if( m6502.after_cli )
if( m6502->after_cli )
{
LOG(("M6502#%d after_cli was >0", cpu_getactivecpu()));
m6502.after_cli = 0;
if (m6502.irq_state != CLEAR_LINE)
m6502->after_cli = 0;
if (m6502->irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m6502.pending_irq = 1;
m6502->pending_irq = 1;
}
else
{
@ -648,12 +674,12 @@ static CPU_EXECUTE( deco16 )
}
}
else
if( m6502.pending_irq )
deco16_take_irq();
if( m6502->pending_irq )
deco16_take_irq(m6502);
} while (m6502_ICount > 0);
} while (m6502->icount > 0);
return cycles - m6502_ICount;
return cycles - m6502->icount;
}
#endif
@ -666,27 +692,29 @@ static CPU_EXECUTE( deco16 )
static void m6502_set_info(UINT32 state, cpuinfo *info)
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: m6502_set_irq_line(M6502_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: m6502_set_irq_line(M6502_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6502_set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: m6502_set_irq_line(m6502, M6502_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: m6502_set_irq_line(m6502, M6502_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6502_set_irq_line(m6502, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_REGISTER + M6502_PC: m6502.pc.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6502_PC: m6502->pc.w.l = info->i; break;
case CPUINFO_INT_SP: S = info->i; break;
case CPUINFO_INT_REGISTER + M6502_S: m6502.sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M6502_P: m6502.p = info->i; break;
case CPUINFO_INT_REGISTER + M6502_A: m6502.a = info->i; break;
case CPUINFO_INT_REGISTER + M6502_X: m6502.x = info->i; break;
case CPUINFO_INT_REGISTER + M6502_Y: m6502.y = info->i; break;
case CPUINFO_INT_REGISTER + M6502_EA: m6502.ea.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6502_ZP: m6502.zp.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6502_S: m6502->sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M6502_P: m6502->p = info->i; break;
case CPUINFO_INT_REGISTER + M6502_A: m6502->a = info->i; break;
case CPUINFO_INT_REGISTER + M6502_X: m6502->x = info->i; break;
case CPUINFO_INT_REGISTER + M6502_Y: m6502->y = info->i; break;
case CPUINFO_INT_REGISTER + M6502_EA: m6502->ea.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6502_ZP: m6502->zp.w.l = info->i; break;
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: m6502.rdmem_id = (read8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: m6502.wrmem_id = (write8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: m6502->rdmem_id = (read8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: m6502->wrmem_id = (write8_machine_func) info->f; break;
}
}
@ -698,10 +726,12 @@ static void m6502_set_info(UINT32 state, cpuinfo *info)
void m6502_get_info(UINT32 state, cpuinfo *info)
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6502); break;
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(m6502_Regs); break;
case CPUINFO_INT_INPUT_LINES: info->i = 2; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = CPU_IS_LE; break;
@ -722,23 +752,23 @@ void m6502_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: info->i = m6502.irq_state; break;
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: info->i = m6502.so_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = m6502.nmi_state; break;
case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: info->i = m6502->irq_state; break;
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: info->i = m6502->so_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = m6502->nmi_state; break;
case CPUINFO_INT_PREVIOUSPC: info->i = m6502.ppc.w.l; break;
case CPUINFO_INT_PREVIOUSPC: info->i = m6502->ppc.w.l; break;
case CPUINFO_INT_PC: info->i = PCD; break;
case CPUINFO_INT_REGISTER + M6502_PC: info->i = m6502.pc.w.l; break;
case CPUINFO_INT_REGISTER + M6502_PC: info->i = m6502->pc.w.l; break;
case CPUINFO_INT_SP: info->i = S; break;
case CPUINFO_INT_REGISTER + M6502_S: info->i = m6502.sp.b.l; break;
case CPUINFO_INT_REGISTER + M6502_P: info->i = m6502.p; break;
case CPUINFO_INT_REGISTER + M6502_A: info->i = m6502.a; break;
case CPUINFO_INT_REGISTER + M6502_X: info->i = m6502.x; break;
case CPUINFO_INT_REGISTER + M6502_Y: info->i = m6502.y; break;
case CPUINFO_INT_REGISTER + M6502_EA: info->i = m6502.ea.w.l; break;
case CPUINFO_INT_REGISTER + M6502_ZP: info->i = m6502.zp.w.l; break;
case CPUINFO_INT_REGISTER + M6502_SUBTYPE: info->i = m6502.subtype; break;
case CPUINFO_INT_REGISTER + M6502_S: info->i = m6502->sp.b.l; break;
case CPUINFO_INT_REGISTER + M6502_P: info->i = m6502->p; break;
case CPUINFO_INT_REGISTER + M6502_A: info->i = m6502->a; break;
case CPUINFO_INT_REGISTER + M6502_X: info->i = m6502->x; break;
case CPUINFO_INT_REGISTER + M6502_Y: info->i = m6502->y; break;
case CPUINFO_INT_REGISTER + M6502_EA: info->i = m6502->ea.w.l; break;
case CPUINFO_INT_REGISTER + M6502_ZP: info->i = m6502->zp.w.l; break;
case CPUINFO_INT_REGISTER + M6502_SUBTYPE: info->i = m6502->subtype; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = m6502_set_info; break;
@ -750,9 +780,9 @@ void m6502_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(m6502); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = m6502_dasm; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m6502_ICount; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m6502.rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m6502.wrmem_id; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m6502->icount; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m6502->rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m6502->wrmem_id; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "M6502"); break;
@ -763,24 +793,24 @@ void m6502_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c",
m6502.p & 0x80 ? 'N':'.',
m6502.p & 0x40 ? 'V':'.',
m6502.p & 0x20 ? 'R':'.',
m6502.p & 0x10 ? 'B':'.',
m6502.p & 0x08 ? 'D':'.',
m6502.p & 0x04 ? 'I':'.',
m6502.p & 0x02 ? 'Z':'.',
m6502.p & 0x01 ? 'C':'.');
m6502->p & 0x80 ? 'N':'.',
m6502->p & 0x40 ? 'V':'.',
m6502->p & 0x20 ? 'R':'.',
m6502->p & 0x10 ? 'B':'.',
m6502->p & 0x08 ? 'D':'.',
m6502->p & 0x04 ? 'I':'.',
m6502->p & 0x02 ? 'Z':'.',
m6502->p & 0x01 ? 'C':'.');
break;
case CPUINFO_STR_REGISTER + M6502_PC: sprintf(info->s, "PC:%04X", m6502.pc.w.l); break;
case CPUINFO_STR_REGISTER + M6502_S: sprintf(info->s, "S:%02X", m6502.sp.b.l); break;
case CPUINFO_STR_REGISTER + M6502_P: sprintf(info->s, "P:%02X", m6502.p); break;
case CPUINFO_STR_REGISTER + M6502_A: sprintf(info->s, "A:%02X", m6502.a); break;
case CPUINFO_STR_REGISTER + M6502_X: sprintf(info->s, "X:%02X", m6502.x); break;
case CPUINFO_STR_REGISTER + M6502_Y: sprintf(info->s, "Y:%02X", m6502.y); break;
case CPUINFO_STR_REGISTER + M6502_EA: sprintf(info->s, "EA:%04X", m6502.ea.w.l); break;
case CPUINFO_STR_REGISTER + M6502_ZP: sprintf(info->s, "ZP:%03X", m6502.zp.w.l); break;
case CPUINFO_STR_REGISTER + M6502_PC: sprintf(info->s, "PC:%04X", m6502->pc.w.l); break;
case CPUINFO_STR_REGISTER + M6502_S: sprintf(info->s, "S:%02X", m6502->sp.b.l); break;
case CPUINFO_STR_REGISTER + M6502_P: sprintf(info->s, "P:%02X", m6502->p); break;
case CPUINFO_STR_REGISTER + M6502_A: sprintf(info->s, "A:%02X", m6502->a); break;
case CPUINFO_STR_REGISTER + M6502_X: sprintf(info->s, "X:%02X", m6502->x); break;
case CPUINFO_STR_REGISTER + M6502_Y: sprintf(info->s, "Y:%02X", m6502->y); break;
case CPUINFO_STR_REGISTER + M6502_EA: sprintf(info->s, "EA:%04X", m6502->ea.w.l); break;
case CPUINFO_STR_REGISTER + M6502_ZP: sprintf(info->s, "ZP:%03X", m6502->zp.w.l); break;
}
}
@ -813,11 +843,13 @@ void n2a03_get_info(UINT32 state, cpuinfo *info)
static void m6510_set_info(UINT32 state, cpuinfo *info)
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_M6510_PORTREAD: m6502.port_read = (UINT8 (*)(UINT8)) info->f; break;
case CPUINFO_PTR_M6510_PORTWRITE: m6502.port_write = (void (*)(UINT8,UINT8)) info->f; break;
case CPUINFO_PTR_M6510_PORTREAD: m6502->port_read = (UINT8 (*)(UINT8)) info->f; break;
case CPUINFO_PTR_M6510_PORTWRITE: m6502->port_write = (void (*)(UINT8,UINT8)) info->f; break;
default: m6502_set_info(state, info); break;
}
@ -825,6 +857,8 @@ static void m6510_set_info(UINT32 state, cpuinfo *info)
void m6510_get_info(UINT32 state, cpuinfo *info)
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are returned as pointers to data or functions --- */
@ -833,14 +867,14 @@ void m6510_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(m6510); break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = m6510_dasm; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP: info->internal_map8 = address_map_m6510_mem; break;
case CPUINFO_PTR_M6510_PORTREAD: info->f = (genf *) m6502.port_read; break;
case CPUINFO_PTR_M6510_PORTWRITE: info->f = (genf *) m6502.port_write; break;
case CPUINFO_PTR_M6510_PORTREAD: info->f = (genf *) m6502->port_read; break;
case CPUINFO_PTR_M6510_PORTWRITE: info->f = (genf *) m6502->port_write; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "M6510"); break;
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_M6510_PORT: info->i = m6510_get_port(); break;
case CPUINFO_INT_M6510_PORT: info->i = m6510_get_port(m6502); break;
default: m6502_get_info(state, info); break;
}
@ -909,10 +943,12 @@ void m8502_get_info(UINT32 state, cpuinfo *info)
static void m65c02_set_info(UINT32 state, cpuinfo *info)
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m65c02_set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m65c02_set_irq_line(m6502, INPUT_LINE_NMI, info->i); break;
default: m6502_set_info(state, info); break;
}
@ -971,12 +1007,14 @@ void m65sc02_get_info(UINT32 state, cpuinfo *info)
static void deco16_set_info(UINT32 state, cpuinfo *info)
{
m6502_Regs *m6502 = token;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: deco16_set_irq_line(M6502_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: deco16_set_irq_line(M6502_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: deco16_set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6502_IRQ_LINE: deco16_set_irq_line(m6502, M6502_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6502_SET_OVERFLOW: deco16_set_irq_line(m6502, M6502_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: deco16_set_irq_line(m6502, INPUT_LINE_NMI, info->i); break;
default: m6502_set_info(state, info); break;
}

235
src/emu/cpu/m6502/m6509.c
View File

@ -56,10 +56,10 @@ addresses take place.
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
typedef struct {
typedef struct _m6509_Regs m6509_Regs;
struct _m6509_Regs {
UINT8 subtype; /* currently selected cpu sub type */
void (*const *insn)(void); /* pointer to the function pointer table */
void (*const *insn)(m6509_Regs *); /* pointer to the function pointer table */
PAIR ppc; /* previous program counter */
/* pc.w.h contains the current page pc_bank.w.h for better speed */
PAIR pc; /* program counter */
@ -79,13 +79,14 @@ typedef struct {
UINT8 so_state;
cpu_irq_callback irq_callback;
const device_config *device;
int icount;
read8_machine_func rdmem_id; /* readmem callback for indexed instructions */
write8_machine_func wrmem_id; /* readmem callback for indexed instructions */
} m6509_Regs;
};
static int m6502_ICount = 0;
static m6509_Regs m6509;
static void *token;
/***************************************************************
* include the opcode macros, functions and tables
@ -95,24 +96,34 @@ static m6509_Regs m6509;
static READ8_HANDLER( m6509_read_00000 )
{
return m6509.pc_bank.b.h2;
m6509_Regs *m6509 = token;
return m6509->pc_bank.b.h2;
}
static READ8_HANDLER( m6509_read_00001 )
{
return m6509.ind_bank.b.h2;
m6509_Regs *m6509 = token;
return m6509->ind_bank.b.h2;
}
static WRITE8_HANDLER( m6509_write_00000 )
{
m6509.pc_bank.b.h2=data&0xf;
m6509.pc.w.h=m6509.pc_bank.w.h;
m6509_Regs *m6509 = token;
m6509_Regs *m6502 = m6509;
m6509->pc_bank.b.h2=data&0xf;
m6509->pc.w.h=m6509->pc_bank.w.h;
change_pc(PCD);
}
static WRITE8_HANDLER( m6509_write_00001 )
{
m6509.ind_bank.b.h2=data&0xf;
m6509_Regs *m6509 = token;
m6509->ind_bank.b.h2=data&0xf;
}
static ADDRESS_MAP_START(m6509_mem, ADDRESS_SPACE_PROGRAM, 8)
@ -125,29 +136,36 @@ static WRITE8_HANDLER( default_wdmem_id ) { program_write_byte_8le(offset, data)
static CPU_INIT( m6509 )
{
m6509.rdmem_id = default_rdmem_id;
m6509.wrmem_id = default_wdmem_id;
m6509.irq_callback = irqcallback;
m6509.device = device;
m6509_Regs *m6509 = device->token;
token = device->token; // temporary
m6509->rdmem_id = default_rdmem_id;
m6509->wrmem_id = default_wdmem_id;
m6509->irq_callback = irqcallback;
m6509->device = device;
}
static CPU_RESET( m6509 )
{
m6509.insn = insn6509;
m6509_Regs *m6509 = device->token;
m6509_Regs *m6502 = m6509;
m6509.pc_bank.d=m6509.ind_bank.d=0;
m6509.pc_bank.b.h2=m6509.ind_bank.b.h2=0xf; /* cbm500 needs this */
m6509.pc.w.h=m6509.pc_bank.w.h;
m6509->insn = insn6509;
m6509->pc_bank.d=m6509->ind_bank.d=0;
m6509->pc_bank.b.h2=m6509->ind_bank.b.h2=0xf; /* cbm500 needs this */
m6509->pc.w.h=m6509->pc_bank.w.h;
/* wipe out the rest of the m6509 structure */
/* read the reset vector into PC */
PCL = RDMEM(M6509_RST_VEC|PB);
PCH = RDMEM((M6509_RST_VEC+1)|PB);
m6509.sp.d = 0x01ff;
m6509.p = F_T|F_B|F_I|F_Z|(P&F_D); /* set T, I and Z flags */
m6509.pending_irq = 0; /* nonzero if an IRQ is pending */
m6509.after_cli = 0; /* pending IRQ and last insn cleared I */
m6509.irq_callback = NULL;
m6509->sp.d = 0x01ff;
m6509->p = F_T|F_B|F_I|F_Z|(P&F_D); /* set T, I and Z flags */
m6509->pending_irq = 0; /* nonzero if an IRQ is pending */
m6509->after_cli = 0; /* pending IRQ and last insn cleared I */
m6509->irq_callback = NULL;
change_pc(PCD);
}
@ -159,28 +177,30 @@ static CPU_EXIT( m6509 )
static void m6509_get_context (void *dst)
{
if( dst )
*(m6509_Regs*)dst = m6509;
}
static void m6509_set_context (void *src)
{
m6509_Regs *m6502;
if( src )
{
m6509 = *(m6509_Regs*)src;
token = src;
m6502 = token;
change_pc(PCD);
}
}
INLINE void m6509_take_irq(void)
INLINE void m6509_take_irq( m6509_Regs *m6502)
{
if( !(P & F_I) )
{
EAD = M6509_IRQ_VEC;
EAWH = PBWH;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -189,15 +209,18 @@ INLINE void m6509_take_irq(void)
PCH = RDMEM(EAD+1);
LOG(("M6509#%d takes IRQ ($%04x)\n", cpu_getactivecpu(), PCD));
/* call back the cpuintrf to let it clear the line */
if (m6509.irq_callback) (*m6509.irq_callback)(m6509.device, 0);
if (m6502->irq_callback) (*m6502->irq_callback)(m6502->device, 0);
change_pc(PCD);
}
m6509.pending_irq = 0;
m6502->pending_irq = 0;
}
static CPU_EXECUTE( m6509 )
{
m6502_ICount = cycles;
m6509_Regs *m6502 = device->token;
m6509_Regs *m6509 = m6502;
m6502->icount = cycles;
change_pc(PCD);
@ -209,21 +232,21 @@ static CPU_EXECUTE( m6509 )
debugger_instruction_hook(Machine, PCD);
/* if an irq is pending, take it now */
if( m6509.pending_irq )
m6509_take_irq();
if( m6509->pending_irq )
m6509_take_irq(m6509);
op = RDOP();
(*m6509.insn[op])();
(*m6509->insn[op])(m6509);
/* check if the I flag was just reset (interrupts enabled) */
if( m6509.after_cli )
if( m6509->after_cli )
{
LOG(("M6509#%d after_cli was >0", cpu_getactivecpu()));
m6509.after_cli = 0;
if (m6509.irq_state != CLEAR_LINE)
m6509->after_cli = 0;
if (m6509->irq_state != CLEAR_LINE)
{
LOG((": irq line is asserted: set pending IRQ\n"));
m6509.pending_irq = 1;
m6509->pending_irq = 1;
}
else
{
@ -231,26 +254,28 @@ static CPU_EXECUTE( m6509 )
}
}
else
if( m6509.pending_irq )
m6509_take_irq();
if( m6509->pending_irq )
m6509_take_irq(m6502);
} while (m6502_ICount > 0);
} while (m6502->icount > 0);
return cycles - m6502_ICount;
return cycles - m6502->icount;
}
static void m6509_set_irq_line(int irqline, int state)
static void m6509_set_irq_line(m6509_Regs *m6509, int irqline, int state)
{
m6509_Regs *m6502 = m6509;
if (irqline == INPUT_LINE_NMI)
{
if (m6509.nmi_state == state) return;
m6509.nmi_state = state;
if (m6509->nmi_state == state) return;
m6509->nmi_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6509#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M6509_NMI_VEC;
EAWH = PBWH;
m6502_ICount -= 2;
m6502->icount -= 2;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -265,19 +290,19 @@ static void m6509_set_irq_line(int irqline, int state)
{
if( irqline == M6509_SET_OVERFLOW )
{
if( m6509.so_state && !state )
if( m6509->so_state && !state )
{
LOG(( "M6509#%d set overflow\n", cpu_getactivecpu()));
P|=F_V;
}
m6509.so_state=state;
m6509->so_state=state;
return;
}
m6509.irq_state = state;
m6509->irq_state = state;
if( state != CLEAR_LINE )
{
LOG(( "M6509#%d set_irq_line(ASSERT)\n", cpu_getactivecpu()));
m6509.pending_irq = 1;
m6509->pending_irq = 1;
}
}
}
@ -288,29 +313,32 @@ static void m6509_set_irq_line(int irqline, int state)
static void m6509_set_info(UINT32 state, cpuinfo *info)
{
m6509_Regs *m6509 = token;
m6509_Regs *m6502 = m6509;
switch (state)
{
/* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_INPUT_STATE + M6509_IRQ_LINE: m6509_set_irq_line(M6509_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:m6509_set_irq_line(M6509_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6509_set_irq_line(INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6509_IRQ_LINE: m6509_set_irq_line(m6509, M6509_IRQ_LINE, info->i); break;
case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:m6509_set_irq_line(m6509, M6509_SET_OVERFLOW, info->i); break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: m6509_set_irq_line(m6509, INPUT_LINE_NMI, info->i); break;
case CPUINFO_INT_PC: PCW = info->i; change_pc(PCD); break;
case CPUINFO_INT_REGISTER + M6509_PC: m6509.pc.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6509_PC: m6509->pc.w.l = info->i; break;
case CPUINFO_INT_SP: S = info->i; break;
case CPUINFO_INT_REGISTER + M6509_S: m6509.sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M6509_P: m6509.p = info->i; break;
case CPUINFO_INT_REGISTER + M6509_A: m6509.a = info->i; break;
case CPUINFO_INT_REGISTER + M6509_X: m6509.x = info->i; break;
case CPUINFO_INT_REGISTER + M6509_Y: m6509.y = info->i; break;
case CPUINFO_INT_REGISTER + M6509_PC_BANK: m6509.pc_bank.b.h2 = info->i; break;
case CPUINFO_INT_REGISTER + M6509_IND_BANK: m6509.ind_bank.b.h2 = info->i; break;
case CPUINFO_INT_REGISTER + M6509_EA: m6509.ea.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6509_ZP: m6509.zp.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6509_S: m6509->sp.b.l = info->i; break;
case CPUINFO_INT_REGISTER + M6509_P: m6509->p = info->i; break;
case CPUINFO_INT_REGISTER + M6509_A: m6509->a = info->i; break;
case CPUINFO_INT_REGISTER + M6509_X: m6509->x = info->i; break;
case CPUINFO_INT_REGISTER + M6509_Y: m6509->y = info->i; break;
case CPUINFO_INT_REGISTER + M6509_PC_BANK: m6509->pc_bank.b.h2 = info->i; break;
case CPUINFO_INT_REGISTER + M6509_IND_BANK: m6509->ind_bank.b.h2 = info->i; break;
case CPUINFO_INT_REGISTER + M6509_EA: m6509->ea.w.l = info->i; break;
case CPUINFO_INT_REGISTER + M6509_ZP: m6509->zp.w.l = info->i; break;
/* --- the following bits of info are set as pointers to data or functions --- */
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: m6509.rdmem_id = (read8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: m6509.wrmem_id = (write8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: m6509->rdmem_id = (read8_machine_func) info->f; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: m6509->wrmem_id = (write8_machine_func) info->f; break;
}
}
@ -322,6 +350,9 @@ static void m6509_set_info(UINT32 state, cpuinfo *info)
void m6509_get_info(UINT32 state, cpuinfo *info)
{
m6509_Regs *m6502 = token;
m6509_Regs *m6509 = m6502;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
@ -346,24 +377,24 @@ void m6509_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_INT_ADDRBUS_WIDTH + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + ADDRESS_SPACE_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE + M6509_IRQ_LINE: info->i = m6509.irq_state; break;
case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:info->i = m6509.so_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = m6509.nmi_state; break;
case CPUINFO_INT_INPUT_STATE + M6509_IRQ_LINE: info->i = m6509->irq_state; break;
case CPUINFO_INT_INPUT_STATE + M6509_SET_OVERFLOW:info->i = m6509->so_state; break;
case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = m6509->nmi_state; break;
case CPUINFO_INT_PREVIOUSPC: info->i = m6509.ppc.w.l; break;
case CPUINFO_INT_PREVIOUSPC: info->i = m6509->ppc.w.l; break;
case CPUINFO_INT_PC: info->i = PCD; break;
case CPUINFO_INT_REGISTER + M6509_PC: info->i = m6509.pc.w.l; break;
case CPUINFO_INT_REGISTER + M6509_PC: info->i = m6509->pc.w.l; break;
case CPUINFO_INT_SP: info->i = S; break;
case CPUINFO_INT_REGISTER + M6509_S: info->i = m6509.sp.b.l; break;
case CPUINFO_INT_REGISTER + M6509_P: info->i = m6509.p; break;
case CPUINFO_INT_REGISTER + M6509_A: info->i = m6509.a; break;
case CPUINFO_INT_REGISTER + M6509_X: info->i = m6509.x; break;
case CPUINFO_INT_REGISTER + M6509_Y: info->i = m6509.y; break;
case CPUINFO_INT_REGISTER + M6509_PC_BANK: info->i = m6509.pc_bank.b.h2; break;
case CPUINFO_INT_REGISTER + M6509_IND_BANK: info->i = m6509.ind_bank.b.h2; break;
case CPUINFO_INT_REGISTER + M6509_EA: info->i = m6509.ea.w.l; break;
case CPUINFO_INT_REGISTER + M6509_ZP: info->i = m6509.zp.w.l; break;
case CPUINFO_INT_REGISTER + M6509_S: info->i = m6509->sp.b.l; break;
case CPUINFO_INT_REGISTER + M6509_P: info->i = m6509->p; break;
case CPUINFO_INT_REGISTER + M6509_A: info->i = m6509->a; break;
case CPUINFO_INT_REGISTER + M6509_X: info->i = m6509->x; break;
case CPUINFO_INT_REGISTER + M6509_Y: info->i = m6509->y; break;
case CPUINFO_INT_REGISTER + M6509_PC_BANK: info->i = m6509->pc_bank.b.h2; break;
case CPUINFO_INT_REGISTER + M6509_IND_BANK: info->i = m6509->ind_bank.b.h2; break;
case CPUINFO_INT_REGISTER + M6509_EA: info->i = m6509->ea.w.l; break;
case CPUINFO_INT_REGISTER + M6509_ZP: info->i = m6509->zp.w.l; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = m6509_set_info; break;
@ -375,10 +406,10 @@ void m6509_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(m6509); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = m6502_dasm; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m6502_ICount; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m6502->icount; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP: info->internal_map8 = address_map_m6509_mem; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m6509.rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m6509.wrmem_id; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m6509->rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m6509->wrmem_id; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "M6509"); break;
@ -389,26 +420,26 @@ void m6509_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c",
m6509.p & 0x80 ? 'N':'.',
m6509.p & 0x40 ? 'V':'.',
m6509.p & 0x20 ? 'R':'.',
m6509.p & 0x10 ? 'B':'.',
m6509.p & 0x08 ? 'D':'.',
m6509.p & 0x04 ? 'I':'.',
m6509.p & 0x02 ? 'Z':'.',
m6509.p & 0x01 ? 'C':'.');
m6509->p & 0x80 ? 'N':'.',
m6509->p & 0x40 ? 'V':'.',
m6509->p & 0x20 ? 'R':'.',
m6509->p & 0x10 ? 'B':'.',
m6509->p & 0x08 ? 'D':'.',
m6509->p & 0x04 ? 'I':'.',
m6509->p & 0x02 ? 'Z':'.',
m6509->p & 0x01 ? 'C':'.');
break;
case CPUINFO_STR_REGISTER + M6509_PC: sprintf(info->s, "PC:%04X", m6509.pc.w.l); break;
case CPUINFO_STR_REGISTER + M6509_S: sprintf(info->s, "S:%02X", m6509.sp.b.l); break;
case CPUINFO_STR_REGISTER + M6509_P: sprintf(info->s, "P:%02X", m6509.p); break;
case CPUINFO_STR_REGISTER + M6509_A: sprintf(info->s, "A:%02X", m6509.a); break;
case CPUINFO_STR_REGISTER + M6509_X: sprintf(info->s, "X:%02X", m6509.x); break;
case CPUINFO_STR_REGISTER + M6509_Y: sprintf(info->s, "Y:%02X", m6509.y); break;
case CPUINFO_STR_REGISTER + M6509_PC_BANK: sprintf(info->s, "M0:%01X", m6509.pc_bank.b.h2); break;
case CPUINFO_STR_REGISTER + M6509_IND_BANK: sprintf(info->s, "M1:%01X", m6509.ind_bank.b.h2); break;
case CPUINFO_STR_REGISTER + M6509_EA: sprintf(info->s, "EA:%04X", m6509.ea.w.l); break;
case CPUINFO_STR_REGISTER + M6509_ZP: sprintf(info->s, "ZP:%03X", m6509.zp.w.l); break;
case CPUINFO_STR_REGISTER + M6509_PC: sprintf(info->s, "PC:%04X", m6509->pc.w.l); break;
case CPUINFO_STR_REGISTER + M6509_S: sprintf(info->s, "S:%02X", m6509->sp.b.l); break;
case CPUINFO_STR_REGISTER + M6509_P: sprintf(info->s, "P:%02X", m6509->p); break;
case CPUINFO_STR_REGISTER + M6509_A: sprintf(info->s, "A:%02X", m6509->a); break;
case CPUINFO_STR_REGISTER + M6509_X: sprintf(info->s, "X:%02X", m6509->x); break;
case CPUINFO_STR_REGISTER + M6509_Y: sprintf(info->s, "Y:%02X", m6509->y); break;
case CPUINFO_STR_REGISTER + M6509_PC_BANK: sprintf(info->s, "M0:%01X", m6509->pc_bank.b.h2); break;
case CPUINFO_STR_REGISTER + M6509_IND_BANK: sprintf(info->s, "M1:%01X", m6509->ind_bank.b.h2); break;
case CPUINFO_STR_REGISTER + M6509_EA: sprintf(info->s, "EA:%04X", m6509->ea.w.l); break;
case CPUINFO_STR_REGISTER + M6509_ZP: sprintf(info->s, "ZP:%03X", m6509->zp.w.l); break;
}
}

24
src/emu/cpu/m6502/m65ce02.c
View File

@ -55,8 +55,8 @@
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
typedef struct {
typedef struct _m65ce02_Regs m65ce02_Regs;
struct _m65ce02_Regs {
void (*const *insn)(void); /* pointer to the function pointer table */
PAIR ppc; /* previous program counter */
PAIR pc; /* program counter */
@ -77,13 +77,9 @@ typedef struct {
const device_config *device;
read8_machine_func rdmem_id; /* readmem callback for indexed instructions */
write8_machine_func wrmem_id; /* writemem callback for indexed instructions */
} m65ce02_Regs;
static int m65ce02_ICount = 0;
static m65ce02_Regs m65ce02;
};
static void *token;
/***************************************************************
* include the opcode macros, functions and tables
***************************************************************/
@ -148,7 +144,7 @@ INLINE void m65ce02_take_irq(void)
if( !(P & F_I) )
{
EAD = M65CE02_IRQ_VEC;
m65ce02_ICount -= 7;
m65ce02->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -165,7 +161,7 @@ INLINE void m65ce02_take_irq(void)
static CPU_EXECUTE( m65ce02 )
{
m65ce02_ICount = cycles;
m65ce02->icount = cycles;
change_pc(PCD);
@ -202,9 +198,9 @@ static CPU_EXECUTE( m65ce02 )
if( m65ce02.pending_irq )
m65ce02_take_irq();
} while (m65ce02_ICount > 0);
} while (m65ce02->icount > 0);
return cycles - m65ce02_ICount;
return cycles - m65ce02->icount;
}
static void m65ce02_set_irq_line(int irqline, int state)
@ -217,7 +213,7 @@ static void m65ce02_set_irq_line(int irqline, int state)
{
LOG(("M65ce02#%d set_nmi_line(ASSERT)\n", cpu_getactivecpu()));
EAD = M65CE02_NMI_VEC;
m65ce02_ICount -= 7;
m65ce02->icount -= 7;
PUSH(PCH);
PUSH(PCL);
PUSH(P & ~F_B);
@ -330,7 +326,7 @@ void m65ce02_get_info(UINT32 state, cpuinfo *info)
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(m65ce02); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = m65ce02_dasm; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m65ce02_ICount; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m65ce02->icount; break;
case CPUINFO_PTR_M6502_READINDEXED_CALLBACK: info->f = (genf *) m65ce02.rdmem_id; break;
case CPUINFO_PTR_M6502_WRITEINDEXED_CALLBACK: info->f = (genf *) m65ce02.wrmem_id; break;

62
src/emu/cpu/m6502/minc4510.h
View File

@ -17,56 +17,56 @@
#define F_N 0x80
/* some shortcuts for improved readability */
#define A m4510.a
#define X m4510.x
#define Y m4510.y
#define P m4510.p
#define Z m4510.z
#define B m4510.zp.b.h
#define SW m4510.sp.w.l
#define SPL m4510.sp.b.l
#define SPH m4510.sp.b.h
#define SPD m4510.sp.d
#define A m4510->a
#define X m4510->x
#define Y m4510->y
#define P m4510->p
#define Z m4510->z
#define B m4510->zp.b.h
#define SW m4510->sp.w.l
#define SPL m4510->sp.b.l
#define SPH m4510->sp.b.h
#define SPD m4510->sp.d
#define NZ m4510.nz
#define NZ m4510->nz
#define EAL m4510.ea.b.l
#define EAH m4510.ea.b.h
#define EAW m4510.ea.w.l
#define EAD m4510.ea.d
#define EAL m4510->ea.b.l
#define EAH m4510->ea.b.h
#define EAW m4510->ea.w.l
#define EAD m4510->ea.d
#define ZPL m4510.zp.b.l
#define ZPH m4510.zp.b.h
#define ZPW m4510.zp.w.l
#define ZPD m4510.zp.d
#define ZPL m4510->zp.b.l
#define ZPH m4510->zp.b.h
#define ZPW m4510->zp.w.l
#define ZPD m4510->zp.d
#define PCL m4510.pc.b.l
#define PCH m4510.pc.b.h
#define PCW m4510.pc.w.l
#define PCD m4510.pc.d
#define PCL m4510->pc.b.l
#define PCH m4510->pc.b.h
#define PCW m4510->pc.w.l
#define PCD m4510->pc.d
#define PPC m4510.ppc.d
#define PPC m4510->ppc.d
#define IRQ_STATE m4510.irq_state
#define AFTER_CLI m4510.after_cli
#define IRQ_STATE m4510->irq_state
#define AFTER_CLI m4510->after_cli
#define M4510_MEM(addr) (m4510.mem[(addr)>>13]+(addr))
#define M4510_MEM(addr) (m4510->mem[(addr)>>13]+(addr))
#define CHANGE_PC change_pc(M4510_MEM(PCD))
#define PEEK_OP() cpu_readop(M4510_MEM(PCW))
#define RDMEM(addr) program_read_byte_8le(M4510_MEM(addr)); m4510_ICount -= 1
#define WRMEM(addr,data) program_write_byte_8le(M4510_MEM(addr),data); m4510_ICount -= 1
#define RDMEM(addr) program_read_byte_8le(M4510_MEM(addr)); m4510->icount -= 1
#define WRMEM(addr,data) program_write_byte_8le(M4510_MEM(addr),data); m4510->icount -= 1
/***************************************************************
* RDOP read an opcode
***************************************************************/
#undef RDOP
#define RDOP() m4510_cpu_readop(); m4510_ICount -= 1
#define RDOP() m4510_cpu_readop(m4510); m4510->icount -= 1
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#undef RDOPARG
#define RDOPARG() m4510_cpu_readop_arg(); m4510_ICount -= 1
#define RDOPARG() m4510_cpu_readop_arg(m4510); m4510->icount -= 1

64
src/emu/cpu/m6502/mincce02.h
View File

@ -17,55 +17,55 @@
#define F_N 0x80
/* some shortcuts for improved readability */
#define A m65ce02.a
#define X m65ce02.x
#define Y m65ce02.y
#define P m65ce02.p
#define Z m65ce02.z
#define B m65ce02.zp.b.h
#define SW m65ce02.sp.w.l
#define SPL m65ce02.sp.b.l
#define SPH m65ce02.sp.b.h
#define SPD m65ce02.sp.d
#define A m65ce02->a
#define X m65ce02->x
#define Y m65ce02->y
#define P m65ce02->p
#define Z m65ce02->z
#define B m65ce02->zp.b.h
#define SW m65ce02->sp.w.l
#define SPL m65ce02->sp.b.l
#define SPH m65ce02->sp.b.h
#define SPD m65ce02->sp.d
#define NZ m65ce02.nz
#define NZ m65ce02->nz
#define EAL m65ce02.ea.b.l
#define EAH m65ce02.ea.b.h
#define EAW m65ce02.ea.w.l
#define EAD m65ce02.ea.d
#define EAL m65ce02->ea.b.l
#define EAH m65ce02->ea.b.h
#define EAW m65ce02->ea.w.l
#define EAD m65ce02->ea.d
#define ZPL m65ce02.zp.b.l
#define ZPH m65ce02.zp.b.h
#define ZPW m65ce02.zp.w.l
#define ZPD m65ce02.zp.d
#define ZPL m65ce02->zp.b.l
#define ZPH m65ce02->zp.b.h
#define ZPW m65ce02->zp.w.l
#define ZPD m65ce02->zp.d
#define PCL m65ce02.pc.b.l
#define PCH m65ce02.pc.b.h
#define PCW m65ce02.pc.w.l
#define PCD m65ce02.pc.d
#define PCL m65ce02->pc.b.l
#define PCH m65ce02->pc.b.h
#define PCW m65ce02->pc.w.l
#define PCD m65ce02->pc.d
#define PPC m65ce02.ppc.d
#define PPC m65ce02->ppc.d
#define RDMEM_ID m65ce02.rdmem_id
#define WRMEM_ID m65ce02.wrmem_id
#define RDMEM_ID m65ce02->rdmem_id
#define WRMEM_ID m65ce02->wrmem_id
#define IRQ_STATE m65ce02.irq_state
#define AFTER_CLI m65ce02.after_cli
#define IRQ_STATE m65ce02->irq_state
#define AFTER_CLI m65ce02->after_cli
#define CHANGE_PC change_pc(PCD)
/***************************************************************
* RDOP read an opcode
***************************************************************/
#define RDOP() cpu_readop(PCW++); m65ce02_ICount -= 1
#define RDOP() cpu_readop(PCW++); m65ce02->icount -= 1
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#define RDOPARG() cpu_readop_arg(PCW++); m65ce02_ICount -= 1
#define RDOPARG() cpu_readop_arg(PCW++); m65ce02->icount -= 1
#define PEEK_OP() cpu_readop(PCW)
#define RDMEM(addr) program_read_byte_8le(addr); m65ce02_ICount -= 1
#define WRMEM(addr,data) program_write_byte_8le(addr,data); m65ce02_ICount -= 1
#define RDMEM(addr) program_read_byte_8le(addr); m65ce02->icount -= 1
#define WRMEM(addr,data) program_write_byte_8le(addr,data); m65ce02->icount -= 1

78
src/emu/cpu/m6502/ops02.h
View File

@ -32,14 +32,14 @@
#define F_N 0x80
/* some shortcuts for improved readability */
#define A m6502.a
#define X m6502.x
#define Y m6502.y
#define P m6502.p
#define S m6502.sp.b.l
#define SPD m6502.sp.d
#define A m6502->a
#define X m6502->x
#define Y m6502->y
#define P m6502->p
#define S m6502->sp.b.l
#define SPD m6502->sp.d
#define NZ m6502.nz
#define NZ m6502->nz
#define SET_NZ(n) \
if ((n) == 0) P = (P & ~F_N) | F_Z; else P = (P & ~(F_N | F_Z)) | ((n) & F_N)
@ -47,47 +47,47 @@
#define SET_Z(n) \
if ((n) == 0) P |= F_Z; else P &= ~F_Z
#define EAL m6502.ea.b.l
#define EAH m6502.ea.b.h
#define EAW m6502.ea.w.l
#define EAD m6502.ea.d
#define EAL m6502->ea.b.l
#define EAH m6502->ea.b.h
#define EAW m6502->ea.w.l
#define EAD m6502->ea.d
#define ZPL m6502.zp.b.l
#define ZPH m6502.zp.b.h
#define ZPW m6502.zp.w.l
#define ZPD m6502.zp.d
#define ZPL m6502->zp.b.l
#define ZPH m6502->zp.b.h
#define ZPW m6502->zp.w.l
#define ZPD m6502->zp.d
#define PCL m6502.pc.b.l
#define PCH m6502.pc.b.h
#define PCW m6502.pc.w.l
#define PCD m6502.pc.d
#define PCL m6502->pc.b.l
#define PCH m6502->pc.b.h
#define PCW m6502->pc.w.l
#define PCD m6502->pc.d
#define PPC m6502.ppc.d
#define PPC m6502->ppc.d
#define RDMEM_ID(a) m6502.rdmem_id(Machine,a)
#define WRMEM_ID(a,d) m6502.wrmem_id(Machine,a,d)
#define RDMEM_ID(a) m6502->rdmem_id(Machine,a)
#define WRMEM_ID(a,d) m6502->wrmem_id(Machine,a,d)
#define CHANGE_PC change_pc(PCD)
/***************************************************************
* RDOP read an opcode
***************************************************************/
#define RDOP() cpu_readop(PCW++); m6502_ICount -= 1
#define RDOP() cpu_readop(PCW++); m6502->icount -= 1
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#define RDOPARG() cpu_readop_arg(PCW++); m6502_ICount -= 1
#define RDOPARG() cpu_readop_arg(PCW++); m6502->icount -= 1
/***************************************************************
* RDMEM read memory
***************************************************************/
#define RDMEM(addr) program_read_byte_8le(addr); m6502_ICount -= 1
#define RDMEM(addr) program_read_byte_8le(addr); m6502->icount -= 1
/***************************************************************
* WRMEM write memory
***************************************************************/
#define WRMEM(addr,data) program_write_byte_8le(addr,data); m6502_ICount -= 1
#define WRMEM(addr,data) program_write_byte_8le(addr,data); m6502->icount -= 1
/***************************************************************
* BRA branch relative
@ -269,9 +269,9 @@
#define RD_ABX_NP EA_ABX_NP; tmp = RDMEM(EAD)
#define RD_ABY_P EA_ABY_P; tmp = RDMEM(EAD)
#define RD_ABY_NP EA_ABY_NP; tmp = RDMEM(EAD)
#define RD_IDX EA_IDX; tmp = RDMEM_ID(EAD); m6502_ICount -= 1
#define RD_IDY_P EA_IDY_P; tmp = RDMEM_ID(EAD); m6502_ICount -= 1
#define RD_IDY_NP EA_IDY_NP; tmp = RDMEM_ID(EAD); m6502_ICount -= 1
#define RD_IDX EA_IDX; tmp = RDMEM_ID(EAD); m6502->icount -= 1
#define RD_IDY_P EA_IDY_P; tmp = RDMEM_ID(EAD); m6502->icount -= 1
#define RD_IDY_NP EA_IDY_NP; tmp = RDMEM_ID(EAD); m6502->icount -= 1
#define RD_ZPI EA_ZPI; tmp = RDMEM(EAD)
/* write a value from tmp */
@ -281,8 +281,8 @@
#define WR_ABS EA_ABS; WRMEM(EAD, tmp)
#define WR_ABX_NP EA_ABX_NP; WRMEM(EAD, tmp)
#define WR_ABY_NP EA_ABY_NP; WRMEM(EAD, tmp)
#define WR_IDX EA_IDX; WRMEM_ID(EAD, tmp); m6502_ICount -= 1
#define WR_IDY_NP EA_IDY_NP; WRMEM_ID(EAD, tmp); m6502_ICount -= 1
#define WR_IDX EA_IDX; WRMEM_ID(EAD, tmp); m6502->icount -= 1
#define WR_IDY_NP EA_IDY_NP; WRMEM_ID(EAD, tmp); m6502->icount -= 1
#define WR_ZPI EA_ZPI; WRMEM(EAD, tmp)
/* dummy read from the last EA */
@ -438,8 +438,8 @@
* CLI Clear interrupt flag
***************************************************************/
#define CLI \
if ((m6502.irq_state != CLEAR_LINE) && (P & F_I)) { \
m6502.after_cli = 1; \
if ((m6502->irq_state != CLEAR_LINE) && (P & F_I)) { \
m6502->after_cli = 1; \
} \
P &= ~F_I
@ -536,8 +536,8 @@
* set PC to the effective address
***************************************************************/
#define JMP \
if( EAD == PPC && !m6502.pending_irq && !m6502.after_cli ) \
if( m6502_ICount > 0 ) m6502_ICount = 0; \
if( EAD == PPC && !m6502->pending_irq && !m6502->after_cli ) \
if( m6502->icount > 0 ) m6502->icount = 0; \
PCD = EAD; \
CHANGE_PC
@ -625,9 +625,9 @@
RDMEM(SPD); \
if ( P & F_I ) { \
PULL(P); \
if ((m6502.irq_state != CLEAR_LINE) && !(P & F_I)) { \
if ((m6502->irq_state != CLEAR_LINE) && !(P & F_I)) { \
LOG(("M6502#%d PLP sets after_cli\n",cpu_getactivecpu())); \
m6502.after_cli = 1; \
m6502->after_cli = 1; \
} \
} else { \
PULL(P); \
@ -666,10 +666,10 @@
PULL(PCL); \
PULL(PCH); \
P |= F_T | F_B; \
if( (m6502.irq_state != CLEAR_LINE) && !(P & F_I) ) \
if( (m6502->irq_state != CLEAR_LINE) && !(P & F_I) ) \
{ \
LOG(("M6502#%d RTI sets after_cli\n",cpu_getactivecpu())); \
m6502.after_cli = 1; \
m6502->after_cli = 1; \
} \
CHANGE_PC

31
src/emu/cpu/m6502/ops09.h
View File

@ -20,18 +20,15 @@
*
*****************************************************************************/
#define m6502 m6509
#define m6502_ICount m6509_ICount
#define ZPWH m6502->zp.w.h
#define ZPWH m6509.zp.w.h
#define EAWH m6502->ea.w.h
#define EAWH m6509.ea.w.h
#define PBWH m6502->pc_bank.w.h
#define PB m6502->pc_bank.d
#define PBWH m6509.pc_bank.w.h
#define PB m6509.pc_bank.d
#define IBWH m6509.ind_bank.w.h
#define IB m6509.ind_bank.d
#define IBWH m6502->ind_bank.w.h
#define IB m6502->ind_bank.d
#undef CHANGE_PC
#define CHANGE_PC change_pc(PCD|PB)
@ -40,25 +37,25 @@
* RDOP read an opcode
***************************************************************/
#undef RDOP
#define RDOP() cpu_readop((PCW++)|PB); m6502_ICount -= 1
#define RDOP() cpu_readop((PCW++)|PB); m6502->icount -= 1
/***************************************************************
* RDOPARG read an opcode argument
***************************************************************/
#undef RDOPARG
#define RDOPARG() cpu_readop_arg((PCW++)|PB); m6502_ICount -= 1
#define RDOPARG() cpu_readop_arg((PCW++)|PB); m6502->icount -= 1
/***************************************************************
* RDMEM read memory
***************************************************************/
#undef RDMEM
#define RDMEM(addr) program_read_byte_8le(addr); m6502_ICount -= 1
#define RDMEM(addr) program_read_byte_8le(addr); m6502->icount -= 1
/***************************************************************
* WRMEM write memory
***************************************************************/
#undef WRMEM
#define WRMEM(addr,data) program_write_byte_8le(addr,data); m6502_ICount -= 1
#define WRMEM(addr,data) program_write_byte_8le(addr,data); m6502->icount -= 1
/***************************************************************
* push a register onto the stack
@ -134,7 +131,7 @@
EAH = RDMEM(ZPD); \
EAWH = PBWH; \
if (EAL + Y > 0xff) \
m6509_ICount--; \
m6502->icount--; \
EAW += Y
@ -150,7 +147,7 @@
EAH = RDMEM(ZPD); \
EAWH = IBWH; \
if (EAL + Y > 0xff) \
m6509_ICount--; \
m6502->icount--; \
EAW += Y
/***************************************************************
@ -178,14 +175,14 @@
{ \
tmp = RDOPARG(); \
EAW = PCW + (signed char)tmp; \
m6509_ICount -= (PCH == EAH) ? 1 : 2; \
m6502->icount -= (PCH == EAH) ? 1 : 2; \
PCD = EAD|PB; \
CHANGE_PC; \
} \
else \
{ \
PCW++; \
m6509_ICount -= 1; \
m6502->icount -= 1; \
}
/* 6502 ********************************************************

30
src/emu/cpu/m6502/ops4510.h
View File

@ -33,30 +33,30 @@
SPL = X; \
if (PEEK_OP() == 0x2b /*TYS*/ ) { \
UINT8 op = RDOP(); \
(*m4510.insn[op])(); \
(*m4510->insn[op])(m4510); \
}
#undef NOP
#define NOP \
m4510.interrupt_inhibit = 0;
m4510->interrupt_inhibit = 0;
/* c65 docu says transfer of axyz to the mapper register
so no readback!? */
#define MAP \
m4510.interrupt_inhibit = 1; \
m4510.low=m4510.a|(m4510.x<<8); \
m4510.high=m4510.y|(m4510.z<<8); \
m4510.mem[0]=(m4510.low&0x1000) ? (m4510.low&0xfff)<<8:0; \
m4510.mem[1]=(m4510.low&0x2000) ? (m4510.low&0xfff)<<8:0; \
m4510.mem[2]=(m4510.low&0x4000) ? (m4510.low&0xfff)<<8:0; \
m4510.mem[3]=(m4510.low&0x8000) ? (m4510.low&0xfff)<<8:0; \
m4510.mem[4]=(m4510.high&0x1000) ? (m4510.high&0xfff)<<8:0; \
m4510.mem[5]=(m4510.high&0x2000) ? (m4510.high&0xfff)<<8:0; \
m4510.mem[6]=(m4510.high&0x4000) ? (m4510.high&0xfff)<<8:0; \
m4510.mem[7]=(m4510.high&0x8000) ? (m4510.high&0xfff)<<8:0; \
m4510->interrupt_inhibit = 1; \
m4510->low=m4510->a|(m4510->x<<8); \
m4510->high=m4510->y|(m4510->z<<8); \
m4510->mem[0]=(m4510->low&0x1000) ? (m4510->low&0xfff)<<8:0; \
m4510->mem[1]=(m4510->low&0x2000) ? (m4510->low&0xfff)<<8:0; \
m4510->mem[2]=(m4510->low&0x4000) ? (m4510->low&0xfff)<<8:0; \
m4510->mem[3]=(m4510->low&0x8000) ? (m4510->low&0xfff)<<8:0; \
m4510->mem[4]=(m4510->high&0x1000) ? (m4510->high&0xfff)<<8:0; \
m4510->mem[5]=(m4510->high&0x2000) ? (m4510->high&0xfff)<<8:0; \
m4510->mem[6]=(m4510->high&0x4000) ? (m4510->high&0xfff)<<8:0; \
m4510->mem[7]=(m4510->high&0x8000) ? (m4510->high&0xfff)<<8:0; \
CHANGE_PC; \
m4510_ICount -= 3; \
m4510->icount -= 3; \
{ \
UINT8 op = RDOP(); \
(*m4510.insn[op])(); \
(*m4510->insn[op])(m4510); \
}

4
src/emu/cpu/m6502/opsc02.h
View File

@ -128,11 +128,11 @@
#define RD_ABX_C02_P EA_ABX_C02_P; tmp = RDMEM(EAD)
#define RD_ABX_C02_NP EA_ABX_C02_NP; tmp = RDMEM(EAD)
#define RD_ABY_C02_P EA_ABY_C02_P; tmp = RDMEM(EAD)
#define RD_IDY_C02_P EA_IDY_C02_P; tmp = RDMEM_ID(EAD); m6502_ICount -= 1
#define RD_IDY_C02_P EA_IDY_C02_P; tmp = RDMEM_ID(EAD); m6502->icount -= 1
#define WR_ABX_C02_NP EA_ABX_C02_NP; WRMEM(EAD, tmp)
#define WR_ABY_C02_NP EA_ABY_C02_NP; WRMEM(EAD, tmp)
#define WR_IDY_C02_NP EA_IDY_C02_NP; WRMEM_ID(EAD, tmp); m6502_ICount -= 1
#define WR_IDY_C02_NP EA_IDY_C02_NP; WRMEM_ID(EAD, tmp); m6502->icount -= 1
/* 65C02********************************************************

4
src/emu/cpu/m6502/t6502.c
View File

@ -23,7 +23,7 @@
*****************************************************************************/
#undef OP
#define OP(nn) INLINE void m6502_##nn(void)
#define OP(nn) INLINE void m6502_##nn(m6502_Regs *m6502)
/*****************************************************************************
*****************************************************************************
@ -323,7 +323,7 @@ OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */
/* and here's the array of function pointers */
static void (*const insn6502[0x100])(void) = {
static void (*const insn6502[0x100])(m6502_Regs *m6502) = {
m6502_00,m6502_01,m6502_02,m6502_03,m6502_04,m6502_05,m6502_06,m6502_07,
m6502_08,m6502_09,m6502_0a,m6502_0b,m6502_0c,m6502_0d,m6502_0e,m6502_0f,
m6502_10,m6502_11,m6502_12,m6502_13,m6502_14,m6502_15,m6502_16,m6502_17,

4
src/emu/cpu/m6502/t6509.c
View File

@ -24,7 +24,7 @@
*****************************************************************************/
#undef OP
#define OP(nn) INLINE void m6509_##nn(void)
#define OP(nn) INLINE void m6509_##nn(m6509_Regs *m6502)
OP(00) { BRK; } /* 7 BRK */
OP(20) { JSR; } /* 6 JSR */
@ -314,7 +314,7 @@ OP(bf) { int tmp; RD_ABY_P; LAX; } /* 4 LAX ABY page penalty */
OP(df) { int tmp; RD_ABX_NP; WB_EA; DCP; WB_EA; } /* 7 DCP ABX */
OP(ff) { int tmp; RD_ABX_NP; WB_EA; ISB; WB_EA; } /* 7 ISB ABX */
static void (*const insn6509[0x100])(void) = {
static void (*const insn6509[0x100])(m6509_Regs *) = {
m6509_00,m6509_01,m6509_02,m6509_03,m6509_04,m6509_05,m6509_06,m6509_07,
m6509_08,m6509_09,m6509_0a,m6509_0b,m6509_0c,m6509_0d,m6509_0e,m6509_0f,
m6509_10,m6509_11,m6509_12,m6509_13,m6509_14,m6509_15,m6509_16,m6509_17,

6
src/emu/cpu/m6502/t65c02.c
View File

@ -24,7 +24,7 @@
*****************************************************************************/
#undef OP
#define OP(nn) INLINE void m65c02_##nn(void)
#define OP(nn) INLINE void m65c02_##nn(m6502_Regs *m6502)
/*****************************************************************************
*****************************************************************************
@ -326,7 +326,7 @@ OP(bf) { int tmp; RD_ZPG; BBS(3); } /* 5-7 BBS3 ZPG */
OP(df) { int tmp; RD_ZPG; BBS(5); } /* 5-7 BBS5 ZPG */
OP(ff) { int tmp; RD_ZPG; BBS(7); } /* 5-7 BBS7 ZPG */
static void (*const insn65c02[0x100])(void) = {
static void (*const insn65c02[0x100])(m6502_Regs *m6502) = {
m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07,
m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f,
m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17,
@ -371,7 +371,7 @@ OP(7e_wdc) { int tmp; RD_ABX_P; RD_EA; ROR; WB_EA; } /* 6 ROR ABX page pena
OP(de_wdc) { int tmp; RD_ABX_P; RD_EA; DEC; WB_EA; } /* 6 DEC ABX page penalty */
OP(fe_wdc) { int tmp; RD_ABX_P; RD_EA; INC; WB_EA; } /* 6 INC ABX page penalty */
static void (*const insnwdc65c02[0x100])(void) = {
static void (*const insnwdc65c02[0x100])(m6502_Regs *m6502) = {
m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07,
m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f,
m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17,

8
src/emu/cpu/m6502/t65ce02.c
View File

@ -21,9 +21,9 @@
#undef OP
#ifdef M4510
#define OP(nn) INLINE void m4510_##nn(void)
#define OP(nn) INLINE void m4510_##nn(m4510_Regs *m4510)
#else
#define OP(nn) INLINE void m65ce02_##nn(void)
#define OP(nn) INLINE void m65ce02_##nn(m65ce02_Regs *m65ce02)
#endif
/*****************************************************************************
@ -326,7 +326,7 @@ OP(df) { int tmp; RD_ZPG; BBS(5); } /* 4 BBS5 ZPG */
OP(ff) { int tmp; RD_ZPG; BBS(7); } /* 4 BBS7 ZPG */
#ifdef M4510
static void (*const insn4510[0x100])(void) = {
static void (*const insn4510[0x100])(m4510_Regs *) = {
m4510_00,m4510_01,m4510_02,m4510_03,m4510_04,m4510_05,m4510_06,m4510_07,
m4510_08,m4510_09,m4510_0a,m4510_0b,m4510_0c,m4510_0d,m4510_0e,m4510_0f,
m4510_10,m4510_11,m4510_12,m4510_13,m4510_14,m4510_15,m4510_16,m4510_17,
@ -361,7 +361,7 @@ static void (*const insn4510[0x100])(void) = {
m4510_f8,m4510_f9,m4510_fa,m4510_fb,m4510_fc,m4510_fd,m4510_fe,m4510_ff
};
#else
static void (*const insn65ce02[0x100])(void) = {
static void (*const insn65ce02[0x100])(m4510_Regs *) = {
m65ce02_00,m65ce02_01,m65ce02_02,m65ce02_03,m65ce02_04,m65ce02_05,m65ce02_06,m65ce02_07,
m65ce02_08,m65ce02_09,m65ce02_0a,m65ce02_0b,m65ce02_0c,m65ce02_0d,m65ce02_0e,m65ce02_0f,
m65ce02_10,m65ce02_11,m65ce02_12,m65ce02_13,m65ce02_14,m65ce02_15,m65ce02_16,m65ce02_17,

4
src/emu/cpu/m6502/t65sc02.c
View File

@ -32,7 +32,7 @@
*/
#undef OP
#define OP(nn) INLINE void m65sc02_##nn(void)
#define OP(nn) INLINE void m65sc02_##nn(m6502_Regs *m6502)
/*****************************************************************************
*****************************************************************************
@ -43,7 +43,7 @@
* op temp cycles rdmem opc wrmem ********************/
OP(63) { BSR; } /* 5? BSR */
static void (*const insn65sc02[0x100])(void) = {
static void (*const insn65sc02[0x100])(m6502_Regs *m6502) = {
m65c02_00,m65c02_01,m65c02_02,m65c02_03,m65c02_04,m65c02_05,m65c02_06,m65c02_07,
m65c02_08,m65c02_09,m65c02_0a,m65c02_0b,m65c02_0c,m65c02_0d,m65c02_0e,m65c02_0f,
m65c02_10,m65c02_11,m65c02_12,m65c02_13,m65c02_14,m65c02_15,m65c02_16,m65c02_17,

28
src/emu/cpu/m6502/tdeco16.c
View File

@ -6,7 +6,7 @@
#define DECO16_VERBOSE 0
#undef OP
#define OP(nn) INLINE void deco16_##nn(void)
#define OP(nn) INLINE void deco16_##nn(m6502_Regs *m6502)
#define DECO16_BRK \
logerror("%04x: BRK\n",activecpu_get_pc()); \
@ -85,7 +85,7 @@ OP(03) { RD_DUM; ILL; } /* 2 ILL */
OP(23) {
int tmp;
m6502_ICount -= 1;
m6502->icount -= 1;
RD_IMM;
if (DECO16_VERBOSE)
@ -95,7 +95,7 @@ OP(43) { RD_DUM; ILL; } /* 2 ILL */
OP(63) {
int tmp;
m6502_ICount -= 1;
m6502->icount -= 1;
RD_IMM;
if (DECO16_VERBOSE)
@ -105,7 +105,7 @@ OP(83) { RD_DUM; ILL; } /* 2 ILL */
OP(a3) {
int tmp;
m6502_ICount -= 1;
m6502->icount -= 1;
RD_IMM;
if (DECO16_VERBOSE)
@ -114,7 +114,7 @@ OP(a3) {
OP(c3) { RD_DUM; ILL; } /* 2 ILL */
OP(e3) { RD_DUM; ILL; } /* 2 ILL */
OP(13) { int tmp; m6502_ICount -= 1; RD_IMM;
OP(13) { int tmp; m6502->icount -= 1; RD_IMM;
if (DECO16_VERBOSE)
logerror("%04x: OP13 %02x\n",activecpu_get_pc(),tmp);
@ -189,14 +189,14 @@ OP(27) { RD_DUM; ILL; } /* 2 ILL / 5 RMB2 ZPG ?? */
OP(47) { RD_DUM; ILL; } /* 2 ILL / 5 RMB4 ZPG ?? */
OP(67) {
int tmp; RD_IMM;
m6502.a=io_read_byte_8le(0);
m6502->a=io_read_byte_8le(0);
// logerror("%04x: VBL (0x67)\n",activecpu_get_pc());
// really - wait for status?
} /* */
OP(87) { int tmp; m6502_ICount -= 1; RD_IMM;
OP(87) { int tmp; m6502->icount -= 1; RD_IMM;
logerror("%04x: OP87 %02x\n",activecpu_get_pc(),tmp);
} /* */
@ -267,15 +267,15 @@ OP(f7) { RD_DUM; ILL; } /* 2 ILL / 5 SMB7 ZPG ?? */
#define deco16_da m65c02_da /* 3 PHX */
#define deco16_fa m65c02_fa /* 4 PLX */
OP(0b) { int tmp; m6502_ICount -= 1; RD_IMM;
OP(0b) { int tmp; m6502->icount -= 1; RD_IMM;
logerror("%04x: OP0B %02x\n",activecpu_get_pc(),tmp);
}
OP(2b) { RD_DUM; ILL; } /* 2 ILL */
OP(4b) { int tmp; m6502_ICount -= 1; RD_IMM;
OP(4b) { int tmp; m6502->icount -= 1; RD_IMM;
logerror("%04x: OP4B %02x\n",activecpu_get_pc(),tmp);
// m6502.a=io_read_byte_8le(0);
// m6502->a=io_read_byte_8le(0);
//tilt??
@ -297,7 +297,7 @@ OP(9b) { RD_DUM; ILL; } /* 2 ILL */
OP(bb) {
int tmp;
m6502_ICount -= 1;
m6502->icount -= 1;
RD_IMM;
if (DECO16_VERBOSE)
@ -364,7 +364,7 @@ OP(0f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR0 ZPG ?? */
OP(2f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR2 ZPG ?? */
OP(4f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR4 ZPG ?? */
OP(6f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR6 ZPG ?? */
OP(8f) { int tmp; m6502_ICount -= 1; RD_IMM;
OP(8f) { int tmp; m6502->icount -= 1; RD_IMM;
logerror("%04x: BANK (8F) %02x\n",activecpu_get_pc(),tmp);
io_write_byte_8le(0,tmp);
@ -380,7 +380,7 @@ OP(1f) { RD_DUM; ILL; } /* 2 ILL / 5 BBR1 ZPG ?? */
OP(3f) {
int tmp;
m6502_ICount -= 1;
m6502->icount -= 1;
RD_IMM;
if (DECO16_VERBOSE)
@ -393,7 +393,7 @@ OP(bf) { RD_DUM; ILL; } /* 2 ILL / 5 BBS3 ZPG ?? */
OP(df) { RD_DUM; ILL; } /* 2 ILL / 5 BBS5 ZPG ?? */
OP(ff) { RD_DUM; ILL; } /* 2 ILL / 5 BBS7 ZPG ?? */
static void (*const insndeco16[0x100])(void) = {
static void (*const insndeco16[0x100])(m6502_Regs *m6502) = {
deco16_00,deco16_01,deco16_02,deco16_03,deco16_04,deco16_05,deco16_06,deco16_07,
deco16_08,deco16_09,deco16_0a,deco16_0b,deco16_0c,deco16_0d,deco16_0e,deco16_0f,
deco16_10,deco16_11,deco16_12,deco16_13,deco16_14,deco16_15,deco16_16,deco16_17,

4
src/emu/cpu/m6502/tn2a03.c
View File

@ -32,7 +32,7 @@
#undef OP
#define OP(nn) INLINE void n2a03_##nn(void)
#define OP(nn) INLINE void n2a03_##nn(m6502_Regs *m6502)
/*****************************************************************************
*****************************************************************************
@ -60,7 +60,7 @@ OP(ed) { int tmp; RD_ABS; SBC_NES; } /* 4 SBC ABS */
OP(7d) { int tmp; RD_ABX_P; ADC_NES; } /* 4 ADC ABX page penalty */
OP(fd) { int tmp; RD_ABX_P; SBC_NES; } /* 4 SBC ABX page penalty */
static void (*const insn2a03[0x100])(void) = {
static void (*const insn2a03[0x100])(m6502_Regs *m6502) = {
m6502_00,m6502_01,m6502_02,m6502_03,m6502_04,m6502_05,m6502_06,m6502_07,
m6502_08,m6502_09,m6502_0a,m6502_0b,m6502_0c,m6502_0d,m6502_0e,m6502_0f,
m6502_10,m6502_11,m6502_12,m6502_13,m6502_14,m6502_15,m6502_16,m6502_17,