mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
Revert "nes_vt: APU improvements (#4476)"
This reverts commit 6d3238ead8.
This commit is contained in:
Vas Crabb
parent
a93943e002
commit
e55e20c79e
@ -642,7 +642,6 @@ end
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---------------------------------------------------
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-- Nintendo custom sound chips
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--@src/devices/sound/nes_apu.h,SOUNDS["NES_APU"] = true
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--@src/devices/sound/nes_vt_apu.h,SOUNDS["NES_APU"] = true
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---------------------------------------------------
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if (SOUNDS["NES_APU"]~=null) then
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@ -650,8 +649,6 @@ if (SOUNDS["NES_APU"]~=null) then
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MAME_DIR .. "src/devices/sound/nes_apu.cpp",
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MAME_DIR .. "src/devices/sound/nes_apu.h",
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MAME_DIR .. "src/devices/sound/nes_defs.h",
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MAME_DIR .. "src/devices/sound/nes_vt_apu.cpp",
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MAME_DIR .. "src/devices/sound/nes_vt_apu.h"
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}
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end
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@ -101,18 +101,13 @@ static void create_noise(u8 *buf, const int bits, int size)
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DEFINE_DEVICE_TYPE(NES_APU, nesapu_device, "nesapu", "N2A03 APU")
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nesapu_device::nesapu_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: nesapu_device(mconfig, tag, NES_APU, owner, clock)
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{
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}
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nesapu_device::nesapu_device(const machine_config &mconfig, const char *tag, device_type type, device_t *owner, u32 clock)
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: device_t(mconfig, type, tag, owner, clock)
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: device_t(mconfig, NES_APU, tag, owner, clock)
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, device_sound_interface(mconfig, *this)
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, m_mem_read_cb(*this)
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, m_irq_handler(*this)
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, m_samps_per_sync(0)
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, m_buffer_size(0)
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, m_stream(nullptr)
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, m_irq_handler(*this)
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, m_mem_read_cb(*this)
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{
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for (auto & elem : m_noise_lut)
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{
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@ -170,7 +165,14 @@ void nesapu_device::calculate_rates()
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void nesapu_device::device_start()
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{
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apu_init();
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// resolve callbacks
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m_irq_handler.resolve_safe();
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m_mem_read_cb.resolve_safe(0x00);
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create_noise(m_noise_lut, 13, apu_t::NOISE_LONG);
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calculate_rates();
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/* register for save */
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for (int i = 0; i < 2; i++)
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{
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@ -228,18 +230,6 @@ void nesapu_device::device_start()
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#endif
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}
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void nesapu_device::apu_init()
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{
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// resolve callbacks
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m_irq_handler.resolve_safe();
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m_mem_read_cb.resolve_safe(0x00);
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create_noise(m_noise_lut, 13, apu_t::NOISE_LONG);
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calculate_rates();
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}
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/* TODO: sound channels should *ALL* have DC volume decay */
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/* OUTPUT SQUARE WAVE SAMPLE (VALUES FROM -16 to +15) */
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@ -54,33 +54,16 @@ public:
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virtual void device_reset() override;
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virtual void device_clock_changed() override;
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virtual u8 read(offs_t offset);
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virtual void write(offs_t offset, u8 data);
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u8 read(offs_t offset);
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void write(offs_t offset, u8 data);
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protected:
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nesapu_device(const machine_config &mconfig, const char *tag, device_type type, device_t *owner, u32 clock);
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// device-level overrides
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virtual void device_start() override;
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// sound stream update overrides
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virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override;
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void apu_init();
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void calculate_rates();
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void create_syncs(unsigned long sps);
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s8 apu_square(apu_t::square_t *chan);
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s8 apu_triangle(apu_t::triangle_t *chan);
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s8 apu_noise(apu_t::noise_t *chan);
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s8 apu_dpcm(apu_t::dpcm_t *chan);
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inline void apu_regwrite(int address, u8 value);
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inline u8 apu_read(int address);
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inline void apu_write(int address, u8 value);
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devcb_read8 m_mem_read_cb;
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devcb_write_line m_irq_handler;
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private:
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/* GLOBAL CONSTANTS */
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static constexpr unsigned SYNCS_MAX1 = 0x20;
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@ -95,7 +78,16 @@ private:
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u32 m_sync_times1[SYNCS_MAX1]; /* Samples per sync table */
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u32 m_sync_times2[SYNCS_MAX2]; /* Samples per sync table */
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sound_stream *m_stream;
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devcb_write_line m_irq_handler;
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devcb_read8 m_mem_read_cb;
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void calculate_rates();
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void create_syncs(unsigned long sps);
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s8 apu_square(apu_t::square_t *chan);
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s8 apu_triangle(apu_t::triangle_t *chan);
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s8 apu_noise(apu_t::noise_t *chan);
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s8 apu_dpcm(apu_t::dpcm_t *chan);
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inline void apu_regwrite(int address, u8 value);
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};
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DECLARE_DEVICE_TYPE(NES_APU, nesapu_device)
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@ -1,289 +0,0 @@
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// license:BSD-3-Clause
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// copyright-holders:David Shah
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/*****************************************************************************
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MAME/MESS VTxx APU CORE
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*****************************************************************************/
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#include "emu.h"
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#include "nes_vt_apu.h"
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#define VTXX_NTSC_XTAL XTAL(21'477'272)
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#define VTXX_NTSC_APU_CLOCK (VTXX_NTSC_XTAL/12)
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DEFINE_DEVICE_TYPE(NES_VT_APU, nesapu_vt_device, "nesapu_vt", "VTxx APU")
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DEFINE_DEVICE_TYPE(NES_VT_APU_SLAVE, nesapu_vt_slave_device, "nesapu_vt_slave", "VTxx APU (slave)")
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nesapu_vt_device::nesapu_vt_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: nesapu_device(mconfig, tag, NES_VT_APU, owner, clock),
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m_xop2(*this, "nesapu_vt_slave"),
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m_rom_read_cb(*this)
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{
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}
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void nesapu_vt_device::device_start()
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{
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apu_init();
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m_rom_read_cb.resolve_safe(0x00);
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if(!m_xop2->started())
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throw device_missing_dependencies();
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for (int i = 0; i < 2; i++)
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{
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save_item(NAME(m_apu_vt.vt33_pcm[i].address), i);
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save_item(NAME(m_apu_vt.vt33_pcm[i].volume), i);
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save_item(NAME(m_apu_vt.vt33_pcm[i].enabled), i);
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save_item(NAME(m_apu_vt.vt33_pcm[i].playing), i);
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save_item(NAME(m_apu_vt.vt33_pcm[i].phaseacc), i);
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save_item(NAME(m_apu_vt.vt33_pcm[i].curr), i);
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}
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save_item(NAME(m_apu_vt.vt03_pcm.phaseacc));
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save_item(NAME(m_apu_vt.vt03_pcm.regs));
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save_item(NAME(m_apu_vt.vt03_pcm.address));
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save_item(NAME(m_apu_vt.vt03_pcm.length));
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save_item(NAME(m_apu_vt.vt03_pcm.remaining_bytes));
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save_item(NAME(m_apu_vt.vt03_pcm.enabled));
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save_item(NAME(m_apu_vt.vt03_pcm.irq_occurred));
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save_item(NAME(m_apu_vt.vt03_pcm.vol));
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save_item(NAME(m_apu_vt.extra_regs));
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save_item(NAME(m_apu_vt.vt3x_sel_channel));
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save_item(NAME(m_apu_vt.use_vt03_pcm));
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save_item(NAME(m_apu_vt.use_vt3x_pcm));
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}
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nesapu_vt_slave_device::nesapu_vt_slave_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock)
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: nesapu_device(mconfig, tag, NES_VT_APU_SLAVE, owner, clock)
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{
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}
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void nesapu_vt_slave_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
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{
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//TODO: any tweaks needed here:
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nesapu_device::sound_stream_update(stream, inputs, outputs, samples);
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}
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void nesapu_vt_device::sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples)
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{
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std::unique_ptr<stream_sample_t[]> pbuf = std::make_unique<stream_sample_t[]>(samples);
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std::unique_ptr<stream_sample_t[]> sbuf = std::make_unique<stream_sample_t[]>(samples);
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stream_sample_t *pptr = pbuf.get(), *sptr = sbuf.get();
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// Dual legacy sound generators
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nesapu_device::sound_stream_update(stream, inputs, &pptr, samples);
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m_xop2->sound_stream_update(stream, inputs, &sptr, samples);
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int accum;
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memset( outputs[0], 0, samples*sizeof(*outputs[0]) );
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for(int i = 0; i < samples; i++)
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{
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accum = 0;
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accum += pbuf[i] >> 8;
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accum += sbuf[i] >> 8; //TODO: mixing between generators?
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accum += vt03_pcm(&m_apu_vt.vt03_pcm);
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accum += vt3x_pcm(&(m_apu_vt.vt33_pcm[0]));
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accum += vt3x_pcm(&(m_apu_vt.vt33_pcm[1]));
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/* 8-bit clamps */
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if (accum > 127)
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accum = 127;
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else if (accum < -128)
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accum = -128;
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*(outputs[0]++)=accum<<8;
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}
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}
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s8 nesapu_vt_device::vt03_pcm(apu_vt_t::vt03_pcm_t *ch) {
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if (ch->enabled) {
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int freq = dpcm_clocks[ch->regs[0] & 0x0F];
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ch->phaseacc -= 4;
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while (ch->phaseacc < 0 && ch->enabled)
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{
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ch->phaseacc += freq;
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u8 data = u8(m_mem_read_cb(ch->address));
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logerror("pcm fetch %04x %d\n", ch->address, int(data));
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ch->vol = data;
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ch->address++;
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ch->remaining_bytes--;
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if (ch->remaining_bytes == 0)
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{
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if (ch->regs[0] & 0x80)
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{
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ch->irq_occurred = true;
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m_irq_handler(true);
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}
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if (ch->regs[0] & 0x40)
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reset_vt03_pcm(ch);
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else
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ch->enabled = false;
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}
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}
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return ch->vol - 128;
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} else {
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return 0;
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}
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}
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s8 nesapu_vt_device::vt3x_pcm(apu_vt_t::vt3x_pcm_t *ch) {
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if (ch->enabled && ch->playing) {
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const int freq = 0x6F;
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ch->phaseacc -= 4;
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while (ch->phaseacc < 0)
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{
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ch->phaseacc += freq;
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u8 sample = m_rom_read_cb(ch->address);
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// logerror("pcm fetch %06x %d\n", ch->address, int(sample));
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if (sample == 0xFF) {
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ch->playing = false;
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ch->enabled = false;
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} else {
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ch->address++;
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ch->curr = s8((s8(sample - 128) * u16(ch->volume)) / 128);
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// logerror("scaled %d\n", int(ch->curr));
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}
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}
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return ch->curr;
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}
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return 0;
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}
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void nesapu_vt_device::reset_vt03_pcm(apu_vt_t::vt03_pcm_t *ch) {
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// logerror("reset vt03 pwm\n");
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ch->address = ((~m_apu_vt.extra_regs[0]) & 0x03) << 14 | m_apu_vt.vt03_pcm.regs[2] << 6;
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ch->remaining_bytes = m_apu_vt.vt03_pcm.regs[3] << 4;
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ch->length = m_apu_vt.vt03_pcm.regs[3] << 4;
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ch->enabled = true;
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ch->irq_occurred = true;
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}
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void nesapu_vt_device::vt_apu_write(uint8_t address, uint8_t data) {
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if(address == 0x35 && !m_apu_vt.use_vt3x_pcm)
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{
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//When VT3x PCM disabled, 4035 controls XOP2
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m_xop2->write(0x15, data & 0x0F);
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m_apu_vt.extra_regs[0x05] = data;
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} else if (address >= 0x10 && address <= 0x13) {
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m_apu_vt.vt03_pcm.regs[address - 0x10] = data;
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if (address == 0x10) {
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m_apu_vt.vt03_pcm.irq_occurred = false;
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m_irq_handler(false);
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}
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if (m_apu_vt.use_vt3x_pcm && (address == 0x12) && !m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].enabled) {
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].address &= ~(0xFF << 6);
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].address |= (data << 6);
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}
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} else if(address >= 0x30 && address <= 0x36) {
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if (address == 0x30) {
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m_apu_vt.use_vt03_pcm = (data & 0x10) != 0;
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} else if (address == 0x33) {
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m_apu_vt.use_vt3x_pcm = (data & 0x80);
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m_apu_vt.vt33_pcm[0].enabled = (data & 0x10);
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m_apu_vt.vt33_pcm[1].enabled = (data & 0x08);
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} else if (address == 0x31) {
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m_apu_vt.vt3x_sel_channel = 0;
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m_apu_vt.vt33_pcm[0].volume = data;
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} else if (address == 0x32) {
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m_apu_vt.vt3x_sel_channel = 1;
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m_apu_vt.vt33_pcm[1].volume = data;
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} else if (address == 0x35 && !m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].enabled) {
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].address &= ~(0x7F << 14);
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].address |= ((data & 0x7F) << 14);
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} else if (address == 0x36 && !m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].enabled) {
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].address &= ~(0xFF << 21);
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].address |= (data << 21);
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m_apu_vt.vt33_pcm[m_apu_vt.vt3x_sel_channel].playing = true;
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}
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m_apu_vt.extra_regs[address - 0x30] = data;
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} else if (address == 0x15) {
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uint8_t nes_val = data;
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if(m_apu_vt.use_vt03_pcm || m_apu_vt.use_vt3x_pcm)
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{
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if (m_apu_vt.use_vt03_pcm) {
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if (nes_val & 0x10)
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reset_vt03_pcm(&m_apu_vt.vt03_pcm);
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else
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m_apu_vt.vt03_pcm.enabled = false;
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}
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nes_val &= 0x0F;
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}
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nesapu_device::write(0x15, nes_val);
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}
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}
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uint8_t nesapu_vt_device::vt_apu_read(uint8_t address) {
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if(address >= 0x30 && address <= 0x36)
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{
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return m_apu_vt.extra_regs[address - 0x30];
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} else if (address >= 0x10 && address <= 0x13) {
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return m_apu_vt.vt03_pcm.regs[address - 0x10];
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} else if (address == 0x15) {
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uint8_t base = nesapu_device::read(0x15);
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if(m_apu_vt.use_vt03_pcm)
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{
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base &= 0x4F;
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base |= (m_apu_vt.vt03_pcm.enabled << 4);
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base |= m_apu_vt.vt03_pcm.irq_occurred ? 0x80 : 0x00;
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}
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return base;
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}
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return 0x00;
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}
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u8 nesapu_vt_device::read(offs_t address)
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{
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// logerror("nesapu_vt read %04x\n", 0x4000 + address);
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if (address <= 0x0F) {
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return nesapu_device::read(address);
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} else if (address >= 0x10 && address <= 0x13) {
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if(!m_apu_vt.use_vt03_pcm)
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return nesapu_device::read(address);
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else
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return vt_apu_read(address);
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} else if (address >= 0x20 && address <= 0x2F) {
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return m_xop2->read(address - 0x20);
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} else if (address == 0x15 || (address >= 0x30 && address <= 0x36)) {
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return vt_apu_read(address);
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} else {
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logerror("nesapu_vt read %04x\n", 0x4000 + address);
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return 0x00;
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}
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}
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void nesapu_vt_device::write(offs_t address, u8 value)
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{
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// logerror("nesapu_vt write %04x %02x\n", 0x4000 + address, value);
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||||
if (address <= 0x0F) {
|
||||
nesapu_device::write(address, value);
|
||||
} else if (address >= 0x10 && address <= 0x13) {
|
||||
//PCM registers affect both new and legacy APU
|
||||
if (m_apu_vt.use_vt03_pcm || m_apu_vt.use_vt3x_pcm)
|
||||
vt_apu_write(address, value);
|
||||
else
|
||||
nesapu_device::write(address, value);
|
||||
} else if (address >= 0x20 && address <= 0x2F) {
|
||||
m_xop2->write(address - 0x20, value);
|
||||
} else if (address == 0x15 || (address >= 0x30 && address <= 0x36)) {
|
||||
vt_apu_write(address, value);
|
||||
} else {
|
||||
logerror("nesapu_vt write %04x %02x\n", 0x4000 + address, value);
|
||||
}
|
||||
}
|
||||
|
||||
MACHINE_CONFIG_START(nesapu_vt_device::device_add_mconfig)
|
||||
MCFG_DEVICE_ADD("nesapu_vt_slave", NES_VT_APU_SLAVE, VTXX_NTSC_APU_CLOCK)
|
||||
MACHINE_CONFIG_END
|
||||
@ -1,140 +0,0 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:David Shah
|
||||
/*****************************************************************************
|
||||
|
||||
MAME/MESS VTxx APU CORE
|
||||
|
||||
This core emulates the audio functionality of the V.R. Technology VTxx series
|
||||
of "enhanced NES" system on chips.
|
||||
|
||||
The VTxx APU is effectively two NES APUs with added PCM functionality.
|
||||
|
||||
APU 1 ("XOP1"), is a full-featured NES APU mapped at 0x4000-0x4013, and has
|
||||
full NES functionality plus a new PCM mode in addition to NES-style DPCM,
|
||||
with controls for that at 0x4030 and 0x4031.
|
||||
|
||||
APU2 ("XOP2"), has all functions except DPCM/PCM and is mapped at
|
||||
0x4020-0x402F.
|
||||
|
||||
Newer devices, from the VT09 (?) onwards add new banking registers for PCM,
|
||||
seperate from the CPU's PRG banking registers, located at 0x4125, 0x4126 (high
|
||||
address bank) and 0x4127, 0x4128 (relative high address bank).
|
||||
|
||||
Even newer devices from the VT33 (??) onwards have a new two-channel PCM mode,
|
||||
limited info known. Possible map below, credit to NewRisingSun for reverse
|
||||
engineering this.
|
||||
0x4031,
|
||||
0x4032: select channel 1 or 2 respectively and set volume
|
||||
0x4033: bit 7: global enable, bit 4: ch1 enable, bit3: ch2 enable
|
||||
0x4012: set start address bits 13..6 of selected channel
|
||||
0x4035: set start address bits 20..14 of selected channel
|
||||
0x4036: set start address bits 24..21 of selected channel, and start playing
|
||||
Playback seems to be stopped by a 0xFF sample.
|
||||
This mode will be called enhanced PCM for lack of a better name
|
||||
*****************************************************************************/
|
||||
|
||||
#ifndef MAME_SOUND_NES_VT_APU_H
|
||||
#define MAME_SOUND_NES_VT_APU_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "nes_apu.h"
|
||||
|
||||
struct apu_vt_t {
|
||||
struct vt03_pcm_t
|
||||
{
|
||||
vt03_pcm_t()
|
||||
{
|
||||
for (auto & elem : regs)
|
||||
elem = 0;
|
||||
}
|
||||
|
||||
float phaseacc = 0.0;
|
||||
uint8_t regs[4];
|
||||
uint32_t address = 0;
|
||||
uint32_t length = 0;
|
||||
uint32_t remaining_bytes = 0;
|
||||
bool enabled = false, irq_occurred = false;
|
||||
uint8_t vol = 0;
|
||||
};
|
||||
|
||||
struct vt3x_pcm_t
|
||||
{
|
||||
vt3x_pcm_t()
|
||||
{
|
||||
for (auto & elem : regs)
|
||||
elem = 0;
|
||||
}
|
||||
|
||||
uint8_t rate = 0;
|
||||
float phaseacc = 0.0;
|
||||
uint32_t address = 0;
|
||||
uint8_t volume = 0;
|
||||
bool enabled = false, playing = false;
|
||||
uint8_t regs[4];
|
||||
int8_t curr = 0;
|
||||
};
|
||||
|
||||
uint8_t extra_regs[7]; //4030 .. 4037
|
||||
|
||||
apu_vt_t()
|
||||
{
|
||||
for (auto & elem : extra_regs)
|
||||
elem = 0;
|
||||
}
|
||||
|
||||
|
||||
int vt3x_sel_channel = 0;
|
||||
vt03_pcm_t vt03_pcm;
|
||||
vt3x_pcm_t vt33_pcm[2];
|
||||
bool use_vt03_pcm = false, use_vt3x_pcm = false;
|
||||
};
|
||||
|
||||
// This represents the "slave APU", which is modified to disable DPCM
|
||||
class nesapu_vt_slave_device : public nesapu_device
|
||||
{
|
||||
public:
|
||||
nesapu_vt_slave_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override;
|
||||
};
|
||||
|
||||
class nesapu_vt_device : public nesapu_device
|
||||
{
|
||||
public:
|
||||
nesapu_vt_device(const machine_config &mconfig, const char *tag, device_t *owner, u32 clock);
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
|
||||
template <class Object> devcb_base &set_rom_read_callback(Object &&cb) { return m_rom_read_cb.set_callback(std::forward<Object>(cb)); }
|
||||
auto rom_read() { return m_rom_read_cb.bind(); }
|
||||
|
||||
virtual void sound_stream_update(sound_stream &stream, stream_sample_t **inputs, stream_sample_t **outputs, int samples) override;
|
||||
|
||||
virtual u8 read(offs_t offset) override;
|
||||
virtual void write(offs_t offset, u8 data) override;
|
||||
|
||||
protected:
|
||||
|
||||
virtual void device_start() override;
|
||||
|
||||
|
||||
uint8_t vt_apu_read(uint8_t address);
|
||||
void vt_apu_write(uint8_t address, uint8_t data);
|
||||
void vt_apu_regwrite(uint8_t address, uint8_t data);
|
||||
|
||||
apu_vt_t m_apu_vt;
|
||||
|
||||
required_device<nesapu_vt_slave_device> m_xop2;
|
||||
|
||||
s8 vt03_pcm(apu_vt_t::vt03_pcm_t *ch);
|
||||
s8 vt3x_pcm(apu_vt_t::vt3x_pcm_t *ch);
|
||||
void reset_vt03_pcm(apu_vt_t::vt03_pcm_t *ch);
|
||||
void start_vt3x_pcm(apu_vt_t::vt3x_pcm_t *ch);
|
||||
private:
|
||||
devcb_read8 m_rom_read_cb;
|
||||
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(NES_VT_APU, nesapu_vt_device)
|
||||
DECLARE_DEVICE_TYPE(NES_VT_APU_SLAVE, nesapu_vt_slave_device)
|
||||
|
||||
#endif // MAME_SOUND_NES_VT_APU_H
|
||||
@ -74,7 +74,6 @@
|
||||
#include "machine/bankdev.h"
|
||||
#include "video/ppu2c0x_vt.h"
|
||||
#include "machine/m6502_vtscr.h"
|
||||
#include "sound/nes_vt_apu.h"
|
||||
#include "screen.h"
|
||||
#include "speaker.h"
|
||||
|
||||
@ -127,7 +126,6 @@ private:
|
||||
/* APU handling */
|
||||
DECLARE_WRITE_LINE_MEMBER(apu_irq);
|
||||
DECLARE_READ8_MEMBER(apu_read_mem);
|
||||
DECLARE_READ8_MEMBER(apu_read_rom);
|
||||
DECLARE_READ8_MEMBER(psg1_4014_r);
|
||||
DECLARE_READ8_MEMBER(psg1_4015_r);
|
||||
DECLARE_WRITE8_MEMBER(psg1_4015_w);
|
||||
@ -235,7 +233,7 @@ private:
|
||||
|
||||
required_device<screen_device> m_screen;
|
||||
required_device<ppu_vt03_device> m_ppu;
|
||||
required_device<nesapu_vt_device> m_apu;
|
||||
required_device<nesapu_device> m_apu;
|
||||
required_device<address_map_bank_device> m_prg;
|
||||
required_memory_bank m_prgbank0;
|
||||
required_memory_bank m_prgbank1;
|
||||
@ -1166,7 +1164,7 @@ void nes_vt_state::nes_vt_map(address_map &map)
|
||||
map(0x0000, 0x07ff).ram();
|
||||
map(0x2000, 0x3fff).mask(0x001F).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write)); /* PPU registers */
|
||||
|
||||
map(0x4000, 0x4036).rw(m_apu, FUNC(nesapu_vt_device::read), FUNC(nesapu_vt_device::write));
|
||||
map(0x4000, 0x4013).rw(m_apu, FUNC(nesapu_device::read), FUNC(nesapu_device::write));
|
||||
map(0x4014, 0x4014).r(FUNC(nes_vt_state::psg1_4014_r)).w(FUNC(nes_vt_state::nes_vh_sprite_dma_w));
|
||||
map(0x4015, 0x4015).rw(FUNC(nes_vt_state::psg1_4015_r), FUNC(nes_vt_state::psg1_4015_w)); /* PSG status / first control register */
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_vt_state::nes_in0_r), FUNC(nes_vt_state::nes_in0_w));
|
||||
@ -1234,7 +1232,7 @@ void nes_vt_state::nes_vt_hh_map(address_map &map)
|
||||
map(0x0000, 0x1fff).mask(0x0fff).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write)); /* PPU registers */
|
||||
|
||||
map(0x4000, 0x4036).rw(m_apu, FUNC(nesapu_vt_device::read), FUNC(nesapu_vt_device::write));
|
||||
map(0x4000, 0x4013).rw(m_apu, FUNC(nesapu_device::read), FUNC(nesapu_device::write));
|
||||
map(0x4015, 0x4015).rw(FUNC(nes_vt_state::psg1_4015_r), FUNC(nes_vt_state::psg1_4015_w)); /* PSG status / first control register */
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_vt_state::nes_in0_r), FUNC(nes_vt_state::nes_in0_w));
|
||||
map(0x4017, 0x4017).r(FUNC(nes_vt_state::nes_in1_r)).w(FUNC(nes_vt_state::psg1_4017_w));
|
||||
@ -1258,7 +1256,7 @@ void nes_vt_state::nes_vt_dg_map(address_map &map)
|
||||
map(0x0000, 0x1fff).ram();
|
||||
map(0x2000, 0x3fff).rw(m_ppu, FUNC(ppu2c0x_device::read), FUNC(ppu2c0x_device::write)); /* PPU registers */
|
||||
|
||||
map(0x4000, 0x4036).rw(m_apu, FUNC(nesapu_vt_device::read), FUNC(nesapu_vt_device::write));
|
||||
map(0x4000, 0x4013).rw(m_apu, FUNC(nesapu_device::read), FUNC(nesapu_device::write));
|
||||
map(0x4015, 0x4015).rw(FUNC(nes_vt_state::psg1_4015_r), FUNC(nes_vt_state::psg1_4015_w)); /* PSG status / first control register */
|
||||
map(0x4016, 0x4016).rw(FUNC(nes_vt_state::nes_in0_r), FUNC(nes_vt_state::nes_in0_w));
|
||||
map(0x4017, 0x4017).r(FUNC(nes_vt_state::nes_in1_r)).w(FUNC(nes_vt_state::psg1_4017_w));
|
||||
@ -1307,17 +1305,12 @@ void nes_vt_state::prg_map(address_map &map)
|
||||
|
||||
WRITE_LINE_MEMBER(nes_vt_state::apu_irq)
|
||||
{
|
||||
m_maincpu->set_input_line(N2A03_APU_IRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
// set_input_line(N2A03_APU_IRQ_LINE, state ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
READ8_MEMBER(nes_vt_state::apu_read_mem)
|
||||
{
|
||||
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
|
||||
}
|
||||
|
||||
READ8_MEMBER(nes_vt_state::apu_read_rom)
|
||||
{
|
||||
return m_prgrom[offset & (m_romsize - 1)];
|
||||
return 0x00;//mintf->program->read_byte(offset);
|
||||
}
|
||||
|
||||
/* not strictly needed, but helps us see where things are in ROM to aid with figuring out banking schemes*/
|
||||
@ -1390,10 +1383,9 @@ void nes_vt_state::nes_vt_base(machine_config &config)
|
||||
than just using 2 APUs as registers in the 2nd one affect the PCM channel mode but the
|
||||
DMA control still comes from the 1st, but in the new mode, sound always outputs via the
|
||||
2nd. Probably need to split the APU into interface and sound gen logic. */
|
||||
NES_VT_APU(config, m_apu, NTSC_APU_CLOCK);
|
||||
NES_APU(config, m_apu, NTSC_APU_CLOCK);
|
||||
m_apu->irq().set(FUNC(nes_vt_state::apu_irq));
|
||||
m_apu->mem_read().set(FUNC(nes_vt_state::apu_read_mem));
|
||||
m_apu->rom_read().set(FUNC(nes_vt_state::apu_read_rom));
|
||||
m_apu->add_route(ALL_OUTPUTS, "mono", 0.50);
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user