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This commit is contained in:
Vas Crabb 2018-07-08 18:08:10 +10:00
parent f0773a505b
commit e56b1e0cda
12 changed files with 171 additions and 222 deletions
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36
src/devices/bus/intellec4/intellec4.h
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@ -114,34 +114,6 @@ to implement the card in both systems.
#pragma once
#define MCFG_INTELLEC4_UNIV_BUS_ROM_SPACE(tag, space) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_rom_space(tag, space);
#define MCFG_INTELLEC4_UNIV_BUS_ROM_PORTS_SPACE(tag, space) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_rom_ports_space(tag, space);
#define MCFG_INTELLEC4_UNIV_BUS_MEMORY_SPACE(tag, space) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_memory_space(tag, space);
#define MCFG_INTELLEC4_UNIV_BUS_STATUS_SPACE(tag, space) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_status_space(tag, space);
#define MCFG_INTELLEC4_UNIV_BUS_RAM_PORTS_SPACE(tag, space) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_ram_ports_space(tag, space);
#define MCFG_INTELLEC4_UNIV_BUS_TEST_CB(obj) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_test_out_cb(DEVCB_##obj);
#define MCFG_INTELLEC4_UNIV_BUS_STOP_CB(obj) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_stop_out_cb(DEVCB_##obj);
#define MCFG_INTELLEC4_UNIV_BUS_RESET_4002_CB(obj) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_reset_4002_out_cb(DEVCB_##obj);
#define MCFG_INTELLEC4_UNIV_BUS_USER_RESET_CB(obj) \
downcast<bus::intellec4::univ_bus_device &>(*device).set_user_reset_out_cb(DEVCB_##obj);
namespace bus { namespace intellec4 {
class univ_slot_device;
@ -188,10 +160,10 @@ public:
template <typename T> void set_ram_ports_space(T &&tag, int space) { m_ram_ports_device.set_tag(std::forward<T>(tag)); m_ram_ports_space = space; }
// callback configuration
template <typename Obj> devcb_base &set_stop_out_cb(Obj &&cb) { return m_stop_out_cb.set_callback(std::forward<Obj>(cb)); }
template <typename Obj> devcb_base &set_test_out_cb(Obj &&cb) { return m_test_out_cb.set_callback(std::forward<Obj>(cb)); }
template <typename Obj> devcb_base &set_reset_4002_out_cb(Obj &&cb) { return m_reset_4002_out_cb.set_callback(std::forward<Obj>(cb)); }
template <typename Obj> devcb_base &set_user_reset_out_cb(Obj &&cb) { return m_user_reset_out_cb.set_callback(std::forward<Obj>(cb)); }
auto stop_out_cb() { return m_stop_out_cb.bind(); }
auto test_out_cb() { return m_test_out_cb.bind(); }
auto reset_4002_out_cb() { return m_reset_4002_out_cb.bind(); }
auto user_reset_out_cb() { return m_user_reset_out_cb.bind(); }
univ_bus_device(machine_config const &mconfig, char const *tag, device_t *owner, uint32_t clock);

1
src/devices/machine/bankdev.h
View File

@ -30,6 +30,7 @@ public:
address_map_bank_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
// configuration helpers
template <typename... T> void set_map(T &&... args) { set_addrmap(0, std::forward<T>(args)...); }
void set_endianness(endianness_t endianness) { m_endianness = endianness; }
void set_data_width(uint8_t data_width) { m_data_width = data_width; }
void set_addr_width(uint8_t addr_width) { m_addr_width = addr_width; }

61
src/mame/drivers/intellec4.cpp
View File

@ -817,35 +817,36 @@ DEVICE_INPUT_DEFAULTS_START(tty)
DEVICE_INPUT_DEFAULTS("FLOW_CONTROL", 0x0001, 0x0000)
DEVICE_INPUT_DEFAULTS_END
MACHINE_CONFIG_START(intellec4_state::intellec4)
MCFG_DEVICE_ADD(m_program_banks, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(intellec4_program_banks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
void intellec4_state::intellec4(machine_config &config)
{
ADDRESS_MAP_BANK(config, m_program_banks, 0);
m_program_banks->set_map(&intellec4_state::intellec4_program_banks);
m_program_banks->set_endianness(ENDIANNESS_LITTLE);
m_program_banks->set_data_width(8);
m_program_banks->set_addr_width(14);
m_program_banks->set_stride(0x1000);
MCFG_DEVICE_ADD(m_rom_port_banks, ADDRESS_MAP_BANK, 0)
MCFG_DEVICE_PROGRAM_MAP(intellec4_rom_port_banks)
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8)
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(14)
MCFG_ADDRESS_MAP_BANK_STRIDE(0x1000)
ADDRESS_MAP_BANK(config, m_rom_port_banks, 0);
m_rom_port_banks->set_map(&intellec4_state::intellec4_rom_port_banks);
m_rom_port_banks->set_endianness(ENDIANNESS_LITTLE);
m_rom_port_banks->set_data_width(8);
m_rom_port_banks->set_addr_width(14);
m_rom_port_banks->set_stride(0x1000);
MCFG_DEVICE_ADD(m_prom_programmer, INTEL_IMM6_76, 0)
INTEL_IMM6_76(config, m_prom_programmer, 0);
MCFG_DEVICE_ADD(m_tty, RS232_PORT, default_rs232_devices, "terminal")
MCFG_SLOT_OPTION_DEVICE_INPUT_DEFAULTS("terminal", tty)
MCFG_SLOT_OPTION_DEVICE_INPUT_DEFAULTS("null_modem", tty)
RS232_PORT(config, m_tty, default_rs232_devices, "terminal");
m_tty->set_option_device_input_defaults("terminal", DEVICE_INPUT_DEFAULTS_NAME(tty));
m_tty->set_option_device_input_defaults("null_modem", DEVICE_INPUT_DEFAULTS_NAME(tty));
MCFG_DEVICE_ADD(m_bus, INTELLEC4_UNIV_BUS, 518000. / 7)
MCFG_INTELLEC4_UNIV_BUS_ROM_SPACE(m_program_banks, AS_PROGRAM)
MCFG_INTELLEC4_UNIV_BUS_ROM_PORTS_SPACE(m_rom_port_banks, AS_PROGRAM)
MCFG_INTELLEC4_UNIV_BUS_MEMORY_SPACE(m_cpu, mcs40_cpu_device_base::AS_RAM_MEMORY)
MCFG_INTELLEC4_UNIV_BUS_STATUS_SPACE(m_cpu, mcs40_cpu_device_base::AS_RAM_STATUS)
MCFG_INTELLEC4_UNIV_BUS_RAM_PORTS_SPACE(m_cpu, mcs40_cpu_device_base::AS_RAM_PORTS)
MCFG_INTELLEC4_UNIV_BUS_RESET_4002_CB(WRITELINE(*this, intellec4_state, bus_reset_4002))
MCFG_INTELLEC4_UNIV_BUS_USER_RESET_CB(WRITELINE(*this, intellec4_state, bus_user_reset))
INTELLEC4_UNIV_BUS(config, m_bus, 518000. / 7);
m_bus->set_rom_space(m_program_banks, AS_PROGRAM);
m_bus->set_rom_ports_space(m_rom_port_banks, AS_PROGRAM);
m_bus->set_memory_space(m_cpu, mcs40_cpu_device_base::AS_RAM_MEMORY);
m_bus->set_status_space(m_cpu, mcs40_cpu_device_base::AS_RAM_STATUS);
m_bus->set_ram_ports_space(m_cpu, mcs40_cpu_device_base::AS_RAM_PORTS);
m_bus->reset_4002_out_cb().set(FUNC(intellec4_state::bus_reset_4002));
m_bus->user_reset_out_cb().set(FUNC(intellec4_state::bus_user_reset));
INTELLEC4_UNIV_SLOT(config, "j7", 5.185_MHz_XTAL / 7, m_bus, intellec4_univ_cards, "imm4_90");
INTELLEC4_UNIV_SLOT(config, "j8", 5.185_MHz_XTAL / 7, m_bus, intellec4_univ_cards, "imm6_26");
INTELLEC4_UNIV_SLOT(config, "j9", 5.185_MHz_XTAL / 7, m_bus, intellec4_univ_cards, nullptr);
@ -859,7 +860,7 @@ MACHINE_CONFIG_START(intellec4_state::intellec4)
INTELLEC4_UNIV_SLOT(config, "j17", 5.185_MHz_XTAL / 7, m_bus, intellec4_univ_cards, nullptr);
INTELLEC4_UNIV_SLOT(config, "j18", 5.185_MHz_XTAL / 7, m_bus, intellec4_univ_cards, nullptr);
INTELLEC4_UNIV_SLOT(config, "j19", 5.185_MHz_XTAL / 7, m_bus, intellec4_univ_cards, nullptr);
MACHINE_CONFIG_END
}
/*----------------------------------
@ -1134,8 +1135,7 @@ MACHINE_CONFIG_START(mod4_state::mod4)
MCFG_I4004_BUS_CYCLE_CB(BUSCYCLE(mod4_state, bus_cycle));
MCFG_I4004_SYNC_CB(WRITELINE(m_bus, bus::intellec4::univ_bus_device, sync_in))
MCFG_DEVICE_MODIFY("bus")
MCFG_INTELLEC4_UNIV_BUS_TEST_CB(WRITELINE(*this, mod4_state, bus_test))
m_bus->test_out_cb().set(FUNC(mod4_state::bus_test));
MCFG_DEFAULT_LAYOUT(layout_intlc44)
MACHINE_CONFIG_END
@ -1361,9 +1361,8 @@ MACHINE_CONFIG_START(mod40_state::mod40)
MCFG_I4040_SYNC_CB(WRITELINE(m_bus, bus::intellec4::univ_bus_device, sync_in))
MCFG_I4040_STP_ACK_CB(WRITELINE(*this, mod40_state, stp_ack))
MCFG_DEVICE_MODIFY("bus")
MCFG_INTELLEC4_UNIV_BUS_STOP_CB(WRITELINE(*this, mod40_state, bus_stop))
MCFG_INTELLEC4_UNIV_BUS_TEST_CB(WRITELINE(*this, mod40_state, bus_test))
m_bus->stop_out_cb().set(FUNC(mod40_state::bus_stop));
m_bus->test_out_cb().set(FUNC(mod40_state::bus_test));
MCFG_DEFAULT_LAYOUT(layout_intlc440)
MACHINE_CONFIG_END

26
src/mame/drivers/microtan.cpp
View File

@ -213,6 +213,8 @@ MACHINE_CONFIG_START(microtan_state::microtan)
MCFG_DEVICE_PROGRAM_MAP(main_map)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", microtan_state, interrupt)
// The 6502 IRQ line is active low and probably driven by open collector outputs (guess).
INPUT_MERGER_ANY_HIGH(config, m_irq_line).output_handler().set_inputline(m_maincpu, 0);
/* video hardware - include overscan */
MCFG_SCREEN_ADD("screen", RASTER)
@ -247,20 +249,20 @@ MACHINE_CONFIG_START(microtan_state::microtan)
MCFG_MOS6551_XTAL(XTAL(1'843'200))
/* via */
MCFG_DEVICE_ADD(m_via6522[0], VIA6522, XTAL(6'000'000) / 8)
MCFG_VIA6522_READPA_HANDLER(READ8(*this, microtan_state, via_0_in_a))
MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(*this, microtan_state, via_0_out_a))
MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(*this, microtan_state, via_0_out_b))
MCFG_VIA6522_CA2_HANDLER(WRITELINE(*this, microtan_state, via_0_out_ca2))
MCFG_VIA6522_CB2_HANDLER(WRITELINE(*this, microtan_state, via_0_out_cb2))
MCFG_VIA6522_IRQ_HANDLER(WRITELINE(*this, microtan_state, via_0_irq))
VIA6522(config, m_via6522[0], 6_MHz_XTAL / 8);
m_via6522[0]->readpa_handler().set(FUNC(microtan_state::via_0_in_a));
m_via6522[0]->writepa_handler().set(FUNC(microtan_state::via_0_out_a));
m_via6522[0]->writepb_handler().set(FUNC(microtan_state::via_0_out_b));
m_via6522[0]->ca2_handler().set(FUNC(microtan_state::via_0_out_ca2));
m_via6522[0]->cb2_handler().set(FUNC(microtan_state::via_0_out_cb2));
m_via6522[0]->irq_handler().set(m_irq_line, FUNC(input_merger_device::in_w<IRQ_VIA_0>));
MCFG_DEVICE_ADD(m_via6522[1], VIA6522, XTAL(6'000'000) / 8)
MCFG_VIA6522_WRITEPA_HANDLER(WRITE8(*this, microtan_state, via_1_out_a))
MCFG_VIA6522_WRITEPB_HANDLER(WRITE8(*this, microtan_state, via_1_out_b))
MCFG_VIA6522_CA2_HANDLER(WRITELINE(*this, microtan_state, via_1_out_ca2))
MCFG_VIA6522_CB2_HANDLER(WRITELINE(*this, microtan_state, via_1_out_cb2))
MCFG_VIA6522_IRQ_HANDLER(WRITELINE(*this, microtan_state, via_1_irq))
m_via6522[1]->writepa_handler().set(FUNC(microtan_state::via_1_out_a));
m_via6522[1]->writepb_handler().set(FUNC(microtan_state::via_1_out_b));
m_via6522[1]->ca2_handler().set(FUNC(microtan_state::via_1_out_ca2));
m_via6522[1]->cb2_handler().set(FUNC(microtan_state::via_1_out_cb2));
m_via6522[1]->irq_handler().set(m_irq_line, FUNC(input_merger_device::in_w<IRQ_VIA_1>));
MACHINE_CONFIG_END
ROM_START( microtan )

18
src/mame/drivers/namcos2.cpp
View File

@ -1700,16 +1700,16 @@ via software as INT1
/* */
/*************************************************************/
MACHINE_CONFIG_START(namcos2_state::configure_c148_standard)
MCFG_NAMCO_C148_ADD("master_intc","maincpu",true)
MCFG_NAMCO_C148_LINK("slave_intc")
MCFG_NAMCO_C148_EXT1_CB(WRITE8(*this, namcos2_state, sound_reset_w))
MCFG_NAMCO_C148_EXT2_CB(WRITE8(*this, namcos2_state, system_reset_w))
void namcos2_state::configure_c148_standard(machine_config &config)
{
NAMCO_C148(config, m_master_intc, 0, m_maincpu, true);
m_master_intc->link_c148_device(m_slave_intc);
m_master_intc->out_ext1_callback().set(FUNC(namcos2_state::sound_reset_w));
m_master_intc->out_ext2_callback().set(FUNC(namcos2_state::system_reset_w));
MCFG_NAMCO_C148_ADD("slave_intc","slave",false)
MCFG_NAMCO_C148_LINK("master_intc")
MACHINE_CONFIG_END
NAMCO_C148(config, m_slave_intc, 0, m_slave, false);
m_slave_intc->link_c148_device(m_master_intc);
}
// TODO: temp
TIMER_DEVICE_CALLBACK_MEMBER(namcos2_state::screen_scanline)

20
src/mame/drivers/namcos21.cpp
View File

@ -1901,16 +1901,16 @@ TIMER_DEVICE_CALLBACK_MEMBER(namcos21_state::screen_scanline)
}
}
MACHINE_CONFIG_START(namcos21_state::configure_c148_standard)
MCFG_NAMCO_C148_ADD("master_intc","maincpu",true)
MCFG_NAMCO_C148_LINK("slave_intc")
MCFG_NAMCO_C148_EXT1_CB(WRITE8(*this, namcos21_state, sound_reset_w))
MCFG_NAMCO_C148_EXT2_CB(WRITE8(*this, namcos21_state, system_reset_w))
void namcos21_state::configure_c148_standard(machine_config &config)
{
NAMCO_C148(config, m_master_intc, 0, m_maincpu, true);
m_master_intc->link_c148_device(m_slave_intc);
m_master_intc->out_ext1_callback().set(FUNC(namcos21_state::sound_reset_w));
m_master_intc->out_ext2_callback().set(FUNC(namcos21_state::system_reset_w));
MCFG_NAMCO_C148_ADD("slave_intc","slave",false)
MCFG_NAMCO_C148_LINK("master_intc")
MACHINE_CONFIG_END
NAMCO_C148(config, m_slave_intc, 0, m_slave, false);
m_slave_intc->link_c148_device(m_master_intc);
}
MACHINE_CONFIG_START(namcos21_state::namcos21)
MCFG_DEVICE_ADD("maincpu", M68000,12288000) /* Master */
@ -2071,7 +2071,7 @@ MACHINE_CONFIG_START(namcos21_state::winrun)
MCFG_DEVICE_PROGRAM_MAP(winrun_gpu_map)
configure_c148_standard(config);
MCFG_NAMCO_C148_ADD("gpu_intc","gpu",false)
NAMCO_C148(config, m_gpu_intc, 0, "gpu", false);
MCFG_NAMCO_C139_ADD("sci")
MCFG_QUANTUM_TIME(attotime::from_hz(6000)) /* 100 CPU slices per frame */

24
src/mame/includes/microtan.h
View File

@ -17,8 +17,11 @@
#ifndef MAME_INCLUDES_MICROTAN_H
#define MAME_INCLUDES_MICROTAN_H
#pragma once
#include "imagedev/snapquik.h"
#include "machine/6522via.h"
#include "machine/input_merger.h"
#include "sound/ay8910.h"
#include "imagedev/cassette.h"
@ -29,6 +32,7 @@ public:
driver_device(mconfig, type, tag),
m_videoram(*this, "videoram"),
m_maincpu(*this, "maincpu"),
m_irq_line(*this, "irq_line"),
m_cassette(*this, "cassette"),
m_via6522(*this, "via6522%u", 0),
m_ay8910(*this, "ay8910%u", 0),
@ -41,20 +45,23 @@ public:
void init_microtan();
protected:
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
private:
enum
{
TIMER_READ_CASSETTE,
TIMER_PULSE_NMI
};
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
private:
enum { IRQ_VIA_0, IRQ_VIA_1, IRQ_KBD };
required_shared_ptr<uint8_t> m_videoram;
required_device<cpu_device> m_maincpu;
required_device<input_merger_device> m_irq_line;
required_device<cassette_image_device> m_cassette;
required_device_array<via6522_device, 2> m_via6522;
required_device_array<ay8910_device, 2> m_ay8910;
@ -67,8 +74,6 @@ private:
uint8_t m_keyboard_ascii;
emu_timer *m_read_cassette_timer;
emu_timer *m_pulse_nmi_timer;
int m_via_irq_line[2];
int m_kbd_irq_line;
uint8_t m_keyrows[10];
int m_lastrow;
int m_mask;
@ -96,10 +101,7 @@ private:
DECLARE_WRITE8_MEMBER(via_1_out_b);
DECLARE_WRITE_LINE_MEMBER(via_1_out_ca2);
DECLARE_WRITE_LINE_MEMBER(via_1_out_cb2);
DECLARE_WRITE_LINE_MEMBER(via_0_irq);
DECLARE_WRITE_LINE_MEMBER(via_1_irq);
uint8_t read_dsw();
void set_irq_line();
void store_key(int key);
image_verify_result verify_snapshot(uint8_t *data, int size);
image_init_result parse_intel_hex(uint8_t *snapshot_buff, char *src);

49
src/mame/includes/namcos2.h
View File

@ -7,6 +7,10 @@
Common functions & declarations for the Namco System 2 driver
***************************************************************************/
#ifndef MAME_INCLUDES_NAMCOS2_H
#define MAME_INCLUDES_NAMCOS2_H
#pragma once
#include "machine/namco_c139.h"
#include "machine/namco_c148.h"
@ -101,27 +105,28 @@ class namcos2_shared_state : public driver_device
{
public:
namcos2_shared_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag),
m_dspmaster(*this, "dspmaster"),
m_dspslave(*this, "dspslave"),
m_gametype(0),
m_c68(*this, "c68"),
m_master_intc(*this, "master_intc"),
m_slave_intc(*this, "slave_intc"),
m_sci(*this, "sci"),
m_gpu(*this, "gpu"),
m_c169_roz_videoram(*this, "rozvideoram", 0),
m_c169_roz_gfxbank(0),
m_c169_roz_mask(nullptr),
m_c355_obj_gfxbank(0),
m_c355_obj_palxor(0),
m_maincpu(*this, "maincpu"),
m_audiocpu(*this, "audiocpu"),
m_slave(*this, "slave"),
m_mcu(*this, "mcu"),
m_gfxdecode(*this, "gfxdecode"),
m_screen(*this, "screen"),
m_palette(*this, "palette") { }
: driver_device(mconfig, type, tag)
, m_dspmaster(*this, "dspmaster")
, m_dspslave(*this, "dspslave")
, m_gametype(0)
, m_c68(*this, "c68")
, m_master_intc(*this, "master_intc")
, m_slave_intc(*this, "slave_intc")
, m_sci(*this, "sci")
, m_gpu(*this, "gpu")
, m_c169_roz_videoram(*this, "rozvideoram", 0)
, m_c169_roz_gfxbank(0)
, m_c169_roz_mask(nullptr)
, m_c355_obj_gfxbank(0)
, m_c355_obj_palxor(0)
, m_maincpu(*this, "maincpu")
, m_audiocpu(*this, "audiocpu")
, m_slave(*this, "slave")
, m_mcu(*this, "mcu")
, m_gfxdecode(*this, "gfxdecode")
, m_screen(*this, "screen")
, m_palette(*this, "palette")
{ }
optional_device<cpu_device> m_dspmaster;
optional_device<cpu_device> m_dspslave;
@ -468,3 +473,5 @@ extern void (*namcos2_kickstart)(running_machine &machine, int internal);
/**************************************************************/
/* Sound CPU support handlers - 6809 */
/**************************************************************/
#endif // MAME_INCLUDES_NAMCOS2_H

12
src/mame/includes/namcos21.h
View File

@ -3,6 +3,10 @@
/**
* @file namcos21.h
*/
#ifndef MAME_INCLUDES_NAMCOS21_H
#define MAME_INCLUDES_NAMCOS21_H
#pragma once
#include "namcos2.h"
#include "machine/namcoio_gearbox.h"
@ -45,8 +49,8 @@ struct edge
class namcos21_state : public namcos2_shared_state
{
public:
namcos21_state(const machine_config &mconfig, device_type type, const char *tag)
: namcos2_shared_state(mconfig, type, tag),
namcos21_state(const machine_config &mconfig, device_type type, const char *tag) :
namcos2_shared_state(mconfig, type, tag),
m_master_dsp_code(*this,"master_dsp_code"),
m_winrun_dspbios(*this,"winrun_dspbios"),
m_winrun_polydata(*this,"winrun_polydata"),
@ -57,7 +61,7 @@ public:
m_dsp(*this, "dsp"),
m_io_gearbox(*this, "gearbox"),
m_gpu_intc(*this, "gpu_intc")
{ }
{ }
void configure_c148_standard(machine_config &config);
void driveyes(machine_config &config);
@ -221,3 +225,5 @@ private:
void winrun_master_map(address_map &map);
void winrun_slave_map(address_map &map);
};
#endif // MAME_INCLUDES_NAMCOS21_H

82
src/mame/machine/microtan.cpp
View File

@ -24,14 +24,8 @@
//#include "imagedev/snapquik.h"
#ifndef VERBOSE
#define VERBOSE 0
#endif
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
//#define VERBOSE 1
#include "logmacro.h"
static const char keyboard[8][9][8] = {
@ -138,51 +132,36 @@ uint8_t microtan_state::read_dsw()
}
}
void microtan_state::set_irq_line()
{
/* The 6502 IRQ line is active low and probably driven
by open collector outputs (guess). Since MAME uses
a non-0 value for ASSERT_LINE we OR the signals here */
m_maincpu->set_input_line(0, m_via_irq_line[0] | m_via_irq_line[1] | m_kbd_irq_line);
}
/**************************************************************
* VIA callback functions for VIA #0
**************************************************************/
READ8_MEMBER(microtan_state::via_0_in_a)
{
int data = ioport("JOY")->read();
LOG(("via_0_in_a %02X\n", data));
LOG("via_0_in_a %02X\n", data);
return data;
}
WRITE8_MEMBER(microtan_state::via_0_out_a)
{
LOG(("via_0_out_a %02X\n", data));
LOG("via_0_out_a %02X\n", data);
}
WRITE8_MEMBER(microtan_state::via_0_out_b)
{
LOG(("via_0_out_b %02X\n", data));
LOG("via_0_out_b %02X\n", data);
/* bit #7 is the cassette output signal */
m_cassette->output(data & 0x80 ? +1.0 : -1.0);
}
WRITE_LINE_MEMBER(microtan_state::via_0_out_ca2)
{
LOG(("via_0_out_ca2 %d\n", state));
LOG("via_0_out_ca2 %d\n", state);
}
WRITE_LINE_MEMBER(microtan_state::via_0_out_cb2)
{
LOG(("via_0_out_cb2 %d\n", state));
}
WRITE_LINE_MEMBER(microtan_state::via_0_irq)
{
LOG(("via_0_irq %d\n", state));
m_via_irq_line[0] = state;
set_irq_line();
LOG("via_0_out_cb2 %d\n", state);
}
/**************************************************************
@ -191,29 +170,22 @@ WRITE_LINE_MEMBER(microtan_state::via_0_irq)
WRITE8_MEMBER(microtan_state::via_1_out_a)
{
LOG(("via_1_out_a %02X\n", data));
LOG("via_1_out_a %02X\n", data);
}
WRITE8_MEMBER(microtan_state::via_1_out_b)
{
LOG(("via_1_out_b %02X\n", data));
LOG("via_1_out_b %02X\n", data);
}
WRITE_LINE_MEMBER(microtan_state::via_1_out_ca2)
{
LOG(("via_1_out_ca2 %d\n", state));
LOG("via_1_out_ca2 %d\n", state);
}
WRITE_LINE_MEMBER(microtan_state::via_1_out_cb2)
{
LOG(("via_1_out_cb2 %d\n", state));
}
WRITE_LINE_MEMBER(microtan_state::via_1_irq)
{
LOG(("via_1_irq %d\n", state));
m_via_irq_line[1] = state;
set_irq_line();
LOG("via_1_out_cb2 %d\n", state);
}
void microtan_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
@ -236,7 +208,7 @@ TIMER_CALLBACK_MEMBER(microtan_state::read_cassette)
{
double level = m_cassette->input();
LOG(("read_cassette: %g\n", level));
LOG("read_cassette: %g\n", level);
if (level < -0.07)
m_via6522[0]->write_cb2(0);
else if (level > +0.07)
@ -246,13 +218,13 @@ TIMER_CALLBACK_MEMBER(microtan_state::read_cassette)
READ8_MEMBER(microtan_state::sound_r)
{
int data = 0xff;
LOG(("sound_r: -> %02x\n", data));
LOG("sound_r: -> %02x\n", data);
return data;
}
WRITE8_MEMBER(microtan_state::sound_w)
{
LOG(("sound_w: <- %02x\n", data));
LOG("sound_w: <- %02x\n", data);
}
@ -263,17 +235,17 @@ READ8_MEMBER(microtan_state::bffx_r)
{
case 0: /* BFF0: read enables chunky graphics */
m_chunky_graphics = 1;
LOG(("bff0_r: -> %02x (chunky graphics on)\n", data));
LOG("bff0_r: -> %02x (chunky graphics on)\n", data);
break;
case 1: /* BFF1: read undefined (?) */
LOG(("bff1_r: -> %02x\n", data));
LOG("bff1_r: -> %02x\n", data);
break;
case 2: /* BFF2: read undefined (?) */
LOG(("bff2_r: -> %02x\n", data));
LOG("bff2_r: -> %02x\n", data);
break;
default: /* BFF3: read keyboard ASCII value */
data = m_keyboard_ascii;
LOG(("bff3_r: -> %02x (keyboard ASCII)\n", data));
LOG("bff3_r: -> %02x (keyboard ASCII)\n", data);
}
return data;
}
@ -291,31 +263,29 @@ WRITE8_MEMBER(microtan_state::bffx_w)
{
case 0: /* BFF0: write reset keyboard interrupt flag */
/* This removes bit 7 from the ASCII value of the last key pressed. */
LOG(("bff0_w: %d <- %02x (keyboard IRQ clear )\n", offset, data));
LOG("bff0_w: %d <- %02x (keyboard IRQ clear )\n", offset, data);
m_keyboard_ascii &= ~0x80;
m_kbd_irq_line = CLEAR_LINE;
set_irq_line();
m_irq_line->in_w<IRQ_KBD>(0);
break;
case 1: /* BFF1: write delayed NMI */
LOG(("bff1_w: %d <- %02x (delayed NMI)\n", offset, data));
LOG("bff1_w: %d <- %02x (delayed NMI)\n", offset, data);
m_pulse_nmi_timer->adjust(m_maincpu->cycles_to_attotime(8));
break;
case 2: /* BFF2: write keypad column write (what is this meant for?) */
LOG(("bff2_w: %d <- %02x (keypad column)\n", offset, data));
LOG("bff2_w: %d <- %02x (keypad column)\n", offset, data);
m_keypad_column = data;
break;
default: /* BFF3: write disable chunky graphics */
LOG(("bff3_w: %d <- %02x (chunky graphics off)\n", offset, data));
LOG("bff3_w: %d <- %02x (chunky graphics off)\n", offset, data);
m_chunky_graphics = 0;
}
}
void microtan_state::store_key(int key)
{
LOG(("microtan: store key '%c'\n", key));
LOG("microtan: store key '%c'\n", key);
m_keyboard_ascii = key | 0x80;
m_kbd_irq_line = ASSERT_LINE;
set_irq_line();
m_irq_line->in_w<IRQ_KBD>(1);
}
INTERRUPT_GEN_MEMBER(microtan_state::interrupt)
@ -509,8 +479,6 @@ void microtan_state::machine_start()
save_item(NAME(m_chunky_graphics));
save_item(NAME(m_keypad_column));
save_item(NAME(m_keyboard_ascii));
save_item(NAME(m_via_irq_line));
save_item(NAME(m_kbd_irq_line));
save_item(NAME(m_keyrows));
save_item(NAME(m_lastrow));
save_item(NAME(m_mask));

15
src/mame/machine/namco_c148.cpp
View File

@ -65,8 +65,8 @@ DEFINE_DEVICE_TYPE(NAMCO_C148, namco_c148_device, "namco_c148", "Namco C148 Inte
// namco_c148_device - constructor
//-------------------------------------------------
namco_c148_device::namco_c148_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: device_t(mconfig, NAMCO_C148, tag, owner, clock),
namco_c148_device::namco_c148_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, NAMCO_C148, tag, owner, clock),
m_out_ext1_cb(*this),
m_out_ext2_cb(*this),
m_hostcpu(*this, finder_base::DUMMY_TAG),
@ -98,6 +98,17 @@ void namco_c148_device::map(address_map &map)
//-------------------------------------------------
// device_validity_check - device-specific checks
//-------------------------------------------------
void namco_c148_device::device_validity_check(validity_checker &valid) const
{
if ((m_linked_c148.finder_tag() != finder_base::DUMMY_TAG) && !m_linked_c148)
osd_printf_error("Linked C148 configured but not found.\n");
}
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------

49
src/mame/machine/namco_c148.h
View File

@ -11,26 +11,6 @@
#pragma once
//**************************************************************************
// INTERFACE CONFIGURATION MACROS
//**************************************************************************
#define MCFG_NAMCO_C148_ADD(_tag, _cputag, _cpumaster) \
MCFG_DEVICE_ADD(_tag, NAMCO_C148, 0) \
downcast<namco_c148_device &>(*device).configure_device(_cputag, _cpumaster);
#define MCFG_NAMCO_C148_LINK(_tag) \
downcast<namco_c148_device &>(*device).link_c148_device(_tag);
#define MCFG_NAMCO_C148_EXT1_CB(_cb) \
downcast<namco_c148_device &>(*device).set_out_ext1_callback(DEVCB_##_cb);
#define MCFG_NAMCO_C148_EXT2_CB(_cb) \
downcast<namco_c148_device &>(*device).set_out_ext2_callback(DEVCB_##_cb);
//**************************************************************************
// TYPE DEFINITIONS
//**************************************************************************
@ -41,23 +21,26 @@ class namco_c148_device : public device_t
{
public:
// construction/destruction
template <typename T>
namco_c148_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock, T &&hostcpu, bool is_master)
: namco_c148_device(mconfig, tag, owner, clock)
{
set_hostcpu(std::forward<T>(hostcpu), is_master);
}
namco_c148_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
void map(address_map &map);
template <class T> void configure_device(T &&tag, bool is_master)
template <typename T> void set_hostcpu(T &&tag, bool is_master)
{
m_hostcpu.set_tag(std::forward<T>(tag));
m_hostcpu_master = is_master;
}
template <class T> void link_c148_device(T &&tag) { m_linked_c148.set_tag(std::forward<T>(tag)); }
template <typename T> void link_c148_device(T &&tag) { m_linked_c148.set_tag(std::forward<T>(tag)); }
template <class Object> devcb_base &set_out_ext1_callback(Object &&cb) { return m_out_ext1_cb.set_callback(std::forward<Object>(cb)); }
template <class Object> devcb_base &set_out_ext2_callback(Object &&cb) { return m_out_ext2_cb.set_callback(std::forward<Object>(cb)); }
devcb_write8 m_out_ext1_cb;
devcb_write8 m_out_ext2_cb;
auto out_ext1_callback() { return m_out_ext1_cb.bind(); }
auto out_ext2_callback() { return m_out_ext2_cb.bind(); }
DECLARE_READ8_MEMBER( vblank_irq_level_r );
DECLARE_WRITE8_MEMBER( vblank_irq_level_w );
@ -103,9 +86,14 @@ public:
protected:
void cpu_irq_trigger();
// device-level overrides
virtual void device_validity_check(validity_checker &valid) const override;
virtual void device_start() override;
virtual void device_reset() override;
private:
devcb_write8 m_out_ext1_cb;
devcb_write8 m_out_ext2_cb;
required_device<cpu_device> m_hostcpu; // reference to the host cpu
optional_device<namco_c148_device> m_linked_c148; // reference to linked master/slave c148
bool m_hostcpu_master; // define if host cpu is master
@ -128,11 +116,4 @@ private:
DECLARE_DEVICE_TYPE(NAMCO_C148, namco_c148_device)
//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************
#endif // MAME_MACHINE_NAMCO_C148_H