mirror of
https://github.com/holub/mame
synced 2025-10-05 08:41:31 +03:00
ncr5390: Improve [P. Mackinlay]
* improved initiator transfer information logic * split transfer count/counter * added rudimentary 53c90a/53c94 support * reworked initiator transfer information state machine: should now support all scsi phases * improved handling of dma/non-dma commands * added an undocumented hack to make InterPro work * match updated 5390 device * inherit memory map * implemented interrupt status flag in status register for 53c90a, this is critical for InterPro
This commit is contained in:
Patrick Mackinlay
Olivier Galibert
parent
0ae673779b
commit
e57ceef927
@ -7,11 +7,12 @@
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#define DELAY_HACK
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DEFINE_DEVICE_TYPE(NCR5390, ncr5390_device, "ncr5390", "NCR 5390 SCSI")
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DEFINE_DEVICE_TYPE(NCR53C90A, ncr53c90a_device, "ncr53c90a", "NCR 53C90A SCSI")
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DEFINE_DEVICE_TYPE(NCR53C94, ncr53c94_device, "ncr53c94", "NCR 53C94 SCSI")
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DEVICE_ADDRESS_MAP_START(map, 8, ncr5390_device)
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AM_RANGE(0x0, 0x0) AM_READWRITE(tcount_lo_r, tcount_lo_w)
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AM_RANGE(0x1, 0x1) AM_READWRITE(tcount_hi_r, tcount_hi_w)
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AM_RANGE(0x0, 0x0) AM_READWRITE(tcounter_lo_r, tcount_lo_w)
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AM_RANGE(0x1, 0x1) AM_READWRITE(tcounter_hi_r, tcount_hi_w)
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AM_RANGE(0x2, 0x2) AM_READWRITE(fifo_r, fifo_w)
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AM_RANGE(0x3, 0x3) AM_READWRITE(command_r, command_w)
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AM_RANGE(0x4, 0x4) AM_READWRITE(status_r, bus_id_w)
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@ -19,22 +20,19 @@ DEVICE_ADDRESS_MAP_START(map, 8, ncr5390_device)
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AM_RANGE(0x6, 0x6) AM_READWRITE(seq_step_r, sync_period_w)
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AM_RANGE(0x7, 0x7) AM_READWRITE(fifo_flags_r, sync_offset_w)
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AM_RANGE(0x8, 0x8) AM_READWRITE(conf_r, conf_w)
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AM_RANGE(0xa, 0xa) AM_WRITE(test_w)
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AM_RANGE(0x9, 0x9) AM_WRITE(clock_w)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(map, 8, ncr53c94_device)
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AM_RANGE(0x0, 0x0) AM_READWRITE(tcount_lo_r, tcount_lo_w)
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AM_RANGE(0x1, 0x1) AM_READWRITE(tcount_hi_r, tcount_hi_w)
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AM_RANGE(0x2, 0x2) AM_READWRITE(fifo_r, fifo_w)
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AM_RANGE(0x3, 0x3) AM_READWRITE(command_r, command_w)
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AM_RANGE(0x4, 0x4) AM_READWRITE(status_r, bus_id_w)
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AM_RANGE(0x5, 0x5) AM_READWRITE(istatus_r, timeout_w)
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AM_RANGE(0x6, 0x6) AM_READWRITE(seq_step_r, sync_period_w)
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AM_RANGE(0x7, 0x7) AM_READWRITE(fifo_flags_r, sync_offset_w)
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AM_RANGE(0x8, 0x8) AM_READWRITE(conf_r, conf_w)
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AM_RANGE(0x9, 0x9) AM_WRITE(clock_w)
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AM_RANGE(0xa, 0xa) AM_WRITE(test_w)
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DEVICE_ADDRESS_MAP_START(map, 8, ncr53c90a_device)
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AM_INHERIT_FROM(ncr5390_device::map)
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AM_RANGE(0xb, 0xb) AM_READWRITE(conf2_r, conf2_w)
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ADDRESS_MAP_END
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DEVICE_ADDRESS_MAP_START(map, 8, ncr53c94_device)
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AM_INHERIT_FROM(ncr53c90a_device::map)
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AM_RANGE(0xc, 0xc) AM_READWRITE(conf3_r, conf3_w)
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AM_RANGE(0xf, 0xf) AM_WRITE(fifo_align_w)
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ADDRESS_MAP_END
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@ -42,21 +40,30 @@ ADDRESS_MAP_END
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ncr5390_device::ncr5390_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
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: nscsi_device(mconfig, type, tag, owner, clock)
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, tm(nullptr), config(0), status(0), istatus(0), clock_conv(0), sync_offset(0), sync_period(0), bus_id(0)
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, select_timeout(0), seq(0), tcount(0), mode(0), fifo_pos(0), command_pos(0), state(0), xfr_phase(0), command_length(0), dma_dir(0), irq(false), drq(false)
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, select_timeout(0), seq(0), tcount(0), tcounter(0), mode(0), fifo_pos(0), command_pos(0), state(0), xfr_phase(0), command_length(0), dma_dir(0), irq(false), drq(false), test_mode(false)
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, m_irq_handler(*this)
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, m_drq_handler(*this)
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{
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}
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ncr53c90a_device::ncr53c90a_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
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: ncr5390_device(mconfig, type, tag, owner, clock)
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, config2(0)
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{
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}
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ncr5390_device::ncr5390_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: ncr5390_device(mconfig, NCR5390, tag, owner, clock)
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{
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}
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ncr53c90a_device::ncr53c90a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: ncr53c90a_device(mconfig, NCR53C90A, tag, owner, clock)
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{
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}
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ncr53c94_device::ncr53c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: ncr5390_device(mconfig, NCR53C94, tag, owner, clock)
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, test_mode(false)
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, config2(0)
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: ncr53c90a_device(mconfig, NCR53C94, tag, owner, clock)
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, config3(0)
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{
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}
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@ -77,6 +84,7 @@ void ncr5390_device::device_start()
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save_item(NAME(seq));
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save_item(NAME(fifo));
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save_item(NAME(tcount));
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save_item(NAME(tcounter));
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save_item(NAME(mode));
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save_item(NAME(fifo_pos));
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save_item(NAME(command_pos));
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@ -86,11 +94,13 @@ void ncr5390_device::device_start()
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save_item(NAME(dma_dir));
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save_item(NAME(irq));
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save_item(NAME(drq));
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save_item(NAME(test_mode));
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m_irq_handler.resolve_safe();
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m_drq_handler.resolve_safe();
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tcount = 0;
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tcounter = 0;
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config = 0;
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status = 0;
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bus_id = 0;
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@ -121,6 +131,7 @@ void ncr5390_device::reset_soft()
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scsi_bus->ctrl_wait(scsi_refid, S_SEL|S_BSY|S_RST, S_ALL);
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status &= 0xef;
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drq = false;
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test_mode = false;
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m_drq_handler(drq);
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reset_disconnect();
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}
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@ -410,17 +421,26 @@ void ncr5390_device::step(bool timeout)
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case INIT_XFR:
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switch(xfr_phase) {
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case S_PHASE_DATA_OUT:
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dma_set(DMA_OUT);
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if(tcount == 0 && fifo_pos == 1)
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scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
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case S_PHASE_COMMAND:
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case S_PHASE_MSG_OUT:
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dma_set(dma_command ? DMA_OUT : DMA_NONE);
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state = INIT_XFR_SEND_BYTE;
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// if it's the last message byte, deassert ATN before sending
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if (xfr_phase == S_PHASE_MSG_OUT && ((!dma_command && fifo_pos == 1) || (dma_command && tcounter == 1)))
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scsi_bus->ctrl_w(scsi_refid, 0, S_ATN);
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send_byte();
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break;
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case S_PHASE_DATA_IN:
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dma_set(DMA_IN);
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state = tcount == fifo_pos+1 ?
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INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK;
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case S_PHASE_STATUS:
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case S_PHASE_MSG_IN:
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dma_set(dma_command ? DMA_IN : DMA_NONE);
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// if it's the last message byte, ACK remains asserted, terminate with function_complete()
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state = (xfr_phase == S_PHASE_MSG_IN && (!dma_command || tcounter == 1)) ? INIT_XFR_RECV_BYTE_NACK : INIT_XFR_RECV_BYTE_ACK;
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recv_byte();
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break;
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@ -435,20 +455,24 @@ void ncr5390_device::step(bool timeout)
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if(!(ctrl & S_REQ))
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break;
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if((ctrl & S_PHASE_MASK) != xfr_phase) {
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command_pos = 0;
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// check for command complete
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if ((dma_command && tcounter == 0 && fifo_pos == 0) // dma in/out: transfer counter == 0 and fifo empty
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|| (!dma_command && (xfr_phase & S_INP) == 0 && fifo_pos == 0) // non-dma out: fifo empty
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|| (!dma_command && (xfr_phase & S_INP) == S_INP && fifo_pos == 1)) // non-dma in: every byte
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bus_complete();
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} else {
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state = INIT_XFR;
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step(false);
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}
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else
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// check for phase change
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if((ctrl & S_PHASE_MASK) != xfr_phase) {
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command_pos = 0;
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bus_complete();
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} else {
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state = INIT_XFR;
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step(false);
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}
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break;
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case INIT_XFR_SEND_BYTE:
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if(tcount == 0 && fifo_pos == 0)
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bus_complete();
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else
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state = INIT_XFR_WAIT_REQ;
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state = INIT_XFR_WAIT_REQ;
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break;
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case INIT_XFR_RECV_BYTE_ACK:
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@ -474,8 +498,8 @@ void ncr5390_device::step(bool timeout)
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break;
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case INIT_XFR_SEND_PAD:
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tcount--;
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if(tcount) {
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tcounter--;
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if(tcounter) {
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state = INIT_XFR_SEND_PAD_WAIT_REQ;
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step(false);
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} else
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@ -496,8 +520,8 @@ void ncr5390_device::step(bool timeout)
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break;
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case INIT_XFR_RECV_PAD:
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tcount--;
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if(tcount) {
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tcounter--;
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if(tcounter) {
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state = INIT_XFR_RECV_PAD_WAIT_REQ;
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scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
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step(false);
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@ -575,10 +599,10 @@ void ncr5390_device::delay_cycles(int cycles)
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tm->adjust(clocks_to_attotime(cycles));
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}
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READ8_MEMBER(ncr5390_device::tcount_lo_r)
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READ8_MEMBER(ncr5390_device::tcounter_lo_r)
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{
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logerror("%s: tcount_lo_r %02x (%s)\n", tag(), tcount & 0xff, machine().describe_context());
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return tcount;
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logerror("%s: tcounter_lo_r %02x (%s)\n", tag(), tcounter & 0xff, machine().describe_context());
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return tcounter;
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}
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WRITE8_MEMBER(ncr5390_device::tcount_lo_w)
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@ -588,10 +612,10 @@ WRITE8_MEMBER(ncr5390_device::tcount_lo_w)
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logerror("%s: tcount_lo_w %02x (%s)\n", tag(), data, machine().describe_context());
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}
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READ8_MEMBER(ncr5390_device::tcount_hi_r)
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READ8_MEMBER(ncr5390_device::tcounter_hi_r)
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{
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logerror("%s: tcount_hi_r %02x (%s)\n", tag(), tcount >> 8, machine().describe_context());
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return tcount >> 8;
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logerror("%s: tcounter_hi_r %02x (%s)\n", tag(), tcounter >> 8, machine().describe_context());
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return tcounter >> 8;
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}
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WRITE8_MEMBER(ncr5390_device::tcount_hi_w)
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@ -606,7 +630,7 @@ uint8_t ncr5390_device::fifo_pop()
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uint8_t r = fifo[0];
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fifo_pos--;
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memmove(fifo, fifo+1, fifo_pos);
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if((!fifo_pos) && tcount && dma_dir == DMA_OUT)
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if((!fifo_pos) && tcounter && dma_dir == DMA_OUT)
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drq_set();
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return r;
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}
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@ -676,6 +700,11 @@ void ncr5390_device::start_command()
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return;
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}
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// for dma commands, reload transfer counter
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dma_command = command[0] & 0x80;
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if (dma_command)
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tcounter = tcount;
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switch(c) {
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case CM_NOP:
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command_pop_and_chain();
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@ -728,6 +757,12 @@ void ncr5390_device::start_command()
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case CI_MSG_ACCEPT:
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state = INIT_MSG_WAIT_REQ;
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// It's undocumented what the sequence register should contain after a message accept
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// command, but the InterPro boot code expects it to be non-zero; setting it to an
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// arbirary 1 here makes InterPro happy. Also in the InterPro case (perhaps typical),
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// after ACK is asserted the device disconnects and the INIT_MSG_WAIT_REQ state is never
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// entered, meaning we end up with I_DISCONNECT instead of I_BUS interrupt status.
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seq = 1;
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scsi_bus->ctrl_w(scsi_refid, 0, S_ACK);
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step(false);
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break;
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@ -847,6 +882,16 @@ WRITE8_MEMBER(ncr5390_device::conf_w)
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{
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config = data;
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scsi_id = data & 7;
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// test mode can only be cleared by hard/soft reset
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if (data & 0x8)
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test_mode = true;
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}
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WRITE8_MEMBER(ncr5390_device::test_w)
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{
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if (test_mode)
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logerror("%s: test_w %d (%s) - test mode not implemented\n", tag(), data, machine().describe_context());
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}
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WRITE8_MEMBER(ncr5390_device::clock_w)
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@ -857,15 +902,15 @@ WRITE8_MEMBER(ncr5390_device::clock_w)
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void ncr5390_device::dma_set(int dir)
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{
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dma_dir = dir;
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if(dma_dir == DMA_OUT && fifo_pos != 16 && tcount != 0)
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if(dma_dir == DMA_OUT && fifo_pos != 16 && tcounter != 0)
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drq_set();
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}
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void ncr5390_device::dma_w(uint8_t val)
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{
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fifo_push(val);
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tcount--;
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if(fifo_pos == 16 || tcount == 0)
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tcounter--;
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if(fifo_pos == 16 || tcounter == 0)
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drq_clear();
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}
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@ -874,8 +919,8 @@ uint8_t ncr5390_device::dma_r()
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uint8_t r = fifo_pop();
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if(!fifo_pos)
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drq_clear();
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tcount--;
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if(tcount == 0) {
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tcounter--;
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if(tcounter == 0) {
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status |= S_TC0;
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step(false);
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}
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@ -898,39 +943,64 @@ void ncr5390_device::drq_clear()
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}
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}
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void ncr53c94_device::device_start()
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{
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save_item(NAME(test_mode));
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save_item(NAME(config2));
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save_item(NAME(config3));
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/*
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* According to the NCR 53C90A, 53C90B data book (http://bitsavers.informatik.uni-stuttgart.de/pdf/ncr/scsi/NCR53C90ab.pdf),
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* the following are the differences from the 53C90:
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*
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* - Supports three-byte message exchange SCSI-2 tagged queueing
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* - Added select with ATN3 command
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* - Added target DMA abort command
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* - Added interrupt polling bit
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* - Added second configuration register
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* - Improved immunity to cable impedance mismatches and improper termination
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* - Tri-state DMA request output
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* - Cut leakage current on SCSI input pins when powered off
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* - Relaxed register timings
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* - Relaxed DMA timings
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* - Relaxed CLK duty cycle
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* - Lengthened read data access time
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* - NOP required less often
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*/
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void ncr53c90a_device::device_start()
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{
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save_item(NAME(config2));
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test_mode = false;
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config2 = 0;
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config3 = 0;
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ncr5390_device::device_start();
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}
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void ncr53c94_device::reset_soft()
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void ncr53c90a_device::reset_soft()
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{
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test_mode = false;
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config2 = 0;
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config3 = 0;
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ncr5390_device::reset_soft();
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}
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WRITE8_MEMBER(ncr53c94_device::conf_w)
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READ8_MEMBER(ncr53c90a_device::status_r)
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{
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ncr5390_device::conf_w(space, offset, data, mem_mask);
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// test mode can only be cleared by hard/soft reset
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if (data & 0x8)
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test_mode = true;
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uint32_t ctrl = scsi_bus->ctrl_r();
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uint8_t res = (irq ? S_INTERRUPT : 0) | status | (ctrl & S_MSG ? 4 : 0) | (ctrl & S_CTL ? 2 : 0) | (ctrl & S_INP ? 1 : 0);
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logerror("%s: status_r %02x (%s)\n", tag(), res, machine().describe_context());
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if (irq)
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status &= ~(S_GROSS_ERROR | S_PARITY | S_TCC);
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return res;
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}
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WRITE8_MEMBER(ncr53c94_device::test_w)
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void ncr53c94_device::device_start()
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{
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if (test_mode)
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logerror("%s: test_w %d (%s) - test mode not implemented\n", tag(), data, machine().describe_context());
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save_item(NAME(config3));
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config3 = 0;
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ncr53c90a_device::device_start();
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}
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void ncr53c94_device::reset_soft()
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{
|
||||
config3 = 0;
|
||||
|
||||
ncr53c90a_device::reset_soft();
|
||||
}
|
||||
|
||||
@ -24,9 +24,9 @@ public:
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 8);
|
||||
|
||||
DECLARE_READ8_MEMBER(tcount_lo_r);
|
||||
DECLARE_READ8_MEMBER(tcounter_lo_r);
|
||||
DECLARE_WRITE8_MEMBER(tcount_lo_w);
|
||||
DECLARE_READ8_MEMBER(tcount_hi_r);
|
||||
DECLARE_READ8_MEMBER(tcounter_hi_r);
|
||||
DECLARE_WRITE8_MEMBER(tcount_hi_w);
|
||||
DECLARE_READ8_MEMBER(fifo_r);
|
||||
DECLARE_WRITE8_MEMBER(fifo_w);
|
||||
@ -42,6 +42,7 @@ public:
|
||||
DECLARE_WRITE8_MEMBER(sync_offset_w);
|
||||
DECLARE_READ8_MEMBER(conf_r);
|
||||
DECLARE_WRITE8_MEMBER(conf_w);
|
||||
DECLARE_WRITE8_MEMBER(test_w);
|
||||
DECLARE_WRITE8_MEMBER(clock_w);
|
||||
|
||||
virtual void scsi_ctrl_changed() override;
|
||||
@ -49,6 +50,10 @@ public:
|
||||
uint8_t dma_r();
|
||||
void dma_w(uint8_t val);
|
||||
|
||||
// memory mapped wrappers for dma read/write
|
||||
DECLARE_READ8_MEMBER(mdma_r) { return dma_r(); }
|
||||
DECLARE_WRITE8_MEMBER(mdma_w) { dma_w(data); }
|
||||
|
||||
protected:
|
||||
ncr5390_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
@ -56,7 +61,6 @@ protected:
|
||||
virtual void device_reset() override;
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
|
||||
private:
|
||||
enum { MODE_D, MODE_T, MODE_I };
|
||||
enum { IDLE };
|
||||
|
||||
@ -192,6 +196,7 @@ private:
|
||||
uint8_t clock_conv, sync_offset, sync_period, bus_id, select_timeout, seq;
|
||||
uint8_t fifo[16];
|
||||
uint16_t tcount;
|
||||
uint16_t tcounter;
|
||||
int mode, fifo_pos, command_pos;
|
||||
int state, xfr_phase;
|
||||
int command_length;
|
||||
@ -199,6 +204,8 @@ private:
|
||||
int dma_dir;
|
||||
|
||||
bool irq, drq;
|
||||
bool dma_command;
|
||||
bool test_mode;
|
||||
|
||||
void dma_set(int dir);
|
||||
void drq_set();
|
||||
@ -234,18 +241,40 @@ private:
|
||||
devcb_write_line m_drq_handler;
|
||||
};
|
||||
|
||||
class ncr53c94_device : public ncr5390_device
|
||||
class ncr53c90a_device : public ncr5390_device
|
||||
{
|
||||
public:
|
||||
ncr53c90a_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 8) override;
|
||||
|
||||
DECLARE_READ8_MEMBER(status_r);
|
||||
|
||||
DECLARE_READ8_MEMBER(conf2_r) { return config2; };
|
||||
DECLARE_WRITE8_MEMBER(conf2_w) { config2 = data; };
|
||||
|
||||
protected:
|
||||
ncr53c90a_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual void device_start() override;
|
||||
void reset_soft();
|
||||
|
||||
// 53c90a uses a previously reserved bit as an interrupt flag
|
||||
enum {
|
||||
S_INTERRUPT = 0x80,
|
||||
};
|
||||
|
||||
private:
|
||||
u8 config2;
|
||||
};
|
||||
|
||||
class ncr53c94_device : public ncr53c90a_device
|
||||
{
|
||||
public:
|
||||
ncr53c94_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
virtual DECLARE_ADDRESS_MAP(map, 8) override;
|
||||
|
||||
DECLARE_WRITE8_MEMBER(conf_w);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(test_w);
|
||||
DECLARE_READ8_MEMBER(conf2_r) { return config2; };
|
||||
DECLARE_WRITE8_MEMBER(conf2_w) { config2 = data; };
|
||||
DECLARE_READ8_MEMBER(conf3_r) { return config3; };
|
||||
DECLARE_WRITE8_MEMBER(conf3_w) { config3 = data; };
|
||||
DECLARE_WRITE8_MEMBER(fifo_align_w) { fifo_align = data; };
|
||||
@ -255,13 +284,12 @@ protected:
|
||||
void reset_soft();
|
||||
|
||||
private:
|
||||
bool test_mode;
|
||||
u8 config2;
|
||||
u8 config3;
|
||||
u8 fifo_align;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(NCR5390, ncr5390_device)
|
||||
DECLARE_DEVICE_TYPE(NCR53C90A, ncr53c90a_device)
|
||||
DECLARE_DEVICE_TYPE(NCR53C94, ncr53c94_device)
|
||||
|
||||
#endif // MAME_MACHINE_NCR5390_H
|
||||
|
||||
@ -265,8 +265,8 @@ READ8_MEMBER(interpro_state::scsi_r)
|
||||
#if NEW_SCSI
|
||||
switch (offset >> 6)
|
||||
{
|
||||
case 0x0: return m_scsi->tcount_lo_r(space, 0);
|
||||
case 0x1: return m_scsi->tcount_hi_r(space, 0);
|
||||
case 0x0: return m_scsi->tcounter_lo_r(space, 0);
|
||||
case 0x1: return m_scsi->tcounter_hi_r(space, 0);
|
||||
case 0x2: return m_scsi->fifo_r(space, 0);
|
||||
case 0x3: return m_scsi->command_r(space, 0);
|
||||
case 0x4: return m_scsi->status_r(space, 0);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user