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Arm Thumb: same but handle 2 magical ROR cases (nw)

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This commit is contained in:
MetalliC 2017-12-24 09:52:58 +02:00
parent 25f84e3bf0
commit e598882d59
1 changed files with 22 additions and 19 deletions
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41
src/devices/cpu/arm7/arm7thmb.cpp
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@ -977,7 +977,7 @@ void arm7_cpu_device::tg05_0(uint32_t pc, uint32_t op) /* STR Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm);
WRITE32(addr, GetRegister(rd));
WRITE32(addr & ~3, GetRegister(rd));
R15 += 2;
}
@ -987,7 +987,7 @@ void arm7_cpu_device::tg05_1(uint32_t pc, uint32_t op) /* STRH Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm);
WRITE16(addr, GetRegister(rd));
WRITE16(addr & ~1, GetRegister(rd));
R15 += 2;
}
@ -1022,8 +1022,9 @@ void arm7_cpu_device::tg05_4(uint32_t pc, uint32_t op) /* LDR Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm);
uint32_t op2 = READ32(addr);
SetRegister(rd, op2);
uint32_t tmp = READ32(addr & ~3);
addr = (addr & 3) << 3;
SetRegister(rd, ROR(tmp, addr));
R15 += 2;
}
@ -1033,7 +1034,7 @@ void arm7_cpu_device::tg05_5(uint32_t pc, uint32_t op) /* LDRH Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm);
uint32_t op2 = READ16(addr);
uint32_t op2 = READ16(addr & ~1);
SetRegister(rd, op2);
R15 += 2;
}
@ -1055,7 +1056,7 @@ void arm7_cpu_device::tg05_7(uint32_t pc, uint32_t op) /* LDSH Rd, [Rn, Rm] */
uint32_t rn = (op & THUMB_GROUP5_RN) >> THUMB_GROUP5_RN_SHIFT;
uint32_t rd = (op & THUMB_GROUP5_RD) >> THUMB_GROUP5_RD_SHIFT;
uint32_t addr = GetRegister(rn) + GetRegister(rm);
uint32_t op2 = READ16(addr);
uint32_t op2 = READ16(addr & ~1);
if (op2 & 0x00008000)
{
op2 |= 0xffff0000;
@ -1071,7 +1072,7 @@ void arm7_cpu_device::tg06_0(uint32_t pc, uint32_t op) /* Store */
uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = op & THUMB_ADDSUB_RD;
int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
WRITE32(GetRegister(rn) + offs, GetRegister(rd));
WRITE32((GetRegister(rn) + offs) & ~3, GetRegister(rd));
R15 += 2;
}
@ -1079,8 +1080,10 @@ void arm7_cpu_device::tg06_1(uint32_t pc, uint32_t op) /* Load */
{
uint32_t rn = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = op & THUMB_ADDSUB_RD;
int32_t offs = ((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2;
SetRegister(rd, READ32(GetRegister(rn) + offs)); // fix
uint32_t addr = GetRegister(rn) + (((op & THUMB_LSOP_OFFS) >> THUMB_LSOP_OFFS_SHIFT) << 2);
uint32_t tmp = READ32(addr & ~3);
addr = (addr & 3) << 3;
SetRegister(rd, ROR(tmp, addr));
R15 += 2;
}
@ -1111,7 +1114,7 @@ void arm7_cpu_device::tg08_0(uint32_t pc, uint32_t op) /* Store */
uint32_t imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
WRITE16(GetRegister(rs) + (imm << 1), GetRegister(rd));
WRITE16((GetRegister(rs) + (imm << 1)) & ~1, GetRegister(rd));
R15 += 2;
}
@ -1120,7 +1123,7 @@ void arm7_cpu_device::tg08_1(uint32_t pc, uint32_t op) /* Load */
uint32_t imm = (op & THUMB_HALFOP_OFFS) >> THUMB_HALFOP_OFFS_SHIFT;
uint32_t rs = (op & THUMB_ADDSUB_RS) >> THUMB_ADDSUB_RS_SHIFT;
uint32_t rd = (op & THUMB_ADDSUB_RD) >> THUMB_ADDSUB_RD_SHIFT;
SetRegister(rd, READ16(GetRegister(rs) + (imm << 1)));
SetRegister(rd, READ16((GetRegister(rs) + (imm << 1)) & ~1));
R15 += 2;
}
@ -1130,7 +1133,7 @@ void arm7_cpu_device::tg09_0(uint32_t pc, uint32_t op) /* Store */
{
uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
int32_t offs = (uint8_t)(op & THUMB_INSN_IMM);
WRITE32(GetRegister(13) + ((uint32_t)offs << 2), GetRegister(rd));
WRITE32((GetRegister(13) + ((uint32_t)offs << 2)) & ~3, GetRegister(rd));
R15 += 2;
}
@ -1138,7 +1141,7 @@ void arm7_cpu_device::tg09_1(uint32_t pc, uint32_t op) /* Load */
{
uint32_t rd = (op & THUMB_STACKOP_RD) >> THUMB_STACKOP_RD_SHIFT;
int32_t offs = (uint8_t)(op & THUMB_INSN_IMM);
uint32_t readword = READ32(GetRegister(13) + ((uint32_t)offs << 2));
uint32_t readword = READ32((GetRegister(13) + ((uint32_t)offs << 2)) & ~3);
SetRegister(rd, readword);
R15 += 2;
}
@ -1193,7 +1196,7 @@ void arm7_cpu_device::tg0b_4(uint32_t pc, uint32_t op) /* PUSH {Rlist} */
if (op & (1 << offs))
{
SetRegister(13, GetRegister(13) - 4);
WRITE32(GetRegister(13), GetRegister(offs));
WRITE32(GetRegister(13) & ~3, GetRegister(offs));
}
}
R15 += 2;
@ -1202,13 +1205,13 @@ void arm7_cpu_device::tg0b_4(uint32_t pc, uint32_t op) /* PUSH {Rlist} */
void arm7_cpu_device::tg0b_5(uint32_t pc, uint32_t op) /* PUSH {Rlist}{LR} */
{
SetRegister(13, GetRegister(13) - 4);
WRITE32(GetRegister(13), GetRegister(14));
WRITE32(GetRegister(13) & ~3, GetRegister(14));
for (int32_t offs = 7; offs >= 0; offs--)
{
if (op & (1 << offs))
{
SetRegister(13, GetRegister(13) - 4);
WRITE32(GetRegister(13), GetRegister(offs));
WRITE32(GetRegister(13) & ~3, GetRegister(offs));
}
}
R15 += 2;
@ -1250,7 +1253,7 @@ void arm7_cpu_device::tg0b_c(uint32_t pc, uint32_t op) /* POP {Rlist} */
{
if (op & (1 << offs))
{
SetRegister(offs, READ32(GetRegister(13)));
SetRegister(offs, READ32(GetRegister(13) & ~3));
SetRegister(13, GetRegister(13) + 4);
}
}
@ -1263,11 +1266,11 @@ void arm7_cpu_device::tg0b_d(uint32_t pc, uint32_t op) /* POP {Rlist}{PC} */
{
if (op & (1 << offs))
{
SetRegister(offs, READ32(GetRegister(13)));
SetRegister(offs, READ32(GetRegister(13) & ~3));
SetRegister(13, GetRegister(13) + 4);
}
}
uint32_t addr = READ32(GetRegister(13));
uint32_t addr = READ32(GetRegister(13) & ~3);
if (m_archRev < 5)
{
R15 = addr & ~1;