From e5a80b0bdbdf60230239e0349680715686807632 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Sun, 26 Jan 2014 22:07:42 +0000 Subject: [PATCH] sharc.c: Modernized cpu core. [Wilbert Pol] --- src/emu/cpu/sharc/compute.c | 498 +++++------ src/emu/cpu/sharc/sharc.c | 1369 +++++++++++------------------ src/emu/cpu/sharc/sharc.h | 333 ++++++- src/emu/cpu/sharc/sharcdma.c | 206 +++-- src/emu/cpu/sharc/sharcmem.c | 96 +- src/emu/cpu/sharc/sharcops.c | 1609 +++++++++++++++++----------------- src/emu/cpu/sharc/sharcops.h | 94 +- src/mame/drivers/gticlub.c | 16 +- src/mame/drivers/hornet.c | 8 +- src/mame/drivers/model2.c | 35 +- src/mame/drivers/nwk-tr.c | 7 +- src/mame/drivers/zr107.c | 13 +- src/mame/machine/konppc.c | 26 +- src/mame/video/gticlub.c | 12 +- src/mame/video/k001005.c | 14 +- src/mame/video/k001005.h | 2 +- 16 files changed, 2136 insertions(+), 2202 deletions(-) diff --git a/src/emu/cpu/sharc/compute.c b/src/emu/cpu/sharc/compute.c index 1d026ea0339..0d60de824e8 100644 --- a/src/emu/cpu/sharc/compute.c +++ b/src/emu/cpu/sharc/compute.c @@ -2,27 +2,27 @@ #include -#define CLEAR_ALU_FLAGS() (cpustate->astat &= ~(AZ|AN|AV|AC|AS|AI)) +#define CLEAR_ALU_FLAGS() (m_astat &= ~(AZ|AN|AV|AC|AS|AI)) -#define SET_FLAG_AZ(r) { cpustate->astat |= (((r) == 0) ? AZ : 0); } -#define SET_FLAG_AN(r) { cpustate->astat |= (((r) & 0x80000000) ? AN : 0); } -#define SET_FLAG_AC_ADD(r,a,b) { cpustate->astat |= (((UINT32)r < (UINT32)a) ? AC : 0); } -#define SET_FLAG_AV_ADD(r,a,b) { cpustate->astat |= (((~((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } -#define SET_FLAG_AC_SUB(r,a,b) { cpustate->astat |= ((!((UINT32)a < (UINT32)b)) ? AC : 0); } -#define SET_FLAG_AV_SUB(r,a,b) { cpustate->astat |= ((( ((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } +#define SET_FLAG_AZ(r) { m_astat |= (((r) == 0) ? AZ : 0); } +#define SET_FLAG_AN(r) { m_astat |= (((r) & 0x80000000) ? AN : 0); } +#define SET_FLAG_AC_ADD(r,a,b) { m_astat |= (((UINT32)r < (UINT32)a) ? AC : 0); } +#define SET_FLAG_AV_ADD(r,a,b) { m_astat |= (((~((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } +#define SET_FLAG_AC_SUB(r,a,b) { m_astat |= ((!((UINT32)a < (UINT32)b)) ? AC : 0); } +#define SET_FLAG_AV_SUB(r,a,b) { m_astat |= ((( ((a) ^ (b)) & ((a) ^ (r))) & 0x80000000) ? AV : 0); } #define IS_FLOAT_ZERO(r) ((((r) & 0x7fffffff) == 0)) #define IS_FLOAT_DENORMAL(r) ((((r) & 0x7f800000) == 0) && (((r) & 0x7fffff) != 0)) #define IS_FLOAT_NAN(r) ((((r) & 0x7f800000) == 0x7f800000) && (((r) & 0x7fffff) != 0)) #define IS_FLOAT_INFINITY(r) (((r) & 0x7fffffff) == 0x7f800000) -#define CLEAR_MULTIPLIER_FLAGS() (cpustate->astat &= ~(MN|MV|MU|MI)) +#define CLEAR_MULTIPLIER_FLAGS() (m_astat &= ~(MN|MV|MU|MI)) -#define SET_FLAG_MN(r) { cpustate->astat |= (((r) & 0x80000000) ? MN : 0); } -#define SET_FLAG_MV(r) { cpustate->astat |= ((((UINT32)((r) >> 32) != 0) && ((UINT32)((r) >> 32) != 0xffffffff)) ? MV : 0); } +#define SET_FLAG_MN(r) { m_astat |= (((r) & 0x80000000) ? MN : 0); } +#define SET_FLAG_MV(r) { m_astat |= ((((UINT32)((r) >> 32) != 0) && ((UINT32)((r) >> 32) != 0xffffffff)) ? MV : 0); } /* TODO: MU needs 80-bit result */ -#define SET_FLAG_MU(r) { cpustate->astat |= ((((UINT32)((r) >> 32) == 0) && ((UINT32)(r)) != 0) ? MU : 0); } +#define SET_FLAG_MU(r) { m_astat |= ((((UINT32)((r) >> 32) == 0) && ((UINT32)(r)) != 0) ? MU : 0); } #define FLOAT_SIGN 0x80000000 @@ -109,11 +109,11 @@ static const UINT32 rsqrts_mantissa_lookup[128] = /* Integer ALU operations */ /* Rn = Rx + Ry */ -INLINE void compute_add(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_add(int rn, int rx, int ry) { UINT32 r = REG(rx) + REG(ry); - if (cpustate->mode1 & MODE1_ALUSAT) + if (m_mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_add: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); @@ -123,15 +123,15 @@ INLINE void compute_add(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AC_ADD(r, REG(rx), REG(ry)); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx - Ry */ -INLINE void compute_sub(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_sub(int rn, int rx, int ry) { UINT32 r = REG(rx) - REG(ry); - if (cpustate->mode1 & MODE1_ALUSAT) + if (m_mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_sub: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); @@ -141,16 +141,16 @@ INLINE void compute_sub(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AC_SUB(r, REG(rx), REG(ry)); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx + Ry + CI */ -INLINE void compute_add_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_add_ci(int rn, int rx, int ry) { - int c = (cpustate->astat & AC) ? 1 : 0; + int c = (m_astat & AC) ? 1 : 0; UINT32 r = REG(rx) + REG(ry) + c; - if (cpustate->mode1 & MODE1_ALUSAT) + if (m_mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_add_ci: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); @@ -160,16 +160,16 @@ INLINE void compute_add_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AC_ADD(r, REG(rx), REG(ry)+c); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx - Ry + CI - 1 */ -INLINE void compute_sub_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_sub_ci(int rn, int rx, int ry) { - int c = (cpustate->astat & AC) ? 1 : 0; + int c = (m_astat & AC) ? 1 : 0; UINT32 r = REG(rx) - REG(ry) + c - 1; - if (cpustate->mode1 & MODE1_ALUSAT) + if (m_mode1 & MODE1_ALUSAT) fatalerror("SHARC: compute_sub_ci: ALU saturation not implemented!\n"); CLEAR_ALU_FLAGS(); @@ -179,11 +179,11 @@ INLINE void compute_sub_ci(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AC_SUB(r, REG(rx), REG(ry)+c-1); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx AND Ry */ -INLINE void compute_and(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_and(int rn, int rx, int ry) { UINT32 r = REG(rx) & REG(ry); @@ -192,50 +192,50 @@ INLINE void compute_and(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AZ(r); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* COMP(Rx, Ry) */ -INLINE void compute_comp(SHARC_REGS *cpustate, int rx, int ry) +void adsp21062_device::compute_comp(int rx, int ry) { UINT32 comp_accum; CLEAR_ALU_FLAGS(); if( REG(rx) == REG(ry) ) - cpustate->astat |= AZ; + m_astat |= AZ; if( (INT32)REG(rx) < (INT32)REG(ry) ) - cpustate->astat |= AN; + m_astat |= AN; // Update ASTAT compare accumulation register - comp_accum = (cpustate->astat >> 24) & 0xff; + comp_accum = (m_astat >> 24) & 0xff; comp_accum >>= 1; - if ((cpustate->astat & (AZ|AN)) == 0) + if ((m_astat & (AZ|AN)) == 0) { comp_accum |= 0x80; } - cpustate->astat &= 0xffffff; - cpustate->astat |= comp_accum << 24; + m_astat &= 0xffffff; + m_astat |= comp_accum << 24; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = PASS Rx */ -INLINE void compute_pass(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_pass(int rn, int rx) { CLEAR_ALU_FLAGS(); /* TODO: floating-point extension field is set to 0 */ REG(rn) = REG(rx); if (REG(rn) == 0) - cpustate->astat |= AZ; + m_astat |= AZ; if (REG(rn) & 0x80000000) - cpustate->astat |= AN; + m_astat |= AN; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx XOR Ry */ -INLINE void compute_xor(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_xor(int rn, int rx, int ry) { UINT32 r = REG(rx) ^ REG(ry); CLEAR_ALU_FLAGS(); @@ -243,11 +243,11 @@ INLINE void compute_xor(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AZ(r); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx OR Ry */ -INLINE void compute_or(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_or(int rn, int rx, int ry) { UINT32 r = REG(rx) | REG(ry); CLEAR_ALU_FLAGS(); @@ -255,11 +255,11 @@ INLINE void compute_or(SHARC_REGS *cpustate, int rn, int rx, int ry) SET_FLAG_AZ(r); REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx + 1 */ -INLINE void compute_inc(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_inc(int rn, int rx) { UINT32 r = REG(rx) + 1; @@ -271,11 +271,11 @@ INLINE void compute_inc(SHARC_REGS *cpustate, int rn, int rx) REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = Rx - 1 */ -INLINE void compute_dec(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_dec(int rn, int rx) { UINT32 r = REG(rx) - 1; @@ -287,11 +287,11 @@ INLINE void compute_dec(SHARC_REGS *cpustate, int rn, int rx) REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = MIN(Rx, Ry) */ -INLINE void compute_min(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_min(int rn, int rx, int ry) { UINT32 r = MIN((INT32)REG(rx), (INT32)REG(ry)); @@ -301,11 +301,11 @@ INLINE void compute_min(SHARC_REGS *cpustate, int rn, int rx, int ry) REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = MAX(Rx, Ry) */ -INLINE void compute_max(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_max(int rn, int rx, int ry) { UINT32 r = MAX((INT32)REG(rx), (INT32)REG(ry)); @@ -315,11 +315,11 @@ INLINE void compute_max(SHARC_REGS *cpustate, int rn, int rx, int ry) REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = -Rx */ -INLINE void compute_neg(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_neg(int rn, int rx) { UINT32 r = -(INT32)(REG(rx)); @@ -331,11 +331,11 @@ INLINE void compute_neg(SHARC_REGS *cpustate, int rn, int rx) REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rn = NOT Rx */ -INLINE void compute_not(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_not(int rn, int rx) { UINT32 r = ~REG(rx); @@ -345,13 +345,13 @@ INLINE void compute_not(SHARC_REGS *cpustate, int rn, int rx) REG(rn) = r; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /*****************************************************************************/ /* Floating-point ALU operations */ -INLINE UINT32 SCALB(SHARC_REGS *cpustate, SHARC_REG rx, int ry) +UINT32 adsp21062_device::SCALB(SHARC_REG rx, int ry) { UINT32 mantissa = rx.r & FLOAT_MANTISSA; UINT32 sign = rx.r & FLOAT_SIGN; @@ -362,13 +362,13 @@ INLINE UINT32 SCALB(SHARC_REGS *cpustate, SHARC_REG rx, int ry) if (exponent > 127) { // overflow - cpustate->astat |= AV; + m_astat |= AV; return sign | FLOAT_INFINITY; } else if (exponent < -126) { // denormal - cpustate->astat |= AZ; + m_astat |= AZ; return sign; } else @@ -378,7 +378,7 @@ INLINE UINT32 SCALB(SHARC_REGS *cpustate, SHARC_REG rx, int ry) } /* Fn = FLOAT Rx */ -INLINE void compute_float(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_float(int rn, int rx) { // verified FREG(rn) = (float)(INT32)REG(rx); @@ -387,22 +387,22 @@ INLINE void compute_float(SHARC_REGS *cpustate, int rn, int rx) // AN SET_FLAG_AN(REG(rn)); // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; /* TODO: AV flag */ - cpustate->astat |= AF; + m_astat |= AF; } /* Rn = FIX Fx */ -INLINE void compute_fix(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_fix(int rn, int rx) { INT32 alu_i; SHARC_REG r_alu; r_alu.f = FREG(rx); - if (cpustate->mode1 & MODE1_TRUNCATE) + if (m_mode1 & MODE1_TRUNCATE) { alu_i = (INT32)(r_alu.f); } @@ -416,23 +416,23 @@ INLINE void compute_fix(SHARC_REGS *cpustate, int rn, int rx) // AZ SET_FLAG_AZ(alu_i); // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; /* TODO: AV flag */ REG(rn) = alu_i; - cpustate->astat |= AF; + m_astat |= AF; } /* Rn = FIX Fx BY Ry */ -INLINE void compute_fix_scaled(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fix_scaled(int rn, int rx, int ry) { INT32 alu_i; SHARC_REG r_alu; - r_alu.r = SCALB(cpustate, cpustate->r[rx], ry); - if (cpustate->mode1 & MODE1_TRUNCATE) + r_alu.r = SCALB(m_r[rx], ry); + if (m_mode1 & MODE1_TRUNCATE) { alu_i = (INT32)(r_alu.f); } @@ -446,17 +446,17 @@ INLINE void compute_fix_scaled(SHARC_REGS *cpustate, int rn, int rx, int ry) // AZ SET_FLAG_AZ(alu_i); // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; /* TODO: AV flag */ REG(rn) = alu_i; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = FLOAT Rx BY Ry */ -INLINE void compute_float_scaled(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_float_scaled(int rn, int rx, int ry) { SHARC_REG x; x.f = (float)(INT32)(REG(rx)); @@ -464,20 +464,20 @@ INLINE void compute_float_scaled(SHARC_REGS *cpustate, int rn, int rx, int ry) // verified CLEAR_ALU_FLAGS(); - REG(rn) = SCALB(cpustate, x, ry); + REG(rn) = SCALB(x, ry); // AN SET_FLAG_AN(REG(rn)); // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(REG(rn)) || IS_FLOAT_ZERO(REG(rn))) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(REG(rn))) ? AUS : 0; - cpustate->astat |= AF; + m_astat |= AF; } /* Rn = LOGB Fx */ -INLINE void compute_logb(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_logb(int rn, int rx) { // verified UINT32 r = REG(rx); @@ -488,20 +488,20 @@ INLINE void compute_logb(SHARC_REGS *cpustate, int rn, int rx) { REG(rn) = FLOAT_INFINITY; - cpustate->astat |= AV; + m_astat |= AV; } else if (IS_FLOAT_ZERO(REG(rx))) { REG(rn) = FLOAT_SIGN | FLOAT_INFINITY; - cpustate->astat |= AV; + m_astat |= AV; } else if (IS_FLOAT_NAN(REG(rx))) { REG(rn) = 0xffffffff; - cpustate->astat |= AI; - cpustate->stky |= AIS; + m_astat |= AI; + m_stky |= AIS; } else { @@ -515,11 +515,11 @@ INLINE void compute_logb(SHARC_REGS *cpustate, int rn, int rx) REG(rn) = exponent; } - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = SCALB Fx BY Fy */ -INLINE void compute_scalb(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_scalb(int rn, int rx, int ry) { // verified SHARC_REG r; @@ -527,192 +527,192 @@ INLINE void compute_scalb(SHARC_REGS *cpustate, int rn, int rx, int ry) if (IS_FLOAT_NAN(REG(rx))) { - cpustate->astat |= AI; - cpustate->stky |= AIS; + m_astat |= AI; + m_stky |= AIS; REG(rn) = 0xffffffff; } else { - r.r = SCALB(cpustate, cpustate->r[rx], ry); + r.r = SCALB(m_r[rx], ry); // AN SET_FLAG_AN(r.r); // AZ - cpustate->astat |= IS_FLOAT_ZERO(r.r) ? AZ : 0; + m_astat |= IS_FLOAT_ZERO(r.r) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; FREG(rn) = r.f; } - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = Fx + Fy */ -INLINE void compute_fadd(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fadd(int rn, int rx, int ry) { SHARC_REG r; r.f = FREG(rx) + FREG(ry); CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= (r.f < 0.0f) ? AN : 0; + m_astat |= (r.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(rn) = r.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = Fx - Fy */ -INLINE void compute_fsub(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fsub(int rn, int rx, int ry) { SHARC_REG r; r.f = FREG(rx) - FREG(ry); CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= (r.f < 0.0f) ? AN : 0; + m_astat |= (r.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(rn) = r.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = -Fx */ -INLINE void compute_fneg(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_fneg(int rn, int rx) { SHARC_REG r; r.f = -FREG(rx); CLEAR_ALU_FLAGS(); // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AN - cpustate->astat |= (r.f < 0.0f) ? AN : 0; + m_astat |= (r.f < 0.0f) ? AN : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(rn) = r.f; - cpustate->astat |= AF; + m_astat |= AF; } /* COMP(Fx, Fy) */ -INLINE void compute_fcomp(SHARC_REGS *cpustate, int rx, int ry) +void adsp21062_device::compute_fcomp(int rx, int ry) { UINT32 comp_accum; CLEAR_ALU_FLAGS(); // AZ if( FREG(rx) == FREG(ry) ) - cpustate->astat |= AZ; + m_astat |= AZ; // AN if( FREG(rx) < FREG(ry) ) - cpustate->astat |= AN; + m_astat |= AN; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; // Update ASTAT compare accumulation register - comp_accum = (cpustate->astat >> 24) & 0xff; + comp_accum = (m_astat >> 24) & 0xff; comp_accum >>= 1; - if ((cpustate->astat & (AZ|AN)) == 0) + if ((m_astat & (AZ|AN)) == 0) { comp_accum |= 0x80; } - cpustate->astat &= 0xffffff; - cpustate->astat |= comp_accum << 24; - cpustate->astat |= AF; + m_astat &= 0xffffff; + m_astat |= comp_accum << 24; + m_astat |= AF; } /* Fn = ABS(Fx + Fy) */ -INLINE void compute_fabs_plus(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fabs_plus(int rn, int rx, int ry) { SHARC_REG r; r.f = fabs(FREG(rx) + FREG(ry)); CLEAR_ALU_FLAGS(); // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(r.r) || IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(rn) = r.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = MAX(Fx, Fy) */ -INLINE void compute_fmax(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fmax(int rn, int rx, int ry) { SHARC_REG r_alu; r_alu.f = MAX(FREG(rx), FREG(ry)); CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; + m_astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ FREG(rn) = r_alu.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = MIN(Fx, Fy) */ -INLINE void compute_fmin(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fmin(int rn, int rx, int ry) { SHARC_REG r_alu; r_alu.f = MIN(FREG(rx), FREG(ry)); CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; + m_astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ FREG(rn) = r_alu.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = CLIP Fx BY Fy */ -INLINE void compute_fclip(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fclip(int rn, int rx, int ry) { SHARC_REG r_alu; @@ -736,18 +736,18 @@ INLINE void compute_fclip(SHARC_REGS *cpustate, int rn, int rx, int ry) CLEAR_ALU_FLAGS(); SET_FLAG_AN(r_alu.r); // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; FREG(rn) = r_alu.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = RECIPS Fx */ -INLINE void compute_recips(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_recips(int rn, int rx) { // verified UINT32 r; @@ -760,17 +760,17 @@ INLINE void compute_recips(SHARC_REGS *cpustate, int rn, int rx) r = 0xffffffff; // AI - cpustate->astat |= AI; + m_astat |= AI; // AIS - cpustate->stky |= AIS; + m_stky |= AIS; } else if (IS_FLOAT_ZERO(REG(rx))) { // +- Zero r = (REG(rx) & FLOAT_SIGN) | FLOAT_INFINITY; - cpustate->astat |= AZ; + m_astat |= AZ; } else { @@ -795,23 +795,23 @@ INLINE void compute_recips(SHARC_REGS *cpustate, int rn, int rx) SET_FLAG_AN(REG(rx)); // AZ & AV - cpustate->astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; - cpustate->astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; + m_astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; } // AF - cpustate->astat |= AF; + m_astat |= AF; REG(rn) = r; } /* Fn = RSQRTS Fx */ -INLINE void compute_rsqrts(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_rsqrts(int rn, int rx) { // verified UINT32 r; @@ -842,62 +842,62 @@ INLINE void compute_rsqrts(SHARC_REGS *cpustate, int rn, int rx) CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= (REG(rx) == 0x80000000) ? AN : 0; + m_astat |= (REG(rx) == 0x80000000) ? AN : 0; // AZ & AV - cpustate->astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; - cpustate->astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; + m_astat |= (IS_FLOAT_ZERO(r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(REG(rx))) ? AV : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || (REG(rx) & 0x80000000)) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || (REG(rx) & 0x80000000)) ? AI : 0; // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; // AF - cpustate->astat |= AF; + m_astat |= AF; REG(rn) = r; } /* Fn = PASS Fx */ -INLINE void compute_fpass(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_fpass(int rn, int rx) { SHARC_REG r; r.f = FREG(rx); CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= (r.f < 0.0f) ? AN : 0; + m_astat |= (r.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; FREG(rn) = r.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fn = ABS Fx */ -INLINE void compute_fabs(SHARC_REGS *cpustate, int rn, int rx) +void adsp21062_device::compute_fabs(int rn, int rx) { SHARC_REG r; r.f = fabs(FREG(rx)); CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= (r.f < 0.0f) ? AN : 0; + m_astat |= (r.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r.r)) ? AZ : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx))) ? AI : 0; FREG(rn) = r.f; - cpustate->astat |= AF; + m_astat |= AF; } /*****************************************************************************/ /* Multiplier opcodes */ /* Rn = (unsigned)Rx * (unsigned)Ry, integer, no rounding */ -INLINE void compute_mul_uuin(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_mul_uuin(int rn, int rx, int ry) { UINT64 r = (UINT64)(UINT32)REG(rx) * (UINT64)(UINT32)REG(ry); @@ -910,7 +910,7 @@ INLINE void compute_mul_uuin(SHARC_REGS *cpustate, int rn, int rx, int ry) } /* Rn = (signed)Rx * (signed)Ry, integer, no rounding */ -INLINE void compute_mul_ssin(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_mul_ssin(int rn, int rx, int ry) { UINT64 r = (INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry); @@ -923,9 +923,9 @@ INLINE void compute_mul_ssin(SHARC_REGS *cpustate, int rn, int rx, int ry) } /* MRF + (signed)Rx * (signed)Ry, integer, no rounding */ -INLINE UINT32 compute_mrf_plus_mul_ssin(SHARC_REGS *cpustate, int rx, int ry) +UINT32 adsp21062_device::compute_mrf_plus_mul_ssin(int rx, int ry) { - UINT64 r = cpustate->mrf + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); + UINT64 r = m_mrf + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); CLEAR_MULTIPLIER_FLAGS(); SET_FLAG_MN((UINT32)r); @@ -936,9 +936,9 @@ INLINE UINT32 compute_mrf_plus_mul_ssin(SHARC_REGS *cpustate, int rx, int ry) } /* MRB + (signed)Rx * (signed)Ry, integer, no rounding */ -INLINE UINT32 compute_mrb_plus_mul_ssin(SHARC_REGS *cpustate, int rx, int ry) +UINT32 adsp21062_device::compute_mrb_plus_mul_ssin(int rx, int ry) { - INT64 r = cpustate->mrb + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); + INT64 r = m_mrb + ((INT64)(INT32)REG(rx) * (INT64)(INT32)REG(ry)); CLEAR_MULTIPLIER_FLAGS(); SET_FLAG_MN((UINT32)r); @@ -949,7 +949,7 @@ INLINE UINT32 compute_mrb_plus_mul_ssin(SHARC_REGS *cpustate, int rx, int ry) } /* Fn = Fx * Fy */ -INLINE void compute_fmul(SHARC_REGS *cpustate, int rn, int rx, int ry) +void adsp21062_device::compute_fmul(int rn, int rx, int ry) { FREG(rn) = FREG(rx) * FREG(ry); @@ -965,15 +965,15 @@ INLINE void compute_fmul(SHARC_REGS *cpustate, int rn, int rx, int ry) /* multi function opcodes */ /* integer*/ -INLINE void compute_multi_mr_to_reg(SHARC_REGS *cpustate, int ai, int rk) +void adsp21062_device::compute_multi_mr_to_reg(int ai, int rk) { switch(ai) { - case 0: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf)); break; - case 1: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrf >> 32)); break; + case 0: SET_UREG(rk, (UINT32)(m_mrf)); break; + case 1: SET_UREG(rk, (UINT32)(m_mrf >> 32)); break; case 2: fatalerror("SHARC: tried to load MR2F\n"); break; - case 4: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb)); break; - case 5: SET_UREG(cpustate, rk, (UINT32)(cpustate->mrb >> 32)); break; + case 4: SET_UREG(rk, (UINT32)(m_mrb)); break; + case 5: SET_UREG(rk, (UINT32)(m_mrb >> 32)); break; case 6: fatalerror("SHARC: tried to load MR2B\n"); break; default: fatalerror("SHARC: unknown ai %d in mr_to_reg\n", ai); } @@ -981,15 +981,15 @@ INLINE void compute_multi_mr_to_reg(SHARC_REGS *cpustate, int ai, int rk) CLEAR_MULTIPLIER_FLAGS(); } -INLINE void compute_multi_reg_to_mr(SHARC_REGS *cpustate, int ai, int rk) +void adsp21062_device::compute_multi_reg_to_mr(int ai, int rk) { switch(ai) { - case 0: cpustate->mrf &= ~0xffffffff; cpustate->mrf |= GET_UREG(cpustate, rk); break; - case 1: cpustate->mrf &= 0xffffffff; cpustate->mrf |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break; + case 0: m_mrf &= ~0xffffffff; m_mrf |= GET_UREG(rk); break; + case 1: m_mrf &= 0xffffffff; m_mrf |= (UINT64)(GET_UREG(rk)) << 32; break; case 2: fatalerror("SHARC: tried to write MR2F\n"); break; - case 4: cpustate->mrb &= ~0xffffffff; cpustate->mrb |= GET_UREG(cpustate, rk); break; - case 5: cpustate->mrb &= 0xffffffff; cpustate->mrb |= (UINT64)(GET_UREG(cpustate, rk)) << 32; break; + case 4: m_mrb &= ~0xffffffff; m_mrb |= GET_UREG(rk); break; + case 5: m_mrb &= 0xffffffff; m_mrb |= (UINT64)(GET_UREG(rk)) << 32; break; case 6: fatalerror("SHARC: tried to write MR2B\n"); break; default: fatalerror("SHARC: unknown ai %d in reg_to_mr\n", ai); } @@ -998,7 +998,7 @@ INLINE void compute_multi_reg_to_mr(SHARC_REGS *cpustate, int ai, int rk) } /* Ra = Rx + Ry, Rs = Rx - Ry */ -INLINE void compute_dual_add_sub(SHARC_REGS *cpustate, int ra, int rs, int rx, int ry) +void adsp21062_device::compute_dual_add_sub(int ra, int rs, int rx, int ry) { UINT32 r_add = REG(rx) + REG(ry); UINT32 r_sub = REG(rx) - REG(ry); @@ -1006,31 +1006,31 @@ INLINE void compute_dual_add_sub(SHARC_REGS *cpustate, int ra, int rs, int rx, i CLEAR_ALU_FLAGS(); if (r_add == 0 || r_sub == 0) { - cpustate->astat |= AZ; + m_astat |= AZ; } if (r_add & 0x80000000 || r_sub & 0x80000000) { - cpustate->astat |= AN; + m_astat |= AN; } if (((~(REG(rx) ^ REG(ry)) & (REG(rx) ^ r_add)) & 0x80000000) || (( (REG(rx) ^ REG(ry)) & (REG(rx) ^ r_sub)) & 0x80000000)) { - cpustate->astat |= AV; + m_astat |= AV; } if (((UINT32)r_add < (UINT32)REG(rx)) || (!((UINT32)r_sub < (UINT32)REG(rx)))) { - cpustate->astat |= AC; + m_astat |= AC; } REG(ra) = r_add; REG(rs) = r_sub; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rm = (signed)Rxm * (signed)Rym, fractional, rounding, Ra = Rxa + Rya */ -INLINE void compute_mul_ssfr_add(SHARC_REGS *cpustate, int rm, int rxm, int rym, int ra, int rxa, int rya) +void adsp21062_device::compute_mul_ssfr_add(int rm, int rxm, int rym, int ra, int rxa, int rya) { UINT32 r_mul = (UINT32)(((INT64)(REG(rxm)) * (INT64)(REG(rym))) >> 31); UINT32 r_add = REG(rxa) + REG(rya); @@ -1051,11 +1051,11 @@ INLINE void compute_mul_ssfr_add(SHARC_REGS *cpustate, int rm, int rxm, int rym, REG(rm) = r_mul; REG(ra) = r_add; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* Rm = (signed)Rxm * (signed)Rym, fractional, rounding, Ra = Rxa - Rya */ -INLINE void compute_mul_ssfr_sub(SHARC_REGS *cpustate, int rm, int rxm, int rym, int ra, int rxa, int rya) +void adsp21062_device::compute_mul_ssfr_sub(int rm, int rxm, int rym, int ra, int rxa, int rya) { UINT32 r_mul = (UINT32)(((INT64)(REG(rxm)) * (INT64)(REG(rym))) >> 31); UINT32 r_sub = REG(rxa) - REG(rya); @@ -1076,14 +1076,14 @@ INLINE void compute_mul_ssfr_sub(SHARC_REGS *cpustate, int rm, int rxm, int rym, REG(rm) = r_mul; REG(ra) = r_sub; - cpustate->astat &= ~AF; + m_astat &= ~AF; } /* floating-point */ /* Fa = Fx + Fy, Fs = Fx - Fy */ -INLINE void compute_dual_fadd_fsub(SHARC_REGS *cpustate, int ra, int rs, int rx, int ry) +void adsp21062_device::compute_dual_fadd_fsub(int ra, int rs, int rx, int ry) { SHARC_REG r_add, r_sub; r_add.f = FREG(rx) + FREG(ry); @@ -1091,26 +1091,26 @@ INLINE void compute_dual_fadd_fsub(SHARC_REGS *cpustate, int ra, int rs, int rx, CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= ((r_add.f < 0.0f) || (r_sub.f < 0.0f)) ? AN : 0; + m_astat |= ((r_add.f < 0.0f) || (r_sub.f < 0.0f)) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || + m_astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(rx)) || IS_FLOAT_NAN(REG(ry))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(ra) = r_add.f; FREG(rs) = r_sub.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = Fxa + Fya */ -INLINE void compute_fmul_fadd(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) +void adsp21062_device::compute_fmul_fadd(int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_add; r_mul.f = FREG(fxm) * FREG(fym); @@ -1123,25 +1123,25 @@ INLINE void compute_fmul_fadd(SHARC_REGS *cpustate, int fm, int fxm, int fym, in /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_add.f < 0.0f) ? AN : 0; + m_astat |= (r_add.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_add.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_add.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(fm) = r_mul.f; FREG(fa) = r_add.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = Fxa - Fya */ -INLINE void compute_fmul_fsub(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) +void adsp21062_device::compute_fmul_fsub(int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_sub; r_mul.f = FREG(fxm) * FREG(fym); @@ -1154,25 +1154,25 @@ INLINE void compute_fmul_fsub(SHARC_REGS *cpustate, int fm, int fxm, int fym, in /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_sub.f < 0.0f) ? AN : 0; + m_astat |= (r_sub.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(fm) = r_mul.f; FREG(fa) = r_sub.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = FLOAT Fxa BY Fya */ -INLINE void compute_fmul_float_scaled(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) +void adsp21062_device::compute_fmul_float_scaled(int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG x; SHARC_REG r_mul, r_alu; @@ -1180,7 +1180,7 @@ INLINE void compute_fmul_float_scaled(SHARC_REGS *cpustate, int fm, int fxm, int x.f = (float)(INT32)REG(fxa); - r_alu.r = SCALB(cpustate, x, fya); + r_alu.r = SCALB(x, fya); CLEAR_MULTIPLIER_FLAGS(); SET_FLAG_MN(r_mul.r); @@ -1189,28 +1189,28 @@ INLINE void compute_fmul_float_scaled(SHARC_REGS *cpustate, int fm, int fxm, int /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; + m_astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r_alu.r) || IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_DENORMAL(r_alu.r) || IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; /* TODO: set AV if overflowed */ FREG(fm) = r_mul.f; FREG(fa) = r_alu.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = FIX Fxa BY Fya */ -INLINE void compute_fmul_fix_scaled(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) +void adsp21062_device::compute_fmul_fix_scaled(int fm, int fxm, int fym, int fa, int fxa, int fya) { INT32 alu_i; SHARC_REG r_mul, r_alu; r_mul.f = FREG(fxm) * FREG(fym); - r_alu.r = SCALB(cpustate, cpustate->r[fxa], fya); + r_alu.r = SCALB(m_r[fxa], fya); - if (cpustate->mode1 & MODE1_TRUNCATE) + if (m_mode1 & MODE1_TRUNCATE) { alu_i = (INT32)(r_alu.f); } @@ -1230,19 +1230,19 @@ INLINE void compute_fmul_fix_scaled(SHARC_REGS *cpustate, int fm, int fxm, int f // AZ SET_FLAG_AZ(alu_i); // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(fxa))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(fxa))) ? AI : 0; /* TODO: AV flag */ FREG(fm) = r_mul.f; REG(fa) = alu_i; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = MAX(Fxa, Fya) */ -INLINE void compute_fmul_fmax(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) +void adsp21062_device::compute_fmul_fmax(int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_alu; r_mul.f = FREG(fxm) * FREG(fym); @@ -1256,23 +1256,23 @@ INLINE void compute_fmul_fmax(SHARC_REGS *cpustate, int fm, int fxm, int fym, in /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; + m_astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ FREG(fm) = r_mul.f; FREG(fa) = r_alu.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = MIN(Fxa, Fya) */ -INLINE void compute_fmul_fmin(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fxa, int fya) +void adsp21062_device::compute_fmul_fmin(int fm, int fxm, int fym, int fa, int fxa, int fya) { SHARC_REG r_mul, r_alu; r_mul.f = FREG(fxm) * FREG(fym); @@ -1286,24 +1286,24 @@ INLINE void compute_fmul_fmin(SHARC_REGS *cpustate, int fm, int fxm, int fym, in /* TODO: MI flag */ CLEAR_ALU_FLAGS(); - cpustate->astat |= (r_alu.f < 0.0f) ? AN : 0; + m_astat |= (r_alu.f < 0.0f) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; + m_astat |= (IS_FLOAT_ZERO(r_alu.r)) ? AZ : 0; // AU - cpustate->stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_alu.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ FREG(fm) = r_mul.f; FREG(fa) = r_alu.f; - cpustate->astat |= AF; + m_astat |= AF; } /* Fm = Fxm * Fym, Fa = Fxa + Fya, Fs = Fxa - Fya */ -INLINE void compute_fmul_dual_fadd_fsub(SHARC_REGS *cpustate, int fm, int fxm, int fym, int fa, int fs, int fxa, int fya) +void adsp21062_device::compute_fmul_dual_fadd_fsub(int fm, int fxm, int fym, int fa, int fs, int fxa, int fya) { SHARC_REG r_mul, r_add, r_sub; r_mul.f = FREG(fxm) * FREG(fym); @@ -1318,21 +1318,21 @@ INLINE void compute_fmul_dual_fadd_fsub(SHARC_REGS *cpustate, int fm, int fxm, i CLEAR_ALU_FLAGS(); // AN - cpustate->astat |= ((r_add.r < 0.0f) || (r_sub.r < 0.0f)) ? AN : 0; + m_astat |= ((r_add.r < 0.0f) || (r_sub.r < 0.0f)) ? AN : 0; // AZ - cpustate->astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || + m_astat |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_ZERO(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r) || IS_FLOAT_ZERO(r_sub.r)) ? AZ : 0; // AUS - cpustate->stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; + m_stky |= (IS_FLOAT_DENORMAL(r_add.r) || IS_FLOAT_DENORMAL(r_sub.r)) ? AUS : 0; // AI - cpustate->astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; + m_astat |= (IS_FLOAT_NAN(REG(fxa)) || IS_FLOAT_NAN(REG(fya))) ? AI : 0; /* TODO: AV flag */ // AIS - if (cpustate->astat & AI) cpustate->stky |= AIS; + if (m_astat & AI) m_stky |= AIS; FREG(fm) = r_mul.f; FREG(fa) = r_add.f; FREG(fs) = r_sub.f; - cpustate->astat |= AF; + m_astat |= AF; } diff --git a/src/emu/cpu/sharc/sharc.c b/src/emu/cpu/sharc/sharc.c index defd40778bf..3e68d1ce186 100644 --- a/src/emu/cpu/sharc/sharc.c +++ b/src/emu/cpu/sharc/sharc.c @@ -7,7 +7,6 @@ #include "debugger.h" #include "sharc.h" -CPU_DISASSEMBLE( sharc ); enum { @@ -39,225 +38,92 @@ enum SHARC_B12, SHARC_B13, SHARC_B14, SHARC_B15, }; -struct SHARC_DAG + +#define ROPCODE(pc) ((UINT64)(m_internal_ram[((pc-0x20000) * 3) + 0]) << 32) | \ + ((UINT64)(m_internal_ram[((pc-0x20000) * 3) + 1]) << 16) | \ + ((UINT64)(m_internal_ram[((pc-0x20000) * 3) + 2]) << 0) + + +const device_type ADSP21062 = &device_creator; + + +// This is just used to stop the debugger from complaining about executing from I/O space +static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 64, adsp21062_device ) + AM_RANGE(0x20000, 0x7ffff) AM_RAM +ADDRESS_MAP_END + + +adsp21062_device::adsp21062_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : cpu_device(mconfig, ADSP21062, "ADSP21062", tag, owner, clock, "adsp21062", __FILE__) + , m_program_config("program", ENDIANNESS_LITTLE, 64, 24, -3, ADDRESS_MAP_NAME(internal_pgm)) + , m_data_config("data", ENDIANNESS_LITTLE, 32, 32, -2) + , m_boot_mode(BOOT_MODE_HOST) { - UINT32 i[8]; - UINT32 m[8]; - UINT32 b[8]; - UINT32 l[8]; -}; - -union SHARC_REG -{ - INT32 r; - float f; -}; - -struct DMA_REGS -{ - UINT32 control; - UINT32 int_index; - UINT32 int_modifier; - UINT32 int_count; - UINT32 chain_ptr; - UINT32 gen_purpose; - UINT32 ext_index; - UINT32 ext_modifier; - UINT32 ext_count; -}; - -struct LADDR -{ - UINT32 addr; - UINT32 code; - UINT32 loop_type; -}; - -struct DMA_OP -{ - UINT32 src; - UINT32 dst; - UINT32 chain_ptr; - INT32 src_modifier; - INT32 dst_modifier; - INT32 src_count; - INT32 dst_count; - INT32 pmode; - INT32 chained_direction; - emu_timer *timer; - bool active; -}; - -struct SHARC_REGS -{ - UINT32 pc; - SHARC_REG r[16]; - SHARC_REG reg_alt[16]; - UINT64 mrf; - UINT64 mrb; - - UINT32 pcstack[32]; - UINT32 lcstack[6]; - UINT32 lastack[6]; - UINT32 lstkp; - - UINT32 faddr; - UINT32 daddr; - UINT32 pcstk; - UINT32 pcstkp; - LADDR laddr; - UINT32 curlcntr; - UINT32 lcntr; - - /* Data Address Generator (DAG) */ - SHARC_DAG dag1; // (DM bus) - SHARC_DAG dag2; // (PM bus) - SHARC_DAG dag1_alt; - SHARC_DAG dag2_alt; - - DMA_REGS dma[12]; - - /* System registers */ - UINT32 mode1; - UINT32 mode2; - UINT32 astat; - UINT32 stky; - UINT32 irptl; - UINT32 imask; - UINT32 imaskp; - UINT32 ustat1; - UINT32 ustat2; - - UINT32 flag[4]; - - UINT32 syscon; - UINT32 sysstat; - - struct - { - UINT32 mode1; - UINT32 astat; - } status_stack[5]; - INT32 status_stkp; - - UINT64 px; - - UINT16 *internal_ram; - UINT16 *internal_ram_block0, *internal_ram_block1; - - device_irq_acknowledge_callback irq_callback; - legacy_cpu_device *device; - address_space *program; - address_space *data; - void (*opcode_handler)(SHARC_REGS *cpustate); - int icount; - UINT64 opcode; - - UINT32 nfaddr; - - INT32 idle; - INT32 irq_active; - INT32 active_irq_num; - - SHARC_BOOT_MODE boot_mode; - - DMA_OP dma_op[12]; - UINT32 dma_status; - - INT32 interrupt_active; - - UINT32 iop_delayed_reg; - UINT32 iop_delayed_data; - emu_timer *delayed_iop_timer; - - UINT32 delay_slot1, delay_slot2; - - INT32 systemreg_latency_cycles; - INT32 systemreg_latency_reg; - UINT32 systemreg_latency_data; - UINT32 systemreg_previous_data; - - UINT32 astat_old; - UINT32 astat_old_old; - UINT32 astat_old_old_old; -}; - - -static void sharc_dma_exec(SHARC_REGS *cpustate, int channel); -static void check_interrupts(SHARC_REGS *cpustate); - -static void (* sharc_op[512])(SHARC_REGS *cpustate); - - - -#define ROPCODE(pc) ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 0]) << 32) | \ - ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 1]) << 16) | \ - ((UINT64)(cpustate->internal_ram[((pc-0x20000) * 3) + 2]) << 0) - -INLINE SHARC_REGS *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == ADSP21062); - return (SHARC_REGS *)downcast(device)->token(); } -INLINE void CHANGE_PC(SHARC_REGS *cpustate, UINT32 newpc) + +offs_t adsp21062_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) { - cpustate->pc = newpc; - cpustate->daddr = newpc; - cpustate->faddr = newpc+1; - cpustate->nfaddr = newpc+2; + extern CPU_DISASSEMBLE( sharc ); + return CPU_DISASSEMBLE_NAME(sharc)(this, buffer, pc, oprom, opram, options); } -INLINE void CHANGE_PC_DELAYED(SHARC_REGS *cpustate, UINT32 newpc) -{ - cpustate->nfaddr = newpc; - cpustate->delay_slot1 = cpustate->pc; - cpustate->delay_slot2 = cpustate->daddr; +void adsp21062_device::CHANGE_PC(UINT32 newpc) +{ + m_pc = newpc; + m_daddr = newpc; + m_faddr = newpc+1; + m_nfaddr = newpc+2; } -static TIMER_CALLBACK(sharc_iop_delayed_write_callback) +void adsp21062_device::CHANGE_PC_DELAYED(UINT32 newpc) { - SHARC_REGS *cpustate = (SHARC_REGS *)ptr; + m_nfaddr = newpc; - switch (cpustate->iop_delayed_reg) + m_delay_slot1 = m_pc; + m_delay_slot2 = m_daddr; +} + +TIMER_CALLBACK_MEMBER(adsp21062_device::sharc_iop_delayed_write_callback) +{ + switch (m_iop_delayed_reg) { case 0x1c: { - if (cpustate->iop_delayed_data & 0x1) + if (m_iop_delayed_data & 0x1) { - sharc_dma_exec(cpustate, 6); + sharc_dma_exec(6); } break; } case 0x1d: { - if (cpustate->iop_delayed_data & 0x1) + if (m_iop_delayed_data & 0x1) { - sharc_dma_exec(cpustate, 7); + sharc_dma_exec(7); } break; } - default: fatalerror("SHARC: sharc_iop_delayed_write: unknown IOP register %02X\n", cpustate->iop_delayed_reg); + default: fatalerror("SHARC: sharc_iop_delayed_write: unknown IOP register %02X\n", m_iop_delayed_reg); } - cpustate->delayed_iop_timer->adjust(attotime::never, 0); + m_delayed_iop_timer->adjust(attotime::never, 0); } -static void sharc_iop_delayed_w(SHARC_REGS *cpustate, UINT32 reg, UINT32 data, int cycles) +void adsp21062_device::sharc_iop_delayed_w(UINT32 reg, UINT32 data, int cycles) { - cpustate->iop_delayed_reg = reg; - cpustate->iop_delayed_data = data; + m_iop_delayed_reg = reg; + m_iop_delayed_data = data; - cpustate->delayed_iop_timer->adjust(cpustate->device->cycles_to_attotime(cycles), 0); + m_delayed_iop_timer->adjust(cycles_to_attotime(cycles), 0); } /* IOP registers */ -static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address) +UINT32 adsp21062_device::sharc_iop_r(UINT32 address) { switch (address) { @@ -265,14 +131,14 @@ static UINT32 sharc_iop_r(SHARC_REGS *cpustate, UINT32 address) case 0x37: // DMA status { - return cpustate->dma_status; + return m_dma_status; } - default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, cpustate->pc); + default: fatalerror("sharc_iop_r: Unimplemented IOP reg %02X at %08X\n", address, m_pc); } return 0; } -static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data) +void adsp21062_device::sharc_iop_w(UINT32 address, UINT32 data) { switch (address) { @@ -291,40 +157,40 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data) // DMA 6 case 0x1c: { - cpustate->dma[6].control = data; - sharc_iop_delayed_w(cpustate, 0x1c, data, 1); + m_dma[6].control = data; + sharc_iop_delayed_w(0x1c, data, 1); break; } case 0x20: break; - case 0x40: cpustate->dma[6].int_index = data; return; - case 0x41: cpustate->dma[6].int_modifier = data; return; - case 0x42: cpustate->dma[6].int_count = data; return; - case 0x43: cpustate->dma[6].chain_ptr = data; return; - case 0x44: cpustate->dma[6].gen_purpose = data; return; - case 0x45: cpustate->dma[6].ext_index = data; return; - case 0x46: cpustate->dma[6].ext_modifier = data; return; - case 0x47: cpustate->dma[6].ext_count = data; return; + case 0x40: m_dma[6].int_index = data; return; + case 0x41: m_dma[6].int_modifier = data; return; + case 0x42: m_dma[6].int_count = data; return; + case 0x43: m_dma[6].chain_ptr = data; return; + case 0x44: m_dma[6].gen_purpose = data; return; + case 0x45: m_dma[6].ext_index = data; return; + case 0x46: m_dma[6].ext_modifier = data; return; + case 0x47: m_dma[6].ext_count = data; return; // DMA 7 case 0x1d: { - cpustate->dma[7].control = data; - sharc_iop_delayed_w(cpustate, 0x1d, data, 30); + m_dma[7].control = data; + sharc_iop_delayed_w(0x1d, data, 30); break; } - case 0x48: cpustate->dma[7].int_index = data; return; - case 0x49: cpustate->dma[7].int_modifier = data; return; - case 0x4a: cpustate->dma[7].int_count = data; return; - case 0x4b: cpustate->dma[7].chain_ptr = data; return; - case 0x4c: cpustate->dma[7].gen_purpose = data; return; - case 0x4d: cpustate->dma[7].ext_index = data; return; - case 0x4e: cpustate->dma[7].ext_modifier = data; return; - case 0x4f: cpustate->dma[7].ext_count = data; return; + case 0x48: m_dma[7].int_index = data; return; + case 0x49: m_dma[7].int_modifier = data; return; + case 0x4a: m_dma[7].int_count = data; return; + case 0x4b: m_dma[7].chain_ptr = data; return; + case 0x4c: m_dma[7].gen_purpose = data; return; + case 0x4d: m_dma[7].ext_index = data; return; + case 0x4e: m_dma[7].ext_modifier = data; return; + case 0x4f: m_dma[7].ext_count = data; return; - default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X\n", address, data, cpustate->pc); + default: fatalerror("sharc_iop_w: Unimplemented IOP reg %02X, %08X at %08X\n", address, data, m_pc); } } @@ -336,14 +202,14 @@ static void sharc_iop_w(SHARC_REGS *cpustate, UINT32 address, UINT32 data) -static void build_opcode_table(void) +void adsp21062_device::build_opcode_table() { int i, j; - int num_ops = sizeof(sharc_opcode_table) / sizeof(SHARC_OP); + int num_ops = sizeof(s_sharc_opcode_table) / sizeof(SHARC_OP); for (i=0; i < 512; i++) { - sharc_op[i] = sharcop_unimplemented; + m_sharc_op[i] = &adsp21062_device::sharcop_unimplemented; } for (i=0; i < 512; i++) @@ -352,15 +218,15 @@ static void build_opcode_table(void) for (j=0; j < num_ops; j++) { - if ((sharc_opcode_table[j].op_mask & op) == sharc_opcode_table[j].op_bits) + if ((s_sharc_opcode_table[j].op_mask & op) == s_sharc_opcode_table[j].op_bits) { - if (sharc_op[i] != sharcop_unimplemented) + if (m_sharc_op[i] != &adsp21062_device::sharcop_unimplemented) { fatalerror("build_opcode_table: table already filled! (i=%04X, j=%d)\n", i, j); } else { - sharc_op[i] = sharc_opcode_table[j].handler; + m_sharc_op[i] = s_sharc_opcode_table[j].handler; } } } @@ -369,218 +235,397 @@ static void build_opcode_table(void) /*****************************************************************************/ -void sharc_external_iop_write(device_t *device, UINT32 address, UINT32 data) +void adsp21062_device::external_iop_write(UINT32 address, UINT32 data) { - SHARC_REGS *cpustate = get_safe_token(device); if (address == 0x1c) { if (data != 0) { - cpustate->dma[6].control = data; + m_dma[6].control = data; } } else { mame_printf_debug("SHARC IOP write %08X, %08X\n", address, data); - sharc_iop_w(cpustate, address, data); + sharc_iop_w(address, data); } } -void sharc_external_dma_write(device_t *device, UINT32 address, UINT64 data) +void adsp21062_device::external_dma_write(UINT32 address, UINT64 data) { - SHARC_REGS *cpustate = get_safe_token(device); - switch ((cpustate->dma[6].control >> 6) & 0x3) + switch ((m_dma[6].control >> 6) & 0x3) { case 2: // 16/48 packing { int shift = address % 3; - UINT64 r = pm_read48(cpustate, cpustate->dma[6].int_index); + UINT64 r = pm_read48(m_dma[6].int_index); r &= ~((UINT64)(0xffff) << (shift*16)); r |= (data & 0xffff) << (shift*16); - pm_write48(cpustate, cpustate->dma[6].int_index, r); + pm_write48(m_dma[6].int_index, r); if (shift == 2) { - cpustate->dma[6].int_index += cpustate->dma[6].int_modifier; + m_dma[6].int_index += m_dma[6].int_modifier; } break; } default: { - fatalerror("sharc_external_dma_write: unimplemented packing mode %d\n", (cpustate->dma[6].control >> 6) & 0x3); + fatalerror("sharc_external_dma_write: unimplemented packing mode %d\n", (m_dma[6].control >> 6) & 0x3); } } } -static CPU_INIT( sharc ) +void adsp21062_device::device_start() { - SHARC_REGS *cpustate = get_safe_token(device); - const sharc_config *cfg = (const sharc_config *)device->static_config(); int saveindex; - cpustate->boot_mode = cfg->boot_mode; - - cpustate->irq_callback = irqcallback; - cpustate->device = device; - cpustate->program = &device->space(AS_PROGRAM); - cpustate->data = &device->space(AS_DATA); + m_program = &space(AS_PROGRAM); + m_data = &space(AS_DATA); build_opcode_table(); - cpustate->internal_ram = auto_alloc_array(device->machine(), UINT16, 2 * 0x10000); // 2x 128KB - cpustate->internal_ram_block0 = &cpustate->internal_ram[0]; - cpustate->internal_ram_block1 = &cpustate->internal_ram[0x20000/2]; + m_internal_ram = auto_alloc_array(machine(), UINT16, 2 * 0x10000); // 2x 128KB + m_internal_ram_block0 = &m_internal_ram[0]; + m_internal_ram_block1 = &m_internal_ram[0x20000/2]; - cpustate->delayed_iop_timer = device->machine().scheduler().timer_alloc(FUNC(sharc_iop_delayed_write_callback), cpustate); + m_delayed_iop_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(adsp21062_device::sharc_iop_delayed_write_callback), this)); for (int i=0; i < 12; i++) { - cpustate->dma_op[i].active = false; - cpustate->dma_op[i].timer = device->machine().scheduler().timer_alloc(FUNC(sharc_dma_callback), cpustate); + m_dma_op[i].src = 0; + m_dma_op[i].dst = 0; + m_dma_op[i].chain_ptr = 0; + m_dma_op[i].src_modifier = 0; + m_dma_op[i].dst_modifier = 0; + m_dma_op[i].src_count = 0; + m_dma_op[i].dst_count = 0; + m_dma_op[i].pmode = 0; + m_dma_op[i].chained_direction = 0; + m_dma_op[i].active = false; + m_dma_op[i].timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(adsp21062_device::sharc_dma_callback), this)); } - device->save_item(NAME(cpustate->pc)); - device->save_pointer(NAME(&cpustate->r[0].r), ARRAY_LENGTH(cpustate->r)); - device->save_pointer(NAME(&cpustate->reg_alt[0].r), ARRAY_LENGTH(cpustate->reg_alt)); - device->save_item(NAME(cpustate->mrf)); - device->save_item(NAME(cpustate->mrb)); - - device->save_item(NAME(cpustate->pcstack)); - device->save_item(NAME(cpustate->lcstack)); - device->save_item(NAME(cpustate->lastack)); - device->save_item(NAME(cpustate->lstkp)); - - device->save_item(NAME(cpustate->faddr)); - device->save_item(NAME(cpustate->daddr)); - device->save_item(NAME(cpustate->pcstk)); - device->save_item(NAME(cpustate->pcstkp)); - device->save_item(NAME(cpustate->laddr.addr)); - device->save_item(NAME(cpustate->laddr.code)); - device->save_item(NAME(cpustate->laddr.loop_type)); - device->save_item(NAME(cpustate->curlcntr)); - device->save_item(NAME(cpustate->lcntr)); - - device->save_item(NAME(cpustate->dag1.i)); - device->save_item(NAME(cpustate->dag1.m)); - device->save_item(NAME(cpustate->dag1.b)); - device->save_item(NAME(cpustate->dag1.l)); - device->save_item(NAME(cpustate->dag2.i)); - device->save_item(NAME(cpustate->dag2.m)); - device->save_item(NAME(cpustate->dag2.b)); - device->save_item(NAME(cpustate->dag2.l)); - device->save_item(NAME(cpustate->dag1_alt.i)); - device->save_item(NAME(cpustate->dag1_alt.m)); - device->save_item(NAME(cpustate->dag1_alt.b)); - device->save_item(NAME(cpustate->dag1_alt.l)); - device->save_item(NAME(cpustate->dag2_alt.i)); - device->save_item(NAME(cpustate->dag2_alt.m)); - device->save_item(NAME(cpustate->dag2_alt.b)); - device->save_item(NAME(cpustate->dag2_alt.l)); - - for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->dma); saveindex++) + for (int i=0; i < 16; i++) { - device->save_item(NAME(cpustate->dma[saveindex].control), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].int_index), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].int_modifier), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].int_count), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].chain_ptr), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].gen_purpose), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].ext_index), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].ext_modifier), saveindex); - device->save_item(NAME(cpustate->dma[saveindex].ext_count), saveindex); + m_r[i].r = 0; + m_reg_alt[i].r = 0; } - - device->save_item(NAME(cpustate->mode1)); - device->save_item(NAME(cpustate->mode2)); - device->save_item(NAME(cpustate->astat)); - device->save_item(NAME(cpustate->stky)); - device->save_item(NAME(cpustate->irptl)); - device->save_item(NAME(cpustate->imask)); - device->save_item(NAME(cpustate->imaskp)); - device->save_item(NAME(cpustate->ustat1)); - device->save_item(NAME(cpustate->ustat2)); - - device->save_item(NAME(cpustate->flag)); - - device->save_item(NAME(cpustate->syscon)); - device->save_item(NAME(cpustate->sysstat)); - - for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->status_stack); saveindex++) + m_mrf = 0; + m_mrb = 0; + for (int i=0; i < 32; i++) { - device->save_item(NAME(cpustate->status_stack[saveindex].mode1), saveindex); - device->save_item(NAME(cpustate->status_stack[saveindex].astat), saveindex); + m_pcstack[i] = 0; } - device->save_item(NAME(cpustate->status_stkp)); - - device->save_item(NAME(cpustate->px)); - - device->save_pointer(NAME(cpustate->internal_ram), 2 * 0x10000); - - device->save_item(NAME(cpustate->opcode)); - - device->save_item(NAME(cpustate->nfaddr)); - - device->save_item(NAME(cpustate->idle)); - device->save_item(NAME(cpustate->irq_active)); - device->save_item(NAME(cpustate->active_irq_num)); - - for (saveindex = 0; saveindex < ARRAY_LENGTH(cpustate->dma_op); saveindex++) + for (int i=0; i < 6; i++) { - device->save_item(NAME(cpustate->dma_op[saveindex].src), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].dst), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].chain_ptr), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].src_modifier), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].dst_modifier), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].src_count), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].dst_count), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].pmode), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].chained_direction), saveindex); - device->save_item(NAME(cpustate->dma_op[saveindex].active), saveindex); + m_lcstack[i] = 0; + m_lastack[i] = 0; + } + m_lstkp = 0; + m_pcstk = 0; + m_pcstkp = 0; + m_laddr.addr = m_laddr.code = m_laddr.loop_type = 0; + m_curlcntr = 0; + m_lcntr = 0; + for (int i=0; i < 8; i++) + { + m_dag1.i[i] = m_dag1.m[i] = m_dag1.b[i] = m_dag1.l[i] = 0; + m_dag2.i[i] = m_dag2.m[i] = m_dag2.b[i] = m_dag2.l[i] = 0; + m_dag1_alt.i[i] = m_dag1_alt.m[i] = m_dag1_alt.b[i] = m_dag1_alt.l[i] = 0; + m_dag2_alt.i[i] = m_dag2_alt.m[i] = m_dag2_alt.b[i] = m_dag2_alt.l[i] = 0; + } + for (int i=0; i < 12; i++) + { + m_dma[i].control = 0; + m_dma[i].int_index = 0; + m_dma[i].int_modifier = 0; + m_dma[i].int_count = 0; + m_dma[i].chain_ptr = 0; + m_dma[i].gen_purpose = 0; + m_dma[i].ext_index = 0; + m_dma[i].ext_modifier = 0; + m_dma[i].ext_count = 0; + } + m_mode1 = 0; + m_mode2 = 0; + m_astat = 0; + m_irptl = 0; + m_imask = 0; + m_imaskp = 0; + m_ustat1 = 0; + m_ustat2 = 0; + m_flag[0] = m_flag[1] = m_flag[2] = m_flag[3] = 0; + m_syscon = 0; + m_sysstat = 0; + for (int i=0; i < 5; i++) + { + m_status_stack[i].mode1 = 0; + m_status_stack[i].astat = 0; + } + m_status_stkp = 0; + m_px = 0; + m_opcode = 0; + m_irq_active = 0; + m_active_irq_num = 0; + m_dma_status = 0; + m_iop_delayed_reg = 0; + m_iop_delayed_data = 0; + m_delay_slot1 = 0; + m_delay_slot2 = 0; + m_systemreg_latency_cycles = 0; + m_systemreg_latency_reg = 0; + m_systemreg_latency_data = 0; + m_systemreg_previous_data = 0; + m_astat_old = 0; + m_astat_old_old = 0; + m_astat_old_old_old = 0; + + save_item(NAME(m_pc)); + save_pointer(NAME(&m_r[0].r), ARRAY_LENGTH(m_r)); + save_pointer(NAME(&m_reg_alt[0].r), ARRAY_LENGTH(m_reg_alt)); + save_item(NAME(m_mrf)); + save_item(NAME(m_mrb)); + + save_item(NAME(m_pcstack)); + save_item(NAME(m_lcstack)); + save_item(NAME(m_lastack)); + save_item(NAME(m_lstkp)); + + save_item(NAME(m_faddr)); + save_item(NAME(m_daddr)); + save_item(NAME(m_pcstk)); + save_item(NAME(m_pcstkp)); + save_item(NAME(m_laddr.addr)); + save_item(NAME(m_laddr.code)); + save_item(NAME(m_laddr.loop_type)); + save_item(NAME(m_curlcntr)); + save_item(NAME(m_lcntr)); + + save_item(NAME(m_dag1.i)); + save_item(NAME(m_dag1.m)); + save_item(NAME(m_dag1.b)); + save_item(NAME(m_dag1.l)); + save_item(NAME(m_dag2.i)); + save_item(NAME(m_dag2.m)); + save_item(NAME(m_dag2.b)); + save_item(NAME(m_dag2.l)); + save_item(NAME(m_dag1_alt.i)); + save_item(NAME(m_dag1_alt.m)); + save_item(NAME(m_dag1_alt.b)); + save_item(NAME(m_dag1_alt.l)); + save_item(NAME(m_dag2_alt.i)); + save_item(NAME(m_dag2_alt.m)); + save_item(NAME(m_dag2_alt.b)); + save_item(NAME(m_dag2_alt.l)); + + for (saveindex = 0; saveindex < ARRAY_LENGTH(m_dma); saveindex++) + { + save_item(NAME(m_dma[saveindex].control), saveindex); + save_item(NAME(m_dma[saveindex].int_index), saveindex); + save_item(NAME(m_dma[saveindex].int_modifier), saveindex); + save_item(NAME(m_dma[saveindex].int_count), saveindex); + save_item(NAME(m_dma[saveindex].chain_ptr), saveindex); + save_item(NAME(m_dma[saveindex].gen_purpose), saveindex); + save_item(NAME(m_dma[saveindex].ext_index), saveindex); + save_item(NAME(m_dma[saveindex].ext_modifier), saveindex); + save_item(NAME(m_dma[saveindex].ext_count), saveindex); } - device->save_item(NAME(cpustate->dma_status)); + save_item(NAME(m_mode1)); + save_item(NAME(m_mode2)); + save_item(NAME(m_astat)); + save_item(NAME(m_stky)); + save_item(NAME(m_irptl)); + save_item(NAME(m_imask)); + save_item(NAME(m_imaskp)); + save_item(NAME(m_ustat1)); + save_item(NAME(m_ustat2)); - device->save_item(NAME(cpustate->interrupt_active)); + save_item(NAME(m_flag)); - device->save_item(NAME(cpustate->iop_delayed_reg)); - device->save_item(NAME(cpustate->iop_delayed_data)); + save_item(NAME(m_syscon)); + save_item(NAME(m_sysstat)); - device->save_item(NAME(cpustate->delay_slot1)); - device->save_item(NAME(cpustate->delay_slot2)); + for (saveindex = 0; saveindex < ARRAY_LENGTH(m_status_stack); saveindex++) + { + save_item(NAME(m_status_stack[saveindex].mode1), saveindex); + save_item(NAME(m_status_stack[saveindex].astat), saveindex); + } + save_item(NAME(m_status_stkp)); - device->save_item(NAME(cpustate->systemreg_latency_cycles)); - device->save_item(NAME(cpustate->systemreg_latency_reg)); - device->save_item(NAME(cpustate->systemreg_latency_data)); - device->save_item(NAME(cpustate->systemreg_previous_data)); + save_item(NAME(m_px)); - device->save_item(NAME(cpustate->astat_old)); - device->save_item(NAME(cpustate->astat_old_old)); - device->save_item(NAME(cpustate->astat_old_old_old)); + save_pointer(NAME(m_internal_ram), 2 * 0x10000); + + save_item(NAME(m_opcode)); + + save_item(NAME(m_nfaddr)); + + save_item(NAME(m_idle)); + save_item(NAME(m_irq_active)); + save_item(NAME(m_active_irq_num)); + + for (saveindex = 0; saveindex < ARRAY_LENGTH(m_dma_op); saveindex++) + { + save_item(NAME(m_dma_op[saveindex].src), saveindex); + save_item(NAME(m_dma_op[saveindex].dst), saveindex); + save_item(NAME(m_dma_op[saveindex].chain_ptr), saveindex); + save_item(NAME(m_dma_op[saveindex].src_modifier), saveindex); + save_item(NAME(m_dma_op[saveindex].dst_modifier), saveindex); + save_item(NAME(m_dma_op[saveindex].src_count), saveindex); + save_item(NAME(m_dma_op[saveindex].dst_count), saveindex); + save_item(NAME(m_dma_op[saveindex].pmode), saveindex); + save_item(NAME(m_dma_op[saveindex].chained_direction), saveindex); + save_item(NAME(m_dma_op[saveindex].active), saveindex); + } + + save_item(NAME(m_dma_status)); + + save_item(NAME(m_interrupt_active)); + + save_item(NAME(m_iop_delayed_reg)); + save_item(NAME(m_iop_delayed_data)); + + save_item(NAME(m_delay_slot1)); + save_item(NAME(m_delay_slot2)); + + save_item(NAME(m_systemreg_latency_cycles)); + save_item(NAME(m_systemreg_latency_reg)); + save_item(NAME(m_systemreg_latency_data)); + save_item(NAME(m_systemreg_previous_data)); + + save_item(NAME(m_astat_old)); + save_item(NAME(m_astat_old_old)); + save_item(NAME(m_astat_old_old_old)); + + state_add( SHARC_PC, "PC", m_pc).formatstr("%08X"); + state_add( SHARC_PCSTK, "PCSTK", m_pcstk).formatstr("%08X"); + state_add( SHARC_PCSTKP, "PCSTKP", m_pcstkp).formatstr("%08X"); + state_add( SHARC_LSTKP, "LSTKP", m_lstkp).formatstr("%08X"); + state_add( SHARC_FADDR, "FADDR", m_faddr).formatstr("%08X"); + state_add( SHARC_DADDR, "DADDR", m_daddr).formatstr("%08X"); + state_add( SHARC_MODE1, "MODE1", m_mode1).formatstr("%08X"); + state_add( SHARC_MODE2, "MODE2", m_mode2).formatstr("%08X"); + state_add( SHARC_ASTAT, "ASTAT", m_astat).formatstr("%08X"); + state_add( SHARC_IRPTL, "IRPTL", m_irptl).formatstr("%08X"); + state_add( SHARC_IMASK, "IMASK", m_imask).formatstr("%08X"); + state_add( SHARC_USTAT1, "USTAT1", m_ustat1).formatstr("%08X"); + state_add( SHARC_USTAT2, "USTAT2", m_ustat2).formatstr("%08X"); + state_add( SHARC_STSTKP, "STSTKP", m_status_stkp).formatstr("%08X"); + + state_add( SHARC_R0, "R0", m_r[0].r).formatstr("%08X"); + state_add( SHARC_R1, "R1", m_r[1].r).formatstr("%08X"); + state_add( SHARC_R2, "R2", m_r[2].r).formatstr("%08X"); + state_add( SHARC_R3, "R3", m_r[3].r).formatstr("%08X"); + state_add( SHARC_R4, "R4", m_r[4].r).formatstr("%08X"); + state_add( SHARC_R5, "R5", m_r[5].r).formatstr("%08X"); + state_add( SHARC_R6, "R6", m_r[6].r).formatstr("%08X"); + state_add( SHARC_R7, "R7", m_r[7].r).formatstr("%08X"); + state_add( SHARC_R8, "R8", m_r[8].r).formatstr("%08X"); + state_add( SHARC_R9, "R9", m_r[9].r).formatstr("%08X"); + state_add( SHARC_R10, "R10", m_r[10].r).formatstr("%08X"); + state_add( SHARC_R11, "R11", m_r[11].r).formatstr("%08X"); + state_add( SHARC_R12, "R12", m_r[12].r).formatstr("%08X"); + state_add( SHARC_R13, "R13", m_r[13].r).formatstr("%08X"); + state_add( SHARC_R14, "R14", m_r[14].r).formatstr("%08X"); + state_add( SHARC_R15, "R15", m_r[15].r).formatstr("%08X"); + + state_add( SHARC_I0, "I0", m_dag1.i[0]).formatstr("%08X"); + state_add( SHARC_I1, "I1", m_dag1.i[1]).formatstr("%08X"); + state_add( SHARC_I2, "I2", m_dag1.i[2]).formatstr("%08X"); + state_add( SHARC_I3, "I3", m_dag1.i[3]).formatstr("%08X"); + state_add( SHARC_I4, "I4", m_dag1.i[4]).formatstr("%08X"); + state_add( SHARC_I5, "I5", m_dag1.i[5]).formatstr("%08X"); + state_add( SHARC_I6, "I6", m_dag1.i[6]).formatstr("%08X"); + state_add( SHARC_I7, "I7", m_dag1.i[7]).formatstr("%08X"); + state_add( SHARC_I8, "I8", m_dag2.i[0]).formatstr("%08X"); + state_add( SHARC_I9, "I9", m_dag2.i[1]).formatstr("%08X"); + state_add( SHARC_I10, "I10", m_dag2.i[2]).formatstr("%08X"); + state_add( SHARC_I11, "I11", m_dag2.i[3]).formatstr("%08X"); + state_add( SHARC_I12, "I12", m_dag2.i[4]).formatstr("%08X"); + state_add( SHARC_I13, "I13", m_dag2.i[5]).formatstr("%08X"); + state_add( SHARC_I14, "I14", m_dag2.i[6]).formatstr("%08X"); + state_add( SHARC_I15, "I15", m_dag2.i[7]).formatstr("%08X"); + + state_add( SHARC_M0, "M0", m_dag1.m[0]).formatstr("%08X"); + state_add( SHARC_M1, "M1", m_dag1.m[1]).formatstr("%08X"); + state_add( SHARC_M2, "M2", m_dag1.m[2]).formatstr("%08X"); + state_add( SHARC_M3, "M3", m_dag1.m[3]).formatstr("%08X"); + state_add( SHARC_M4, "M4", m_dag1.m[4]).formatstr("%08X"); + state_add( SHARC_M5, "M5", m_dag1.m[5]).formatstr("%08X"); + state_add( SHARC_M6, "M6", m_dag1.m[6]).formatstr("%08X"); + state_add( SHARC_M7, "M7", m_dag1.m[7]).formatstr("%08X"); + state_add( SHARC_M8, "M8", m_dag2.m[0]).formatstr("%08X"); + state_add( SHARC_M9, "M9", m_dag2.m[1]).formatstr("%08X"); + state_add( SHARC_M10, "M10", m_dag2.m[2]).formatstr("%08X"); + state_add( SHARC_M11, "M11", m_dag2.m[3]).formatstr("%08X"); + state_add( SHARC_M12, "M12", m_dag2.m[4]).formatstr("%08X"); + state_add( SHARC_M13, "M13", m_dag2.m[5]).formatstr("%08X"); + state_add( SHARC_M14, "M14", m_dag2.m[6]).formatstr("%08X"); + state_add( SHARC_M15, "M15", m_dag2.m[7]).formatstr("%08X"); + + state_add( SHARC_L0, "L0", m_dag1.l[0]).formatstr("%08X"); + state_add( SHARC_L1, "L1", m_dag1.l[1]).formatstr("%08X"); + state_add( SHARC_L2, "L2", m_dag1.l[2]).formatstr("%08X"); + state_add( SHARC_L3, "L3", m_dag1.l[3]).formatstr("%08X"); + state_add( SHARC_L4, "L4", m_dag1.l[4]).formatstr("%08X"); + state_add( SHARC_L5, "L5", m_dag1.l[5]).formatstr("%08X"); + state_add( SHARC_L6, "L6", m_dag1.l[6]).formatstr("%08X"); + state_add( SHARC_L7, "L7", m_dag1.l[7]).formatstr("%08X"); + state_add( SHARC_L8, "L8", m_dag2.l[0]).formatstr("%08X"); + state_add( SHARC_L9, "L9", m_dag2.l[1]).formatstr("%08X"); + state_add( SHARC_L10, "L10", m_dag2.l[2]).formatstr("%08X"); + state_add( SHARC_L11, "L11", m_dag2.l[3]).formatstr("%08X"); + state_add( SHARC_L12, "L12", m_dag2.l[4]).formatstr("%08X"); + state_add( SHARC_L13, "L13", m_dag2.l[5]).formatstr("%08X"); + state_add( SHARC_L14, "L14", m_dag2.l[6]).formatstr("%08X"); + state_add( SHARC_L15, "L15", m_dag2.l[7]).formatstr("%08X"); + + state_add( SHARC_B0, "B0", m_dag1.b[0]).formatstr("%08X"); + state_add( SHARC_B1, "B1", m_dag1.b[1]).formatstr("%08X"); + state_add( SHARC_B2, "B2", m_dag1.b[2]).formatstr("%08X"); + state_add( SHARC_B3, "B3", m_dag1.b[3]).formatstr("%08X"); + state_add( SHARC_B4, "B4", m_dag1.b[4]).formatstr("%08X"); + state_add( SHARC_B5, "B5", m_dag1.b[5]).formatstr("%08X"); + state_add( SHARC_B6, "B6", m_dag1.b[6]).formatstr("%08X"); + state_add( SHARC_B7, "B7", m_dag1.b[7]).formatstr("%08X"); + state_add( SHARC_B8, "B8", m_dag2.b[0]).formatstr("%08X"); + state_add( SHARC_B9, "B9", m_dag2.b[1]).formatstr("%08X"); + state_add( SHARC_B10, "B10", m_dag2.b[2]).formatstr("%08X"); + state_add( SHARC_B11, "B11", m_dag2.b[3]).formatstr("%08X"); + state_add( SHARC_B12, "B12", m_dag2.b[4]).formatstr("%08X"); + state_add( SHARC_B13, "B13", m_dag2.b[5]).formatstr("%08X"); + state_add( SHARC_B14, "B14", m_dag2.b[6]).formatstr("%08X"); + state_add( SHARC_B15, "B15", m_dag2.b[7]).formatstr("%08X"); + + state_add( STATE_GENPC, "GENPC", m_pc).noshow(); + + m_icountptr = &m_icount; } -static CPU_RESET( sharc ) +void adsp21062_device::device_reset() { - SHARC_REGS *cpustate = get_safe_token(device); - memset(cpustate->internal_ram, 0, 2 * 0x10000 * sizeof(UINT16)); + memset(m_internal_ram, 0, 2 * 0x10000 * sizeof(UINT16)); - switch(cpustate->boot_mode) + switch(m_boot_mode) { case BOOT_MODE_EPROM: { - cpustate->dma[6].int_index = 0x20000; - cpustate->dma[6].int_modifier = 1; - cpustate->dma[6].int_count = 0x100; - cpustate->dma[6].ext_index = 0x400000; - cpustate->dma[6].ext_modifier = 1; - cpustate->dma[6].ext_count = 0x600; - cpustate->dma[6].control = 0x2a1; + m_dma[6].int_index = 0x20000; + m_dma[6].int_modifier = 1; + m_dma[6].int_count = 0x100; + m_dma[6].ext_index = 0x400000; + m_dma[6].ext_modifier = 1; + m_dma[6].ext_count = 0x600; + m_dma[6].control = 0x2a1; - sharc_dma_exec(cpustate, 6); - dma_op(cpustate, 6); + sharc_dma_exec(6); + dma_op(6); - cpustate->dma_op[6].timer->adjust(attotime::never, 0); + m_dma_op[6].timer->adjust(attotime::never, 0); break; } @@ -588,46 +633,48 @@ static CPU_RESET( sharc ) break; default: - fatalerror("SHARC: Unimplemented boot mode %d\n", cpustate->boot_mode); + fatalerror("SHARC: Unimplemented boot mode %d\n", m_boot_mode); } - cpustate->pc = 0x20004; - cpustate->daddr = cpustate->pc + 1; - cpustate->faddr = cpustate->daddr + 1; - cpustate->nfaddr = cpustate->faddr+1; + m_pc = 0x20004; + m_daddr = m_pc + 1; + m_faddr = m_daddr + 1; + m_nfaddr = m_faddr+1; - cpustate->idle = 0; - cpustate->stky = 0x5400000; + m_idle = 0; + m_stky = 0x5400000; - cpustate->interrupt_active = 0; + m_interrupt_active = 0; } -static CPU_EXIT( sharc ) -{ - /* TODO */ -} -static void sharc_set_irq_line(SHARC_REGS *cpustate, int irqline, int state) +void adsp21062_device::execute_set_input(int irqline, int state) { - if (state == ASSERT_LINE) + if (irqline >= 0 && irqline <= 2) { - cpustate->irq_active |= 1 << (8-irqline); - } - else - { - cpustate->irq_active &= ~(1 << (8-irqline)); - } + if (state == ASSERT_LINE) + { + m_irq_active |= 1 << (8-irqline); + } + else + { + m_irq_active &= ~(1 << (8-irqline)); + } + } + else if (irqline >= SHARC_INPUT_FLAG0 && irqline <= SHARC_INPUT_FLAG3) + { + set_flag_input(irqline - SHARC_INPUT_FLAG0, state); + } } -void sharc_set_flag_input(device_t *device, int flag_num, int state) +void adsp21062_device::set_flag_input(int flag_num, int state) { - SHARC_REGS *cpustate = get_safe_token(device); if (flag_num >= 0 && flag_num < 4) { // Check if flag is set to input in MODE2 (bit == 0) - if ((cpustate->mode2 & (1 << (flag_num+15))) == 0) + if ((m_mode2 & (1 << (flag_num+15))) == 0) { - cpustate->flag[flag_num] = state ? 1 : 0; + m_flag[flag_num] = state ? 1 : 0; } else { @@ -636,280 +683,156 @@ void sharc_set_flag_input(device_t *device, int flag_num, int state) } } -static void check_interrupts(SHARC_REGS *cpustate) +void adsp21062_device::check_interrupts() { int i; - if ((cpustate->imask & cpustate->irq_active) && (cpustate->mode1 & MODE1_IRPTEN) && !cpustate->interrupt_active && - cpustate->pc != cpustate->delay_slot1 && cpustate->pc != cpustate->delay_slot2) + if ((m_imask & m_irq_active) && (m_mode1 & MODE1_IRPTEN) && !m_interrupt_active && + m_pc != m_delay_slot1 && m_pc != m_delay_slot2) { int which = 0; for (i=0; i < 32; i++) { - if (cpustate->irq_active & (1 << i)) + if (m_irq_active & (1 << i)) { break; } which++; } - if (cpustate->idle) + if (m_idle) { - PUSH_PC(cpustate, cpustate->pc+1); + PUSH_PC(m_pc+1); } else { - PUSH_PC(cpustate, cpustate->daddr); + PUSH_PC(m_daddr); } - cpustate->irptl |= 1 << which; + m_irptl |= 1 << which; if (which >= 6 && which <= 8) { - PUSH_STATUS_STACK(cpustate); + PUSH_STATUS_STACK(); } - CHANGE_PC(cpustate, 0x20000 + (which * 0x4)); + CHANGE_PC(0x20000 + (which * 0x4)); /* TODO: alter IMASKP */ - cpustate->active_irq_num = which; - cpustate->irq_active &= ~(1 << which); + m_active_irq_num = which; + m_irq_active &= ~(1 << which); - cpustate->interrupt_active = 1; + m_interrupt_active = 1; } } -static CPU_EXECUTE( sharc ) +void adsp21062_device::execute_run() { - SHARC_REGS *cpustate = get_safe_token(device); - - if (cpustate->idle && cpustate->irq_active == 0) + if (m_idle && m_irq_active == 0) { - cpustate->icount = 0; - debugger_instruction_hook(device, cpustate->daddr); + m_icount = 0; + debugger_instruction_hook(this, m_daddr); } - if (cpustate->irq_active != 0) + if (m_irq_active != 0) { - check_interrupts(cpustate); - cpustate->idle = 0; + check_interrupts(); + m_idle = 0; } - while (cpustate->icount > 0 && !cpustate->idle) + while (m_icount > 0 && !m_idle) { - cpustate->pc = cpustate->daddr; - cpustate->daddr = cpustate->faddr; - cpustate->faddr = cpustate->nfaddr; - cpustate->nfaddr++; + m_pc = m_daddr; + m_daddr = m_faddr; + m_faddr = m_nfaddr; + m_nfaddr++; - cpustate->astat_old_old_old = cpustate->astat_old_old; - cpustate->astat_old_old = cpustate->astat_old; - cpustate->astat_old = cpustate->astat; + m_astat_old_old_old = m_astat_old_old; + m_astat_old_old = m_astat_old; + m_astat_old = m_astat; - cpustate->opcode = ROPCODE(cpustate->pc); + m_opcode = ROPCODE(m_pc); - debugger_instruction_hook(device, cpustate->pc); + debugger_instruction_hook(this, m_pc); // handle looping - if (cpustate->pc == cpustate->laddr.addr) + if (m_pc == m_laddr.addr) { - switch (cpustate->laddr.loop_type) + switch (m_laddr.loop_type) { case 0: // arithmetic condition-based { - int condition = cpustate->laddr.code; + int condition = m_laddr.code; { - UINT32 looptop = TOP_PC(cpustate); - if (cpustate->pc - looptop > 2) + UINT32 looptop = TOP_PC(); + if (m_pc - looptop > 2) { - cpustate->astat = cpustate->astat_old_old_old; + m_astat = m_astat_old_old_old; } } - if (DO_CONDITION_CODE(cpustate, condition)) + if (DO_CONDITION_CODE(condition)) { - POP_LOOP(cpustate); - POP_PC(cpustate); + POP_LOOP(); + POP_PC(); } else { - CHANGE_PC(cpustate, TOP_PC(cpustate)); + CHANGE_PC(TOP_PC()); } - cpustate->astat = cpustate->astat_old; + m_astat = m_astat_old; break; } case 1: // counter-based, length 1 { - //fatalerror("SHARC: counter-based loop, length 1 at %08X\n", cpustate->pc); + //fatalerror("SHARC: counter-based loop, length 1 at %08X\n", m_pc); //break; } case 2: // counter-based, length 2 { - //fatalerror("SHARC: counter-based loop, length 2 at %08X\n", cpustate->pc); + //fatalerror("SHARC: counter-based loop, length 2 at %08X\n", m_pc); //break; } case 3: // counter-based, length >2 { - --cpustate->lcstack[cpustate->lstkp]; - --cpustate->curlcntr; - if (cpustate->curlcntr == 0) + --m_lcstack[m_lstkp]; + --m_curlcntr; + if (m_curlcntr == 0) { - POP_LOOP(cpustate); - POP_PC(cpustate); + POP_LOOP(); + POP_PC(); } else { - CHANGE_PC(cpustate, TOP_PC(cpustate)); + CHANGE_PC(TOP_PC()); } } } } - sharc_op[(cpustate->opcode >> 39) & 0x1ff](cpustate); + (this->*m_sharc_op[(m_opcode >> 39) & 0x1ff])(); // System register latency effect - if (cpustate->systemreg_latency_cycles > 0) + if (m_systemreg_latency_cycles > 0) { - --cpustate->systemreg_latency_cycles; - if (cpustate->systemreg_latency_cycles <= 0) + --m_systemreg_latency_cycles; + if (m_systemreg_latency_cycles <= 0) { - systemreg_write_latency_effect(cpustate); + systemreg_write_latency_effect(); } } - --cpustate->icount; + --m_icount; }; } -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( sharc ) +bool adsp21062_device::memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value) { - SHARC_REGS *cpustate = get_safe_token(device); - - switch (state) - { - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + SHARC_PC: cpustate->pc = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_FADDR: cpustate->faddr = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_DADDR: cpustate->daddr = info->i; break; - - case CPUINFO_INT_REGISTER + SHARC_R0: cpustate->r[0].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R1: cpustate->r[1].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R2: cpustate->r[2].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R3: cpustate->r[3].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R4: cpustate->r[4].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R5: cpustate->r[5].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R6: cpustate->r[6].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R7: cpustate->r[7].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R8: cpustate->r[8].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R9: cpustate->r[9].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R10: cpustate->r[10].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R11: cpustate->r[11].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R12: cpustate->r[12].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R13: cpustate->r[13].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R14: cpustate->r[14].r = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_R15: cpustate->r[15].r = info->i; break; - - case CPUINFO_INT_REGISTER + SHARC_I0: cpustate->dag1.i[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I1: cpustate->dag1.i[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I2: cpustate->dag1.i[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I3: cpustate->dag1.i[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I4: cpustate->dag1.i[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I5: cpustate->dag1.i[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I6: cpustate->dag1.i[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I7: cpustate->dag1.i[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I8: cpustate->dag2.i[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I9: cpustate->dag2.i[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I10: cpustate->dag2.i[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I11: cpustate->dag2.i[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I12: cpustate->dag2.i[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I13: cpustate->dag2.i[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I14: cpustate->dag2.i[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_I15: cpustate->dag2.i[7] = info->i; break; - - case CPUINFO_INT_REGISTER + SHARC_M0: cpustate->dag1.m[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M1: cpustate->dag1.m[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M2: cpustate->dag1.m[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M3: cpustate->dag1.m[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M4: cpustate->dag1.m[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M5: cpustate->dag1.m[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M6: cpustate->dag1.m[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M7: cpustate->dag1.m[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M8: cpustate->dag2.m[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M9: cpustate->dag2.m[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M10: cpustate->dag2.m[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M11: cpustate->dag2.m[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M12: cpustate->dag2.m[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M13: cpustate->dag2.m[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M14: cpustate->dag2.m[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_M15: cpustate->dag2.m[7] = info->i; break; - - case CPUINFO_INT_REGISTER + SHARC_L0: cpustate->dag1.l[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L1: cpustate->dag1.l[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L2: cpustate->dag1.l[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L3: cpustate->dag1.l[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L4: cpustate->dag1.l[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L5: cpustate->dag1.l[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L6: cpustate->dag1.l[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L7: cpustate->dag1.l[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L8: cpustate->dag2.l[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L9: cpustate->dag2.l[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L10: cpustate->dag2.l[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L11: cpustate->dag2.l[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L12: cpustate->dag2.l[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L13: cpustate->dag2.l[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L14: cpustate->dag2.l[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_L15: cpustate->dag2.m[7] = info->i; break; - - case CPUINFO_INT_REGISTER + SHARC_B0: cpustate->dag1.b[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B1: cpustate->dag1.b[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B2: cpustate->dag1.b[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B3: cpustate->dag1.b[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B4: cpustate->dag1.b[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B5: cpustate->dag1.b[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B6: cpustate->dag1.b[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B7: cpustate->dag1.b[7] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B8: cpustate->dag2.b[0] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B9: cpustate->dag2.b[1] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B10: cpustate->dag2.b[2] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B11: cpustate->dag2.b[3] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B12: cpustate->dag2.b[4] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B13: cpustate->dag2.b[5] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B14: cpustate->dag2.b[6] = info->i; break; - case CPUINFO_INT_REGISTER + SHARC_B15: cpustate->dag2.b[7] = info->i; break; - } -} - -static CPU_SET_INFO( adsp21062 ) -{ - if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 2) - { - sharc_set_irq_line(get_safe_token(device), state-CPUINFO_INT_INPUT_STATE, info->i); - return; - } - else if (state >= CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0 && state <= CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG3) - { - sharc_set_flag_input(device, state-(CPUINFO_INT_INPUT_STATE + SHARC_INPUT_FLAG0), info->i); - return; - } - switch(state) - { - default: CPU_SET_INFO_CALL(sharc); break; - } -} - - -static CPU_READ( sharc ) -{ - SHARC_REGS *cpustate = get_safe_token(device); - if (space == AS_PROGRAM) + if (spacenum == AS_PROGRAM) { int address = offset >> 3; @@ -920,24 +843,25 @@ static CPU_READ( sharc ) case 1: { int frac = offset & 7; - *value = (pm_read48(cpustate, offset >> 3) >> ((frac^7) * 8)) & 0xff; + value = (pm_read48(offset >> 3) >> ((frac^7) * 8)) & 0xff; break; } case 8: { - *value = pm_read48(cpustate, offset >> 3); + value = pm_read48(offset >> 3); break; } } } else { - *value = 0; + value = 0; } } - else if (space == AS_DATA) + else if (spacenum == AS_DATA) { int address = offset >> 2; + if (address >= 0x20000) { switch (size) @@ -945,328 +869,53 @@ static CPU_READ( sharc ) case 1: { int frac = offset & 3; - *value = (dm_read32(cpustate, offset >> 2) >> ((frac^3) * 8)) & 0xff; + value = (dm_read32(offset >> 2) >> ((frac^3) * 8)) & 0xff; break; } case 2: { int frac = (offset >> 1) & 1; - *value = (dm_read32(cpustate, offset >> 2) >> ((frac^1) * 16)) & 0xffff; + value = (dm_read32(offset >> 2) >> ((frac^1) * 16)) & 0xffff; break; } case 4: { - *value = dm_read32(cpustate, offset >> 2); + value = dm_read32(offset >> 2); break; } } } else { - *value = 0; + value = 0; } } - return 1; + return true; } -static CPU_READOP( sharc ) +bool adsp21062_device::memory_readop(offs_t offset, int size, UINT64 &value) { - SHARC_REGS *cpustate = get_safe_token(device); UINT64 mask = (size < 8) ? (((UINT64)1 << (8 * size)) - 1) : ~(UINT64)0; int shift = 8 * (offset & 7); offset >>= 3; if (offset >= 0x20000 && offset < 0x28000) { - UINT64 op = ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 0]) << 32) | - ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 1]) << 16) | - ((UINT64)(cpustate->internal_ram_block0[((offset-0x20000) * 3) + 2]) << 0); - *value = (op >> shift) & mask; + UINT64 op = ((UINT64)(m_internal_ram_block0[((offset-0x20000) * 3) + 0]) << 32) | + ((UINT64)(m_internal_ram_block0[((offset-0x20000) * 3) + 1]) << 16) | + ((UINT64)(m_internal_ram_block0[((offset-0x20000) * 3) + 2]) << 0); + value = (op >> shift) & mask; + return true; } else if (offset >= 0x28000 && offset < 0x30000) { - UINT64 op = ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 0]) << 32) | - ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 1]) << 16) | - ((UINT64)(cpustate->internal_ram_block1[((offset-0x28000) * 3) + 2]) << 0); - *value = (op >> shift) & mask; + UINT64 op = ((UINT64)(m_internal_ram_block1[((offset-0x28000) * 3) + 0]) << 32) | + ((UINT64)(m_internal_ram_block1[((offset-0x28000) * 3) + 1]) << 16) | + ((UINT64)(m_internal_ram_block1[((offset-0x28000) * 3) + 2]) << 0); + value = (op >> shift) & mask; + return true; } - return 1; + return false; } -// This is just used to stop the debugger from complaining about executing from I/O space -static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 64, adsp21062_device ) - AM_RANGE(0x20000, 0x7ffff) AM_RAM -ADDRESS_MAP_END - -static CPU_GET_INFO( sharc ) -{ - SHARC_REGS *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch(state) - { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(SHARC_REGS); break; - case CPUINFO_INT_INPUT_LINES: info->i = 32; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 8; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 8; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 40; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 64; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 24; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -3; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -2; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break; - - case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + SHARC_PC: info->i = cpustate->pc; break; - case CPUINFO_INT_REGISTER + SHARC_PCSTK: info->i = cpustate->pcstk; break; - case CPUINFO_INT_REGISTER + SHARC_PCSTKP: info->i = cpustate->pcstkp; break; - case CPUINFO_INT_REGISTER + SHARC_LSTKP: info->i = cpustate->lstkp; break; - case CPUINFO_INT_REGISTER + SHARC_FADDR: info->i = cpustate->faddr; break; - case CPUINFO_INT_REGISTER + SHARC_DADDR: info->i = cpustate->daddr; break; - case CPUINFO_INT_REGISTER + SHARC_MODE1: info->i = cpustate->mode1; break; - case CPUINFO_INT_REGISTER + SHARC_MODE2: info->i = cpustate->mode2; break; - case CPUINFO_INT_REGISTER + SHARC_ASTAT: info->i = cpustate->astat; break; - case CPUINFO_INT_REGISTER + SHARC_IRPTL: info->i = cpustate->irptl; break; - case CPUINFO_INT_REGISTER + SHARC_IMASK: info->i = cpustate->imask; break; - case CPUINFO_INT_REGISTER + SHARC_USTAT1: info->i = cpustate->ustat1; break; - case CPUINFO_INT_REGISTER + SHARC_USTAT2: info->i = cpustate->ustat2; break; - case CPUINFO_INT_REGISTER + SHARC_STSTKP: info->i = cpustate->status_stkp; break; - - case CPUINFO_INT_REGISTER + SHARC_R0: info->i = cpustate->r[0].r; break; - case CPUINFO_INT_REGISTER + SHARC_R1: info->i = cpustate->r[1].r; break; - case CPUINFO_INT_REGISTER + SHARC_R2: info->i = cpustate->r[2].r; break; - case CPUINFO_INT_REGISTER + SHARC_R3: info->i = cpustate->r[3].r; break; - case CPUINFO_INT_REGISTER + SHARC_R4: info->i = cpustate->r[4].r; break; - case CPUINFO_INT_REGISTER + SHARC_R5: info->i = cpustate->r[5].r; break; - case CPUINFO_INT_REGISTER + SHARC_R6: info->i = cpustate->r[6].r; break; - case CPUINFO_INT_REGISTER + SHARC_R7: info->i = cpustate->r[7].r; break; - case CPUINFO_INT_REGISTER + SHARC_R8: info->i = cpustate->r[8].r; break; - case CPUINFO_INT_REGISTER + SHARC_R9: info->i = cpustate->r[9].r; break; - case CPUINFO_INT_REGISTER + SHARC_R10: info->i = cpustate->r[10].r; break; - case CPUINFO_INT_REGISTER + SHARC_R11: info->i = cpustate->r[11].r; break; - case CPUINFO_INT_REGISTER + SHARC_R12: info->i = cpustate->r[12].r; break; - case CPUINFO_INT_REGISTER + SHARC_R13: info->i = cpustate->r[13].r; break; - case CPUINFO_INT_REGISTER + SHARC_R14: info->i = cpustate->r[14].r; break; - case CPUINFO_INT_REGISTER + SHARC_R15: info->i = cpustate->r[15].r; break; - - case CPUINFO_INT_REGISTER + SHARC_I0: info->i = cpustate->dag1.i[0]; break; - case CPUINFO_INT_REGISTER + SHARC_I1: info->i = cpustate->dag1.i[1]; break; - case CPUINFO_INT_REGISTER + SHARC_I2: info->i = cpustate->dag1.i[2]; break; - case CPUINFO_INT_REGISTER + SHARC_I3: info->i = cpustate->dag1.i[3]; break; - case CPUINFO_INT_REGISTER + SHARC_I4: info->i = cpustate->dag1.i[4]; break; - case CPUINFO_INT_REGISTER + SHARC_I5: info->i = cpustate->dag1.i[5]; break; - case CPUINFO_INT_REGISTER + SHARC_I6: info->i = cpustate->dag1.i[6]; break; - case CPUINFO_INT_REGISTER + SHARC_I7: info->i = cpustate->dag1.i[7]; break; - case CPUINFO_INT_REGISTER + SHARC_I8: info->i = cpustate->dag2.i[0]; break; - case CPUINFO_INT_REGISTER + SHARC_I9: info->i = cpustate->dag2.i[1]; break; - case CPUINFO_INT_REGISTER + SHARC_I10: info->i = cpustate->dag2.i[2]; break; - case CPUINFO_INT_REGISTER + SHARC_I11: info->i = cpustate->dag2.i[3]; break; - case CPUINFO_INT_REGISTER + SHARC_I12: info->i = cpustate->dag2.i[4]; break; - case CPUINFO_INT_REGISTER + SHARC_I13: info->i = cpustate->dag2.i[5]; break; - case CPUINFO_INT_REGISTER + SHARC_I14: info->i = cpustate->dag2.i[6]; break; - case CPUINFO_INT_REGISTER + SHARC_I15: info->i = cpustate->dag2.i[7]; break; - - case CPUINFO_INT_REGISTER + SHARC_M0: info->i = cpustate->dag1.m[0]; break; - case CPUINFO_INT_REGISTER + SHARC_M1: info->i = cpustate->dag1.m[1]; break; - case CPUINFO_INT_REGISTER + SHARC_M2: info->i = cpustate->dag1.m[2]; break; - case CPUINFO_INT_REGISTER + SHARC_M3: info->i = cpustate->dag1.m[3]; break; - case CPUINFO_INT_REGISTER + SHARC_M4: info->i = cpustate->dag1.m[4]; break; - case CPUINFO_INT_REGISTER + SHARC_M5: info->i = cpustate->dag1.m[5]; break; - case CPUINFO_INT_REGISTER + SHARC_M6: info->i = cpustate->dag1.m[6]; break; - case CPUINFO_INT_REGISTER + SHARC_M7: info->i = cpustate->dag1.m[7]; break; - case CPUINFO_INT_REGISTER + SHARC_M8: info->i = cpustate->dag2.m[0]; break; - case CPUINFO_INT_REGISTER + SHARC_M9: info->i = cpustate->dag2.m[1]; break; - case CPUINFO_INT_REGISTER + SHARC_M10: info->i = cpustate->dag2.m[2]; break; - case CPUINFO_INT_REGISTER + SHARC_M11: info->i = cpustate->dag2.m[3]; break; - case CPUINFO_INT_REGISTER + SHARC_M12: info->i = cpustate->dag2.m[4]; break; - case CPUINFO_INT_REGISTER + SHARC_M13: info->i = cpustate->dag2.m[5]; break; - case CPUINFO_INT_REGISTER + SHARC_M14: info->i = cpustate->dag2.m[6]; break; - case CPUINFO_INT_REGISTER + SHARC_M15: info->i = cpustate->dag2.m[7]; break; - - case CPUINFO_INT_REGISTER + SHARC_L0: info->i = cpustate->dag1.l[0]; break; - case CPUINFO_INT_REGISTER + SHARC_L1: info->i = cpustate->dag1.l[1]; break; - case CPUINFO_INT_REGISTER + SHARC_L2: info->i = cpustate->dag1.l[2]; break; - case CPUINFO_INT_REGISTER + SHARC_L3: info->i = cpustate->dag1.l[3]; break; - case CPUINFO_INT_REGISTER + SHARC_L4: info->i = cpustate->dag1.l[4]; break; - case CPUINFO_INT_REGISTER + SHARC_L5: info->i = cpustate->dag1.l[5]; break; - case CPUINFO_INT_REGISTER + SHARC_L6: info->i = cpustate->dag1.l[6]; break; - case CPUINFO_INT_REGISTER + SHARC_L7: info->i = cpustate->dag1.l[7]; break; - case CPUINFO_INT_REGISTER + SHARC_L8: info->i = cpustate->dag2.l[0]; break; - case CPUINFO_INT_REGISTER + SHARC_L9: info->i = cpustate->dag2.l[1]; break; - case CPUINFO_INT_REGISTER + SHARC_L10: info->i = cpustate->dag2.l[2]; break; - case CPUINFO_INT_REGISTER + SHARC_L11: info->i = cpustate->dag2.l[3]; break; - case CPUINFO_INT_REGISTER + SHARC_L12: info->i = cpustate->dag2.l[4]; break; - case CPUINFO_INT_REGISTER + SHARC_L13: info->i = cpustate->dag2.l[5]; break; - case CPUINFO_INT_REGISTER + SHARC_L14: info->i = cpustate->dag2.l[6]; break; - case CPUINFO_INT_REGISTER + SHARC_L15: info->i = cpustate->dag2.l[7]; break; - - case CPUINFO_INT_REGISTER + SHARC_B0: info->i = cpustate->dag1.b[0]; break; - case CPUINFO_INT_REGISTER + SHARC_B1: info->i = cpustate->dag1.b[1]; break; - case CPUINFO_INT_REGISTER + SHARC_B2: info->i = cpustate->dag1.b[2]; break; - case CPUINFO_INT_REGISTER + SHARC_B3: info->i = cpustate->dag1.b[3]; break; - case CPUINFO_INT_REGISTER + SHARC_B4: info->i = cpustate->dag1.b[4]; break; - case CPUINFO_INT_REGISTER + SHARC_B5: info->i = cpustate->dag1.b[5]; break; - case CPUINFO_INT_REGISTER + SHARC_B6: info->i = cpustate->dag1.b[6]; break; - case CPUINFO_INT_REGISTER + SHARC_B7: info->i = cpustate->dag1.b[7]; break; - case CPUINFO_INT_REGISTER + SHARC_B8: info->i = cpustate->dag2.b[0]; break; - case CPUINFO_INT_REGISTER + SHARC_B9: info->i = cpustate->dag2.b[1]; break; - case CPUINFO_INT_REGISTER + SHARC_B10: info->i = cpustate->dag2.b[2]; break; - case CPUINFO_INT_REGISTER + SHARC_B11: info->i = cpustate->dag2.b[3]; break; - case CPUINFO_INT_REGISTER + SHARC_B12: info->i = cpustate->dag2.b[4]; break; - case CPUINFO_INT_REGISTER + SHARC_B13: info->i = cpustate->dag2.b[5]; break; - case CPUINFO_INT_REGISTER + SHARC_B14: info->i = cpustate->dag2.b[6]; break; - case CPUINFO_INT_REGISTER + SHARC_B15: info->i = cpustate->dag2.b[7]; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sharc); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sharc); break; - case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(sharc); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sharc);break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sharc); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; - case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(sharc); break; - case CPUINFO_FCT_READOP: info->readop = CPU_READOP_NAME(sharc); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(internal_pgm); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_FAMILY: strcpy(info->s, "SHARC"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "2.01"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break; - - case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break; - - case CPUINFO_STR_REGISTER + SHARC_PC: sprintf(info->s, "PC: %08X", cpustate->pc); break; - case CPUINFO_STR_REGISTER + SHARC_PCSTK: sprintf(info->s, "PCSTK: %08X", cpustate->pcstk); break; - case CPUINFO_STR_REGISTER + SHARC_PCSTKP: sprintf(info->s, "PCSTKP: %08X", cpustate->pcstkp); break; - case CPUINFO_STR_REGISTER + SHARC_LSTKP: sprintf(info->s, "LSTKP: %08X", cpustate->lstkp); break; - case CPUINFO_STR_REGISTER + SHARC_FADDR: sprintf(info->s, "FADDR: %08X", cpustate->faddr); break; - case CPUINFO_STR_REGISTER + SHARC_DADDR: sprintf(info->s, "DADDR: %08X", cpustate->daddr); break; - case CPUINFO_STR_REGISTER + SHARC_MODE1: sprintf(info->s, "MODE1: %08X", cpustate->mode1); break; - case CPUINFO_STR_REGISTER + SHARC_MODE2: sprintf(info->s, "MODE2: %08X", cpustate->mode2); break; - case CPUINFO_STR_REGISTER + SHARC_ASTAT: sprintf(info->s, "ASTAT: %08X", cpustate->astat); break; - case CPUINFO_STR_REGISTER + SHARC_IRPTL: sprintf(info->s, "IRPTL: %08X", cpustate->irptl); break; - case CPUINFO_STR_REGISTER + SHARC_IMASK: sprintf(info->s, "IMASK: %08X", cpustate->imask); break; - case CPUINFO_STR_REGISTER + SHARC_USTAT1: sprintf(info->s, "USTAT1: %08X", cpustate->ustat1); break; - case CPUINFO_STR_REGISTER + SHARC_USTAT2: sprintf(info->s, "USTAT2: %08X", cpustate->ustat2); break; - case CPUINFO_STR_REGISTER + SHARC_STSTKP: sprintf(info->s, "STSTKP: %08X", cpustate->status_stkp); break; - - case CPUINFO_STR_REGISTER + SHARC_R0: sprintf(info->s, "R0: %08X", (UINT32)cpustate->r[0].r); break; - case CPUINFO_STR_REGISTER + SHARC_R1: sprintf(info->s, "R1: %08X", (UINT32)cpustate->r[1].r); break; - case CPUINFO_STR_REGISTER + SHARC_R2: sprintf(info->s, "R2: %08X", (UINT32)cpustate->r[2].r); break; - case CPUINFO_STR_REGISTER + SHARC_R3: sprintf(info->s, "R3: %08X", (UINT32)cpustate->r[3].r); break; - case CPUINFO_STR_REGISTER + SHARC_R4: sprintf(info->s, "R4: %08X", (UINT32)cpustate->r[4].r); break; - case CPUINFO_STR_REGISTER + SHARC_R5: sprintf(info->s, "R5: %08X", (UINT32)cpustate->r[5].r); break; - case CPUINFO_STR_REGISTER + SHARC_R6: sprintf(info->s, "R6: %08X", (UINT32)cpustate->r[6].r); break; - case CPUINFO_STR_REGISTER + SHARC_R7: sprintf(info->s, "R7: %08X", (UINT32)cpustate->r[7].r); break; - case CPUINFO_STR_REGISTER + SHARC_R8: sprintf(info->s, "R8: %08X", (UINT32)cpustate->r[8].r); break; - case CPUINFO_STR_REGISTER + SHARC_R9: sprintf(info->s, "R9: %08X", (UINT32)cpustate->r[9].r); break; - case CPUINFO_STR_REGISTER + SHARC_R10: sprintf(info->s, "R10: %08X", (UINT32)cpustate->r[10].r); break; - case CPUINFO_STR_REGISTER + SHARC_R11: sprintf(info->s, "R11: %08X", (UINT32)cpustate->r[11].r); break; - case CPUINFO_STR_REGISTER + SHARC_R12: sprintf(info->s, "R12: %08X", (UINT32)cpustate->r[12].r); break; - case CPUINFO_STR_REGISTER + SHARC_R13: sprintf(info->s, "R13: %08X", (UINT32)cpustate->r[13].r); break; - case CPUINFO_STR_REGISTER + SHARC_R14: sprintf(info->s, "R14: %08X", (UINT32)cpustate->r[14].r); break; - case CPUINFO_STR_REGISTER + SHARC_R15: sprintf(info->s, "R15: %08X", (UINT32)cpustate->r[15].r); break; - - case CPUINFO_STR_REGISTER + SHARC_I0: sprintf(info->s, "I0: %08X", (UINT32)cpustate->dag1.i[0]); break; - case CPUINFO_STR_REGISTER + SHARC_I1: sprintf(info->s, "I1: %08X", (UINT32)cpustate->dag1.i[1]); break; - case CPUINFO_STR_REGISTER + SHARC_I2: sprintf(info->s, "I2: %08X", (UINT32)cpustate->dag1.i[2]); break; - case CPUINFO_STR_REGISTER + SHARC_I3: sprintf(info->s, "I3: %08X", (UINT32)cpustate->dag1.i[3]); break; - case CPUINFO_STR_REGISTER + SHARC_I4: sprintf(info->s, "I4: %08X", (UINT32)cpustate->dag1.i[4]); break; - case CPUINFO_STR_REGISTER + SHARC_I5: sprintf(info->s, "I5: %08X", (UINT32)cpustate->dag1.i[5]); break; - case CPUINFO_STR_REGISTER + SHARC_I6: sprintf(info->s, "I6: %08X", (UINT32)cpustate->dag1.i[6]); break; - case CPUINFO_STR_REGISTER + SHARC_I7: sprintf(info->s, "I7: %08X", (UINT32)cpustate->dag1.i[7]); break; - case CPUINFO_STR_REGISTER + SHARC_I8: sprintf(info->s, "I8: %08X", (UINT32)cpustate->dag2.i[0]); break; - case CPUINFO_STR_REGISTER + SHARC_I9: sprintf(info->s, "I9: %08X", (UINT32)cpustate->dag2.i[1]); break; - case CPUINFO_STR_REGISTER + SHARC_I10: sprintf(info->s, "I10: %08X", (UINT32)cpustate->dag2.i[2]); break; - case CPUINFO_STR_REGISTER + SHARC_I11: sprintf(info->s, "I11: %08X", (UINT32)cpustate->dag2.i[3]); break; - case CPUINFO_STR_REGISTER + SHARC_I12: sprintf(info->s, "I12: %08X", (UINT32)cpustate->dag2.i[4]); break; - case CPUINFO_STR_REGISTER + SHARC_I13: sprintf(info->s, "I13: %08X", (UINT32)cpustate->dag2.i[5]); break; - case CPUINFO_STR_REGISTER + SHARC_I14: sprintf(info->s, "I14: %08X", (UINT32)cpustate->dag2.i[6]); break; - case CPUINFO_STR_REGISTER + SHARC_I15: sprintf(info->s, "I15: %08X", (UINT32)cpustate->dag2.i[7]); break; - - case CPUINFO_STR_REGISTER + SHARC_M0: sprintf(info->s, "M0: %08X", (UINT32)cpustate->dag1.m[0]); break; - case CPUINFO_STR_REGISTER + SHARC_M1: sprintf(info->s, "M1: %08X", (UINT32)cpustate->dag1.m[1]); break; - case CPUINFO_STR_REGISTER + SHARC_M2: sprintf(info->s, "M2: %08X", (UINT32)cpustate->dag1.m[2]); break; - case CPUINFO_STR_REGISTER + SHARC_M3: sprintf(info->s, "M3: %08X", (UINT32)cpustate->dag1.m[3]); break; - case CPUINFO_STR_REGISTER + SHARC_M4: sprintf(info->s, "M4: %08X", (UINT32)cpustate->dag1.m[4]); break; - case CPUINFO_STR_REGISTER + SHARC_M5: sprintf(info->s, "M5: %08X", (UINT32)cpustate->dag1.m[5]); break; - case CPUINFO_STR_REGISTER + SHARC_M6: sprintf(info->s, "M6: %08X", (UINT32)cpustate->dag1.m[6]); break; - case CPUINFO_STR_REGISTER + SHARC_M7: sprintf(info->s, "M7: %08X", (UINT32)cpustate->dag1.m[7]); break; - case CPUINFO_STR_REGISTER + SHARC_M8: sprintf(info->s, "M8: %08X", (UINT32)cpustate->dag2.m[0]); break; - case CPUINFO_STR_REGISTER + SHARC_M9: sprintf(info->s, "M9: %08X", (UINT32)cpustate->dag2.m[1]); break; - case CPUINFO_STR_REGISTER + SHARC_M10: sprintf(info->s, "M10: %08X", (UINT32)cpustate->dag2.m[2]); break; - case CPUINFO_STR_REGISTER + SHARC_M11: sprintf(info->s, "M11: %08X", (UINT32)cpustate->dag2.m[3]); break; - case CPUINFO_STR_REGISTER + SHARC_M12: sprintf(info->s, "M12: %08X", (UINT32)cpustate->dag2.m[4]); break; - case CPUINFO_STR_REGISTER + SHARC_M13: sprintf(info->s, "M13: %08X", (UINT32)cpustate->dag2.m[5]); break; - case CPUINFO_STR_REGISTER + SHARC_M14: sprintf(info->s, "M14: %08X", (UINT32)cpustate->dag2.m[6]); break; - case CPUINFO_STR_REGISTER + SHARC_M15: sprintf(info->s, "M15: %08X", (UINT32)cpustate->dag2.m[7]); break; - - case CPUINFO_STR_REGISTER + SHARC_L0: sprintf(info->s, "L0: %08X", (UINT32)cpustate->dag1.l[0]); break; - case CPUINFO_STR_REGISTER + SHARC_L1: sprintf(info->s, "L1: %08X", (UINT32)cpustate->dag1.l[1]); break; - case CPUINFO_STR_REGISTER + SHARC_L2: sprintf(info->s, "L2: %08X", (UINT32)cpustate->dag1.l[2]); break; - case CPUINFO_STR_REGISTER + SHARC_L3: sprintf(info->s, "L3: %08X", (UINT32)cpustate->dag1.l[3]); break; - case CPUINFO_STR_REGISTER + SHARC_L4: sprintf(info->s, "L4: %08X", (UINT32)cpustate->dag1.l[4]); break; - case CPUINFO_STR_REGISTER + SHARC_L5: sprintf(info->s, "L5: %08X", (UINT32)cpustate->dag1.l[5]); break; - case CPUINFO_STR_REGISTER + SHARC_L6: sprintf(info->s, "L6: %08X", (UINT32)cpustate->dag1.l[6]); break; - case CPUINFO_STR_REGISTER + SHARC_L7: sprintf(info->s, "L7: %08X", (UINT32)cpustate->dag1.l[7]); break; - case CPUINFO_STR_REGISTER + SHARC_L8: sprintf(info->s, "L8: %08X", (UINT32)cpustate->dag2.l[0]); break; - case CPUINFO_STR_REGISTER + SHARC_L9: sprintf(info->s, "L9: %08X", (UINT32)cpustate->dag2.l[1]); break; - case CPUINFO_STR_REGISTER + SHARC_L10: sprintf(info->s, "L10: %08X", (UINT32)cpustate->dag2.l[2]); break; - case CPUINFO_STR_REGISTER + SHARC_L11: sprintf(info->s, "L11: %08X", (UINT32)cpustate->dag2.l[3]); break; - case CPUINFO_STR_REGISTER + SHARC_L12: sprintf(info->s, "L12: %08X", (UINT32)cpustate->dag2.l[4]); break; - case CPUINFO_STR_REGISTER + SHARC_L13: sprintf(info->s, "L13: %08X", (UINT32)cpustate->dag2.l[5]); break; - case CPUINFO_STR_REGISTER + SHARC_L14: sprintf(info->s, "L14: %08X", (UINT32)cpustate->dag2.l[6]); break; - case CPUINFO_STR_REGISTER + SHARC_L15: sprintf(info->s, "L15: %08X", (UINT32)cpustate->dag2.l[7]); break; - - case CPUINFO_STR_REGISTER + SHARC_B0: sprintf(info->s, "B0: %08X", (UINT32)cpustate->dag1.b[0]); break; - case CPUINFO_STR_REGISTER + SHARC_B1: sprintf(info->s, "B1: %08X", (UINT32)cpustate->dag1.b[1]); break; - case CPUINFO_STR_REGISTER + SHARC_B2: sprintf(info->s, "B2: %08X", (UINT32)cpustate->dag1.b[2]); break; - case CPUINFO_STR_REGISTER + SHARC_B3: sprintf(info->s, "B3: %08X", (UINT32)cpustate->dag1.b[3]); break; - case CPUINFO_STR_REGISTER + SHARC_B4: sprintf(info->s, "B4: %08X", (UINT32)cpustate->dag1.b[4]); break; - case CPUINFO_STR_REGISTER + SHARC_B5: sprintf(info->s, "B5: %08X", (UINT32)cpustate->dag1.b[5]); break; - case CPUINFO_STR_REGISTER + SHARC_B6: sprintf(info->s, "B6: %08X", (UINT32)cpustate->dag1.b[6]); break; - case CPUINFO_STR_REGISTER + SHARC_B7: sprintf(info->s, "B7: %08X", (UINT32)cpustate->dag1.b[7]); break; - case CPUINFO_STR_REGISTER + SHARC_B8: sprintf(info->s, "B8: %08X", (UINT32)cpustate->dag2.b[0]); break; - case CPUINFO_STR_REGISTER + SHARC_B9: sprintf(info->s, "B9: %08X", (UINT32)cpustate->dag2.b[1]); break; - case CPUINFO_STR_REGISTER + SHARC_B10: sprintf(info->s, "B10: %08X", (UINT32)cpustate->dag2.b[2]); break; - case CPUINFO_STR_REGISTER + SHARC_B11: sprintf(info->s, "B11: %08X", (UINT32)cpustate->dag2.b[3]); break; - case CPUINFO_STR_REGISTER + SHARC_B12: sprintf(info->s, "B12: %08X", (UINT32)cpustate->dag2.b[4]); break; - case CPUINFO_STR_REGISTER + SHARC_B13: sprintf(info->s, "B13: %08X", (UINT32)cpustate->dag2.b[5]); break; - case CPUINFO_STR_REGISTER + SHARC_B14: sprintf(info->s, "B14: %08X", (UINT32)cpustate->dag2.b[6]); break; - case CPUINFO_STR_REGISTER + SHARC_B15: sprintf(info->s, "B15: %08X", (UINT32)cpustate->dag2.b[7]); break; - } -} - -CPU_GET_INFO( adsp21062 ) -{ - switch(state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(adsp21062); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "ADSP21062"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "adsp21062"); break; - - default: CPU_GET_INFO_CALL(sharc); break; - } -} - -DEFINE_LEGACY_CPU_DEVICE(ADSP21062, adsp21062); diff --git a/src/emu/cpu/sharc/sharc.h b/src/emu/cpu/sharc/sharc.h index 6305b746410..c33b29e3bf5 100644 --- a/src/emu/cpu/sharc/sharc.h +++ b/src/emu/cpu/sharc/sharc.h @@ -9,6 +9,7 @@ #define SHARC_INPUT_FLAG2 5 #define SHARC_INPUT_FLAG3 6 + enum SHARC_BOOT_MODE { BOOT_MODE_EPROM, @@ -17,17 +18,335 @@ enum SHARC_BOOT_MODE BOOT_MODE_NOBOOT }; -struct sharc_config { - SHARC_BOOT_MODE boot_mode; + +struct SHARC_DAG +{ + UINT32 i[8]; + UINT32 m[8]; + UINT32 b[8]; + UINT32 l[8]; }; -extern void sharc_set_flag_input(device_t *device, int flag_num, int state); +union SHARC_REG +{ + INT32 r; + float f; +}; -extern void sharc_external_iop_write(device_t *device, UINT32 address, UINT32 data); -extern void sharc_external_dma_write(device_t *device, UINT32 address, UINT64 data); +struct SHARC_DMA_REGS +{ + UINT32 control; + UINT32 int_index; + UINT32 int_modifier; + UINT32 int_count; + UINT32 chain_ptr; + UINT32 gen_purpose; + UINT32 ext_index; + UINT32 ext_modifier; + UINT32 ext_count; +}; -DECLARE_LEGACY_CPU_DEVICE(ADSP21062, adsp21062); +struct SHARC_LADDR +{ + UINT32 addr; + UINT32 code; + UINT32 loop_type; +}; + +struct SHARC_DMA_OP +{ + UINT32 src; + UINT32 dst; + UINT32 chain_ptr; + INT32 src_modifier; + INT32 dst_modifier; + INT32 src_count; + INT32 dst_count; + INT32 pmode; + INT32 chained_direction; + emu_timer *timer; + bool active; +}; + + +#define MCFG_SHARC_BOOT_MODE(boot_mode) \ + adsp21062_device::set_boot_mode(*device, boot_mode); + + +class adsp21062_device : public cpu_device +{ +public: + // construction/destruction + adsp21062_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock); + + // static configuration helpers + static void set_boot_mode(device_t &device, const SHARC_BOOT_MODE boot_mode) { downcast(device).m_boot_mode = boot_mode; } + + void set_flag_input(int flag_num, int state); + void external_iop_write(UINT32 address, UINT32 data); + void external_dma_write(UINT32 address, UINT64 data); + + TIMER_CALLBACK_MEMBER(sharc_iop_delayed_write_callback); + TIMER_CALLBACK_MEMBER(sharc_dma_callback); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 8; } + virtual UINT32 execute_max_cycles() const { return 8; } + virtual UINT32 execute_input_lines() const { return 32; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ); } + virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value); + virtual bool memory_readop(offs_t offset, int size, UINT64 &value); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 1; } + virtual UINT32 disasm_max_opcode_bytes() const { return 40; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +private: + address_space_config m_program_config; + address_space_config m_data_config; + + typedef void (adsp21062_device::*opcode_func)(); + struct SHARC_OP + { + UINT32 op_mask; + UINT32 op_bits; + opcode_func handler; + }; + static const SHARC_OP s_sharc_opcode_table[]; + + UINT32 m_pc; + SHARC_REG m_r[16]; + SHARC_REG m_reg_alt[16]; + UINT64 m_mrf; + UINT64 m_mrb; + + UINT32 m_pcstack[32]; + UINT32 m_lcstack[6]; + UINT32 m_lastack[6]; + UINT32 m_lstkp; + + UINT32 m_faddr; + UINT32 m_daddr; + UINT32 m_pcstk; + UINT32 m_pcstkp; + SHARC_LADDR m_laddr; + UINT32 m_curlcntr; + UINT32 m_lcntr; + + /* Data Address Generator (DAG) */ + SHARC_DAG m_dag1; // (DM bus) + SHARC_DAG m_dag2; // (PM bus) + SHARC_DAG m_dag1_alt; + SHARC_DAG m_dag2_alt; + + SHARC_DMA_REGS m_dma[12]; + + /* System registers */ + UINT32 m_mode1; + UINT32 m_mode2; + UINT32 m_astat; + UINT32 m_stky; + UINT32 m_irptl; + UINT32 m_imask; + UINT32 m_imaskp; + UINT32 m_ustat1; + UINT32 m_ustat2; + + UINT32 m_flag[4]; + + UINT32 m_syscon; + UINT32 m_sysstat; + + struct + { + UINT32 mode1; + UINT32 astat; + } m_status_stack[5]; + INT32 m_status_stkp; + + UINT64 m_px; + + UINT16 *m_internal_ram; + UINT16 *m_internal_ram_block0, *m_internal_ram_block1; + + address_space *m_program; + address_space *m_data; + opcode_func m_sharc_op[512]; + int m_icount; + UINT64 m_opcode; + + UINT32 m_nfaddr; + + INT32 m_idle; + INT32 m_irq_active; + INT32 m_active_irq_num; + + SHARC_BOOT_MODE m_boot_mode; + + SHARC_DMA_OP m_dma_op[12]; + UINT32 m_dma_status; + + INT32 m_interrupt_active; + + UINT32 m_iop_delayed_reg; + UINT32 m_iop_delayed_data; + emu_timer *m_delayed_iop_timer; + + UINT32 m_delay_slot1, m_delay_slot2; + + INT32 m_systemreg_latency_cycles; + INT32 m_systemreg_latency_reg; + UINT32 m_systemreg_latency_data; + UINT32 m_systemreg_previous_data; + + UINT32 m_astat_old; + UINT32 m_astat_old_old; + UINT32 m_astat_old_old_old; + + inline void CHANGE_PC(UINT32 newpc); + inline void CHANGE_PC_DELAYED(UINT32 newpc); + void sharc_iop_delayed_w(UINT32 reg, UINT32 data, int cycles); + UINT32 sharc_iop_r(UINT32 address); + void sharc_iop_w(UINT32 address, UINT32 data); + UINT32 pm_read32(UINT32 address); + void pm_write32(UINT32 address, UINT32 data); + UINT64 pm_read48(UINT32 address); + void pm_write48(UINT32 address, UINT64 data); + UINT32 dm_read32(UINT32 address); + void dm_write32(UINT32 address, UINT32 data); + void schedule_chained_dma_op(int channel, UINT32 dma_chain_ptr, int chained_direction); + void schedule_dma_op(int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode); + void dma_op(int channel); + void sharc_dma_exec(int channel); + void add_systemreg_write_latency_effect(int sysreg, UINT32 data, UINT32 prev_data); + inline void swap_register(UINT32 *a, UINT32 *b); + void systemreg_write_latency_effect(); + UINT32 GET_UREG(int ureg); + void SET_UREG(int ureg, UINT32 data); + void SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx); + void COMPUTE(UINT32 opcode); + void check_interrupts(); + inline void PUSH_PC(UINT32 pc); + inline UINT32 POP_PC(); + inline UINT32 TOP_PC(); + inline void PUSH_LOOP(UINT32 addr, UINT32 code, UINT32 type, UINT32 count); + inline void POP_LOOP(); + inline void PUSH_STATUS_STACK(); + inline void POP_STATUS_STACK(); + inline int IF_CONDITION_CODE(int cond); + inline int DO_CONDITION_CODE(int cond); + void sharcop_compute_dreg_dm_dreg_pm(); + void sharcop_compute(); + void sharcop_compute_ureg_dmpm_premod(); + void sharcop_compute_ureg_dmpm_postmod(); + void sharcop_compute_dm_to_dreg_immmod(); + void sharcop_compute_dreg_to_dm_immmod(); + void sharcop_compute_pm_to_dreg_immmod(); + void sharcop_compute_dreg_to_pm_immmod(); + void sharcop_compute_ureg_to_ureg(); + void sharcop_imm_shift_dreg_dmpm(); + void sharcop_imm_shift(); + void sharcop_compute_modify(); + void sharcop_direct_call(); + void sharcop_direct_jump(); + void sharcop_relative_call(); + void sharcop_relative_jump(); + void sharcop_indirect_jump(); + void sharcop_indirect_call(); + void sharcop_relative_jump_compute(); + void sharcop_relative_call_compute(); + void sharcop_indirect_jump_compute_dreg_dm(); + void sharcop_relative_jump_compute_dreg_dm(); + void sharcop_rts(); + void sharcop_rti(); + void sharcop_do_until_counter_imm(); + void sharcop_do_until_counter_ureg(); + void sharcop_do_until(); + void sharcop_dm_to_ureg_direct(); + void sharcop_ureg_to_dm_direct(); + void sharcop_pm_to_ureg_direct(); + void sharcop_ureg_to_pm_direct(); + void sharcop_dm_to_ureg_indirect(); + void sharcop_ureg_to_dm_indirect(); + void sharcop_pm_to_ureg_indirect(); + void sharcop_ureg_to_pm_indirect(); + void sharcop_imm_to_dmpm(); + void sharcop_imm_to_ureg(); + void sharcop_sysreg_bitop(); + void sharcop_modify(); + void sharcop_bit_reverse(); + void sharcop_push_pop_stacks(); + void sharcop_nop(); + void sharcop_idle(); + void sharcop_unimplemented(); + inline void compute_add(int rn, int rx, int ry); + inline void compute_sub(int rn, int rx, int ry); + inline void compute_add_ci(int rn, int rx, int ry); + inline void compute_sub_ci(int rn, int rx, int ry); + inline void compute_and(int rn, int rx, int ry); + inline void compute_comp(int rx, int ry); + inline void compute_pass(int rn, int rx); + inline void compute_xor(int rn, int rx, int ry); + inline void compute_or(int rn, int rx, int ry); + inline void compute_inc(int rn, int rx); + inline void compute_dec(int rn, int rx); + inline void compute_min(int rn, int rx, int ry); + inline void compute_max(int rn, int rx, int ry); + inline void compute_neg(int rn, int rx); + inline void compute_not(int rn, int rx); + inline UINT32 SCALB(SHARC_REG rx, int ry); + inline void compute_float(int rn, int rx); + inline void compute_fix(int rn, int rx); + inline void compute_fix_scaled(int rn, int rx, int ry); + inline void compute_float_scaled(int rn, int rx, int ry); + inline void compute_logb(int rn, int rx); + inline void compute_scalb(int rn, int rx, int ry); + inline void compute_fadd(int rn, int rx, int ry); + inline void compute_fsub(int rn, int rx, int ry); + inline void compute_fneg(int rn, int rx); + inline void compute_fcomp(int rx, int ry); + inline void compute_fabs_plus(int rn, int rx, int ry); + inline void compute_fmax(int rn, int rx, int ry); + inline void compute_fmin(int rn, int rx, int ry); + inline void compute_fclip(int rn, int rx, int ry); + inline void compute_recips(int rn, int rx); + inline void compute_rsqrts(int rn, int rx); + inline void compute_fpass(int rn, int rx); + inline void compute_fabs(int rn, int rx); + inline void compute_mul_uuin(int rn, int rx, int ry); + inline void compute_mul_ssin(int rn, int rx, int ry); + inline UINT32 compute_mrf_plus_mul_ssin(int rx, int ry); + inline UINT32 compute_mrb_plus_mul_ssin(int rx, int ry); + inline void compute_fmul(int rn, int rx, int ry); + inline void compute_multi_mr_to_reg(int ai, int rk); + inline void compute_multi_reg_to_mr(int ai, int rk); + inline void compute_dual_add_sub(int ra, int rs, int rx, int ry); + inline void compute_mul_ssfr_add(int rm, int rxm, int rym, int ra, int rxa, int rya); + inline void compute_mul_ssfr_sub(int rm, int rxm, int rym, int ra, int rxa, int rya); + inline void compute_dual_fadd_fsub(int ra, int rs, int rx, int ry); + inline void compute_fmul_fadd(int fm, int fxm, int fym, int fa, int fxa, int fya); + inline void compute_fmul_fsub(int fm, int fxm, int fym, int fa, int fxa, int fya); + inline void compute_fmul_float_scaled(int fm, int fxm, int fym, int fa, int fxa, int fya); + inline void compute_fmul_fix_scaled(int fm, int fxm, int fym, int fa, int fxa, int fya); + inline void compute_fmul_fmax(int fm, int fxm, int fym, int fa, int fxa, int fya); + inline void compute_fmul_fmin(int fm, int fxm, int fym, int fa, int fxa, int fya); + inline void compute_fmul_dual_fadd_fsub(int fm, int fxm, int fym, int fa, int fs, int fxa, int fya); + void build_opcode_table(); + +}; + + +extern const device_type ADSP21062; -extern UINT32 sharc_dasm_one(char *buffer, offs_t pc, UINT64 opcode); #endif /* __SHARC_H__ */ diff --git a/src/emu/cpu/sharc/sharcdma.c b/src/emu/cpu/sharc/sharcdma.c index 394407bee2e..7107fa5f95f 100644 --- a/src/emu/cpu/sharc/sharcdma.c +++ b/src/emu/cpu/sharc/sharcdma.c @@ -6,91 +6,91 @@ #define DMA_PMODE_32_48 3 #define DMA_PMODE_8_48 4 -static void schedule_chained_dma_op(SHARC_REGS *cpustate, int channel, UINT32 dma_chain_ptr, int chained_direction) +void adsp21062_device::schedule_chained_dma_op(int channel, UINT32 dma_chain_ptr, int chained_direction) { UINT32 op_ptr = 0x20000 + dma_chain_ptr; - UINT32 int_index = dm_read32(cpustate, op_ptr - 0); - UINT32 int_modifier = dm_read32(cpustate, op_ptr - 1); - UINT32 int_count = dm_read32(cpustate, op_ptr - 2); - UINT32 chain_ptr = dm_read32(cpustate, op_ptr - 3); - //UINT32 gen_purpose = dm_read32(cpustate, op_ptr - 4); - UINT32 ext_index = dm_read32(cpustate, op_ptr - 5); - UINT32 ext_modifier = dm_read32(cpustate, op_ptr - 6); - UINT32 ext_count = dm_read32(cpustate, op_ptr - 7); + UINT32 int_index = dm_read32(op_ptr - 0); + UINT32 int_modifier = dm_read32(op_ptr - 1); + UINT32 int_count = dm_read32(op_ptr - 2); + UINT32 chain_ptr = dm_read32(op_ptr - 3); + //UINT32 gen_purpose = dm_read32(op_ptr - 4); + UINT32 ext_index = dm_read32(op_ptr - 5); + UINT32 ext_modifier = dm_read32(op_ptr - 6); + UINT32 ext_count = dm_read32(op_ptr - 7); - if (cpustate->dma_op[channel].active) + if (m_dma_op[channel].active) { - fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc); + fatalerror("schedule_chained_dma_op: DMA operation already scheduled at %08X!\n", m_pc); } if (chained_direction) // Transmit to external { - cpustate->dma_op[channel].dst = ext_index; - cpustate->dma_op[channel].dst_modifier = ext_modifier; - cpustate->dma_op[channel].dst_count = ext_count; - cpustate->dma_op[channel].src = int_index; - cpustate->dma_op[channel].src_modifier = int_modifier; - cpustate->dma_op[channel].src_count = int_count; + m_dma_op[channel].dst = ext_index; + m_dma_op[channel].dst_modifier = ext_modifier; + m_dma_op[channel].dst_count = ext_count; + m_dma_op[channel].src = int_index; + m_dma_op[channel].src_modifier = int_modifier; + m_dma_op[channel].src_count = int_count; } else // Receive from external { - cpustate->dma_op[channel].src = ext_index; - cpustate->dma_op[channel].src_modifier = ext_modifier; - cpustate->dma_op[channel].src_count = ext_count; - cpustate->dma_op[channel].dst = int_index; - cpustate->dma_op[channel].dst_modifier = int_modifier; - cpustate->dma_op[channel].dst_count = int_count; + m_dma_op[channel].src = ext_index; + m_dma_op[channel].src_modifier = ext_modifier; + m_dma_op[channel].src_count = ext_count; + m_dma_op[channel].dst = int_index; + m_dma_op[channel].dst_modifier = int_modifier; + m_dma_op[channel].dst_count = int_count; } - cpustate->dma_op[channel].pmode = 0; - cpustate->dma_op[channel].chain_ptr = chain_ptr; - cpustate->dma_op[channel].chained_direction = chained_direction; + m_dma_op[channel].pmode = 0; + m_dma_op[channel].chain_ptr = chain_ptr; + m_dma_op[channel].chained_direction = chained_direction; - cpustate->dma_op[channel].active = true; + m_dma_op[channel].active = true; - int cycles = cpustate->dma_op[channel].src_count / 4; - cpustate->dma_op[channel].timer->adjust(cpustate->device->cycles_to_attotime(cycles), channel); + int cycles = m_dma_op[channel].src_count / 4; + m_dma_op[channel].timer->adjust(cycles_to_attotime(cycles), channel); // enable busy flag - cpustate->dma_status |= (1 << channel); + m_dma_status |= (1 << channel); } -static void schedule_dma_op(SHARC_REGS *cpustate, int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode) +void adsp21062_device::schedule_dma_op(int channel, UINT32 src, UINT32 dst, int src_modifier, int dst_modifier, int src_count, int dst_count, int pmode) { - if (cpustate->dma_op[channel].active) + if (m_dma_op[channel].active) { - fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!\n", cpustate->pc); + fatalerror("schedule_dma_op: DMA operation already scheduled at %08X!\n", m_pc); } - cpustate->dma_op[channel].src = src; - cpustate->dma_op[channel].dst = dst; - cpustate->dma_op[channel].src_modifier = src_modifier; - cpustate->dma_op[channel].dst_modifier = dst_modifier; - cpustate->dma_op[channel].src_count = src_count; - cpustate->dma_op[channel].dst_count = dst_count; - cpustate->dma_op[channel].pmode = pmode; - cpustate->dma_op[channel].chain_ptr = 0; + m_dma_op[channel].src = src; + m_dma_op[channel].dst = dst; + m_dma_op[channel].src_modifier = src_modifier; + m_dma_op[channel].dst_modifier = dst_modifier; + m_dma_op[channel].src_count = src_count; + m_dma_op[channel].dst_count = dst_count; + m_dma_op[channel].pmode = pmode; + m_dma_op[channel].chain_ptr = 0; - cpustate->dma_op[channel].active = true; + m_dma_op[channel].active = true; int cycles = src_count / 4; - cpustate->dma_op[channel].timer->adjust(cpustate->device->cycles_to_attotime(cycles), channel); + m_dma_op[channel].timer->adjust(cycles_to_attotime(cycles), channel); // enable busy flag - cpustate->dma_status |= (1 << channel); + m_dma_status |= (1 << channel); } -static void dma_op(SHARC_REGS *cpustate, int channel) +void adsp21062_device::dma_op(int channel) { int i; - UINT32 src = cpustate->dma_op[channel].src; - UINT32 dst = cpustate->dma_op[channel].dst; - int src_modifier = cpustate->dma_op[channel].src_modifier; - int dst_modifier = cpustate->dma_op[channel].dst_modifier; - int src_count = cpustate->dma_op[channel].src_count; - //int dst_count = cpustate->dma_op[channel].dst_count; - int pmode = cpustate->dma_op[channel].pmode; + UINT32 src = m_dma_op[channel].src; + UINT32 dst = m_dma_op[channel].dst; + int src_modifier = m_dma_op[channel].src_modifier; + int dst_modifier = m_dma_op[channel].dst_modifier; + int src_count = m_dma_op[channel].src_count; + //int dst_count = m_dma_op[channel].dst_count; + int pmode = m_dma_op[channel].pmode; //printf("dma_op: %08X, %08X, %08X, %08X, %08X, %08X, %d\n", src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); @@ -100,8 +100,8 @@ static void dma_op(SHARC_REGS *cpustate, int channel) { for (i=0; i < src_count; i++) { - UINT32 data = dm_read32(cpustate, src); - dm_write32(cpustate, dst, data); + UINT32 data = dm_read32(src); + dm_write32(dst, data); src += src_modifier; dst += dst_modifier; } @@ -112,9 +112,9 @@ static void dma_op(SHARC_REGS *cpustate, int channel) int length = src_count/2; for (i=0; i < length; i++) { - UINT32 data = ((dm_read32(cpustate, src+0) & 0xffff) << 16) | (dm_read32(cpustate, src+1) & 0xffff); + UINT32 data = ((dm_read32(src+0) & 0xffff) << 16) | (dm_read32(src+1) & 0xffff); - dm_write32(cpustate, dst, data); + dm_write32(dst, data); src += src_modifier * 2; dst += dst_modifier; } @@ -125,14 +125,14 @@ static void dma_op(SHARC_REGS *cpustate, int channel) int length = src_count/6; for (i=0; i < length; i++) { - UINT64 data = ((UINT64)(dm_read32(cpustate, src+0) & 0xff) << 0) | - ((UINT64)(dm_read32(cpustate, src+1) & 0xff) << 8) | - ((UINT64)(dm_read32(cpustate, src+2) & 0xff) << 16) | - ((UINT64)(dm_read32(cpustate, src+3) & 0xff) << 24) | - ((UINT64)(dm_read32(cpustate, src+4) & 0xff) << 32) | - ((UINT64)(dm_read32(cpustate, src+5) & 0xff) << 40); + UINT64 data = ((UINT64)(dm_read32(src+0) & 0xff) << 0) | + ((UINT64)(dm_read32(src+1) & 0xff) << 8) | + ((UINT64)(dm_read32(src+2) & 0xff) << 16) | + ((UINT64)(dm_read32(src+3) & 0xff) << 24) | + ((UINT64)(dm_read32(src+4) & 0xff) << 32) | + ((UINT64)(dm_read32(src+5) & 0xff) << 40); - pm_write48(cpustate, dst, data); + pm_write48(dst, data); src += src_modifier * 6; dst += dst_modifier; } @@ -146,38 +146,38 @@ static void dma_op(SHARC_REGS *cpustate, int channel) if (channel == 6) { - cpustate->irptl |= (1 << (channel+10)); + m_irptl |= (1 << (channel+10)); /* DMA interrupt */ - if (cpustate->imask & (1 << (channel+10))) + if (m_imask & (1 << (channel+10))) { - cpustate->irq_active |= 1 << (channel+10); + m_irq_active |= 1 << (channel+10); } } // clear busy flag - cpustate->dma_status &= ~(1 << channel); + m_dma_status &= ~(1 << channel); - cpustate->dma_op[channel].active = false; + m_dma_op[channel].active = false; } -static void sharc_dma_exec(SHARC_REGS *cpustate, int channel) +void adsp21062_device::sharc_dma_exec(int channel) { UINT32 src, dst; UINT32 src_count, dst_count; UINT32 src_modifier, dst_modifier; int chen, tran, dtype, pmode, /*mswf, master,*/ ishake, intio/*, ext, flsh*/; - chen = (cpustate->dma[channel].control >> 1) & 0x1; - tran = (cpustate->dma[channel].control >> 2) & 0x1; - dtype = (cpustate->dma[channel].control >> 5) & 0x1; - pmode = (cpustate->dma[channel].control >> 6) & 0x3; - //mswf = (cpustate->dma[channel].control >> 8) & 0x1; - //master = (cpustate->dma[channel].control >> 9) & 0x1; - ishake = (cpustate->dma[channel].control >> 10) & 0x1; - intio = (cpustate->dma[channel].control >> 11) & 0x1; - //ext = (cpustate->dma[channel].control >> 12) & 0x1; - //flsh = (cpustate->dma[channel].control >> 13) & 0x1; + chen = (m_dma[channel].control >> 1) & 0x1; + tran = (m_dma[channel].control >> 2) & 0x1; + dtype = (m_dma[channel].control >> 5) & 0x1; + pmode = (m_dma[channel].control >> 6) & 0x3; + //mswf = (m_dma[channel].control >> 8) & 0x1; + //master = (m_dma[channel].control >> 9) & 0x1; + ishake = (m_dma[channel].control >> 10) & 0x1; + intio = (m_dma[channel].control >> 11) & 0x1; + //ext = (m_dma[channel].control >> 12) & 0x1; + //flsh = (m_dma[channel].control >> 13) & 0x1; if (ishake) fatalerror("SHARC: dma_exec: handshake not supported\n"); @@ -185,32 +185,31 @@ static void sharc_dma_exec(SHARC_REGS *cpustate, int channel) fatalerror("SHARC: dma_exec: single-word interrupt enable not supported\n"); - if (chen) // Chained DMA { - UINT32 dma_chain_ptr = cpustate->dma[channel].chain_ptr & 0x1ffff; + UINT32 dma_chain_ptr = m_dma[channel].chain_ptr & 0x1ffff; - schedule_chained_dma_op(cpustate, channel, dma_chain_ptr, tran); + schedule_chained_dma_op(channel, dma_chain_ptr, tran); } else { if (tran) // Transmit to external { - dst = cpustate->dma[channel].ext_index; - dst_modifier = cpustate->dma[channel].ext_modifier; - dst_count = cpustate->dma[channel].ext_count; - src = cpustate->dma[channel].int_index; - src_modifier = cpustate->dma[channel].int_modifier; - src_count = cpustate->dma[channel].int_count; + dst = m_dma[channel].ext_index; + dst_modifier = m_dma[channel].ext_modifier; + dst_count = m_dma[channel].ext_count; + src = m_dma[channel].int_index; + src_modifier = m_dma[channel].int_modifier; + src_count = m_dma[channel].int_count; } else // Receive from external { - src = cpustate->dma[channel].ext_index; - src_modifier = cpustate->dma[channel].ext_modifier; - src_count = cpustate->dma[channel].ext_count; - dst = cpustate->dma[channel].int_index; - dst_modifier = cpustate->dma[channel].int_modifier; - dst_count = cpustate->dma[channel].int_count; + src = m_dma[channel].ext_index; + src_modifier = m_dma[channel].ext_modifier; + src_count = m_dma[channel].ext_count; + dst = m_dma[channel].int_index; + dst_modifier = m_dma[channel].int_modifier; + dst_count = m_dma[channel].int_count; if (dst < 0x20000) { @@ -224,28 +223,27 @@ static void sharc_dma_exec(SHARC_REGS *cpustate, int channel) pmode = DMA_PMODE_8_48; } - schedule_dma_op(cpustate, channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); + schedule_dma_op(channel, src, dst, src_modifier, dst_modifier, src_count, dst_count, pmode); } } -static TIMER_CALLBACK(sharc_dma_callback) +TIMER_CALLBACK_MEMBER(adsp21062_device::sharc_dma_callback) { - SHARC_REGS *cpustate = (SHARC_REGS *)ptr; int channel = param; - cpustate->dma_op[channel].timer->adjust(attotime::never, 0); + m_dma_op[channel].timer->adjust(attotime::never, 0); - cpustate->irptl |= (1 << (channel+10)); + m_irptl |= (1 << (channel+10)); // DMA interrupt - if (cpustate->imask & (1 << (channel+10))) + if (m_imask & (1 << (channel+10))) { - cpustate->irq_active |= 1 << (channel+10); + m_irq_active |= 1 << (channel+10); } - dma_op(cpustate, channel); - if (cpustate->dma_op[channel].chain_ptr != 0) + dma_op(channel); + if (m_dma_op[channel].chain_ptr != 0) { - schedule_chained_dma_op(cpustate, channel, cpustate->dma_op[channel].chain_ptr, cpustate->dma_op[channel].chained_direction); + schedule_chained_dma_op(channel, m_dma_op[channel].chain_ptr, m_dma_op[channel].chained_direction); } } diff --git a/src/emu/cpu/sharc/sharcmem.c b/src/emu/cpu/sharc/sharcmem.c index 7d1cae5f84c..ed65d66d891 100644 --- a/src/emu/cpu/sharc/sharcmem.c +++ b/src/emu/cpu/sharc/sharcmem.c @@ -1,35 +1,35 @@ /* SHARC memory operations */ -static UINT32 pm_read32(SHARC_REGS *cpustate, UINT32 address) +UINT32 adsp21062_device::pm_read32(UINT32 address) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - return (UINT32)(cpustate->internal_ram_block0[addr + 0] << 16) | - (cpustate->internal_ram_block0[addr + 1]); + return (UINT32)(m_internal_ram_block0[addr + 0] << 16) | + (m_internal_ram_block0[addr + 1]); } else if (address >= 0x28000 && address < 0x40000) { // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - return (UINT32)(cpustate->internal_ram_block1[addr + 0] << 16) | - (cpustate->internal_ram_block1[addr + 1]); + return (UINT32)(m_internal_ram_block1[addr + 0] << 16) | + (m_internal_ram_block1[addr + 1]); } else { - fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, cpustate->pc); + fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, m_pc); } } -static void pm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) +void adsp21062_device::pm_write32(UINT32 address, UINT32 data) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 16); - cpustate->internal_ram_block0[addr + 1] = (UINT16)(data); + m_internal_ram_block0[addr + 0] = (UINT16)(data >> 16); + m_internal_ram_block0[addr + 1] = (UINT16)(data); return; } else if (address >= 0x28000 && address < 0x40000) @@ -37,50 +37,50 @@ static void pm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 16); - cpustate->internal_ram_block1[addr + 1] = (UINT16)(data); + m_internal_ram_block1[addr + 0] = (UINT16)(data >> 16); + m_internal_ram_block1[addr + 1] = (UINT16)(data); return; } else { - fatalerror("SHARC: PM Bus Write %08X, %08X at %08X\n", address, data, cpustate->pc); + fatalerror("SHARC: PM Bus Write %08X, %08X at %08X\n", address, data, m_pc); } } -static UINT64 pm_read48(SHARC_REGS *cpustate, UINT32 address) +UINT64 adsp21062_device::pm_read48(UINT32 address) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - return ((UINT64)(cpustate->internal_ram_block0[addr + 0]) << 32) | - ((UINT64)(cpustate->internal_ram_block0[addr + 1]) << 16) | - ((UINT64)(cpustate->internal_ram_block0[addr + 2]) << 0); + return ((UINT64)(m_internal_ram_block0[addr + 0]) << 32) | + ((UINT64)(m_internal_ram_block0[addr + 1]) << 16) | + ((UINT64)(m_internal_ram_block0[addr + 2]) << 0); } else if (address >= 0x28000 && address < 0x40000) { // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - return ((UINT64)(cpustate->internal_ram_block1[addr + 0]) << 32) | - ((UINT64)(cpustate->internal_ram_block1[addr + 1]) << 16) | - ((UINT64)(cpustate->internal_ram_block1[addr + 2]) << 0); + return ((UINT64)(m_internal_ram_block1[addr + 0]) << 32) | + ((UINT64)(m_internal_ram_block1[addr + 1]) << 16) | + ((UINT64)(m_internal_ram_block1[addr + 2]) << 0); } else { - fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, cpustate->pc); + fatalerror("SHARC: PM Bus Read %08X at %08X\n", address, m_pc); } return 0; } -static void pm_write48(SHARC_REGS *cpustate, UINT32 address, UINT64 data) +void adsp21062_device::pm_write48(UINT32 address, UINT64 data) { if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 3; - cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 32); - cpustate->internal_ram_block0[addr + 1] = (UINT16)(data >> 16); - cpustate->internal_ram_block0[addr + 2] = (UINT16)(data); + m_internal_ram_block0[addr + 0] = (UINT16)(data >> 32); + m_internal_ram_block0[addr + 1] = (UINT16)(data >> 16); + m_internal_ram_block0[addr + 2] = (UINT16)(data); return; } else if (address >= 0x28000 && address < 0x40000) @@ -88,36 +88,36 @@ static void pm_write48(SHARC_REGS *cpustate, UINT32 address, UINT64 data) // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 3; - cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 32); - cpustate->internal_ram_block1[addr + 1] = (UINT16)(data >> 16); - cpustate->internal_ram_block1[addr + 2] = (UINT16)(data); + m_internal_ram_block1[addr + 0] = (UINT16)(data >> 32); + m_internal_ram_block1[addr + 1] = (UINT16)(data >> 16); + m_internal_ram_block1[addr + 2] = (UINT16)(data); return; } else { - fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X\n", address, (UINT16)(data >> 32),(UINT32)data, cpustate->pc); + fatalerror("SHARC: PM Bus Write %08X, %04X%08X at %08X\n", address, (UINT16)(data >> 32),(UINT32)data, m_pc); } } -static UINT32 dm_read32(SHARC_REGS *cpustate, UINT32 address) +UINT32 adsp21062_device::dm_read32(UINT32 address) { if (address < 0x100) { - return sharc_iop_r(cpustate, address); + return sharc_iop_r(address); } else if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 2; - return (UINT32)(cpustate->internal_ram_block0[addr + 0] << 16) | - (cpustate->internal_ram_block0[addr + 1]); + return (UINT32)(m_internal_ram_block0[addr + 0] << 16) | + (m_internal_ram_block0[addr + 1]); } else if (address >= 0x28000 && address < 0x40000) { // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 2; - return (UINT32)(cpustate->internal_ram_block1[addr + 0] << 16) | - (cpustate->internal_ram_block1[addr + 1]); + return (UINT32)(m_internal_ram_block1[addr + 0] << 16) | + (m_internal_ram_block1[addr + 1]); } // short word addressing @@ -125,8 +125,8 @@ static UINT32 dm_read32(SHARC_REGS *cpustate, UINT32 address) { UINT32 addr = address & 0xffff; - UINT16 r = cpustate->internal_ram_block0[addr ^ 1]; - if (cpustate->mode1 & 0x4000) + UINT16 r = m_internal_ram_block0[addr ^ 1]; + if (m_mode1 & 0x4000) { // sign-extend return (INT32)(INT16)(r); @@ -141,8 +141,8 @@ static UINT32 dm_read32(SHARC_REGS *cpustate, UINT32 address) // block 1 is mirrored in 0x50000...5ffff, 0x60000...0x6ffff and 0x70000...7ffff UINT32 addr = address & 0xffff; - UINT16 r = cpustate->internal_ram_block1[addr ^ 1]; - if (cpustate->mode1 & 0x4000) + UINT16 r = m_internal_ram_block1[addr ^ 1]; + if (m_mode1 & 0x4000) { // sign-extend return (INT32)(INT16)(r); @@ -153,22 +153,22 @@ static UINT32 dm_read32(SHARC_REGS *cpustate, UINT32 address) } } - return cpustate->data->read_dword(address << 2); + return m_data->read_dword(address << 2); } -static void dm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) +void adsp21062_device::dm_write32(UINT32 address, UINT32 data) { if (address < 0x100) { - sharc_iop_w(cpustate, address, data); + sharc_iop_w(address, data); return; } else if (address >= 0x20000 && address < 0x28000) { UINT32 addr = (address & 0x7fff) * 2; - cpustate->internal_ram_block0[addr + 0] = (UINT16)(data >> 16); - cpustate->internal_ram_block0[addr + 1] = (UINT16)(data); + m_internal_ram_block0[addr + 0] = (UINT16)(data >> 16); + m_internal_ram_block0[addr + 1] = (UINT16)(data); return; } else if (address >= 0x28000 && address < 0x40000) @@ -176,8 +176,8 @@ static void dm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) // block 1 is mirrored in 0x28000...2ffff, 0x30000...0x37fff and 0x38000...3ffff UINT32 addr = (address & 0x7fff) * 2; - cpustate->internal_ram_block1[addr + 0] = (UINT16)(data >> 16); - cpustate->internal_ram_block1[addr + 1] = (UINT16)(data); + m_internal_ram_block1[addr + 0] = (UINT16)(data >> 16); + m_internal_ram_block1[addr + 1] = (UINT16)(data); return; } @@ -186,7 +186,7 @@ static void dm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) { UINT32 addr = address & 0xffff; - cpustate->internal_ram_block0[addr ^ 1] = data; + m_internal_ram_block0[addr ^ 1] = data; return; } else if (address >= 0x50000 && address < 0x80000) @@ -194,9 +194,9 @@ static void dm_write32(SHARC_REGS *cpustate, UINT32 address, UINT32 data) // block 1 is mirrored in 0x50000...5ffff, 0x60000...0x6ffff and 0x70000...7ffff UINT32 addr = address & 0xffff; - cpustate->internal_ram_block1[addr ^ 1] = data; + m_internal_ram_block1[addr ^ 1] = data; return; } - cpustate->data->write_dword(address << 2, data); + m_data->write_dword(address << 2, data); } diff --git a/src/emu/cpu/sharc/sharcops.c b/src/emu/cpu/sharc/sharcops.c index 95d49abcc73..d1efd4a87ba 100644 --- a/src/emu/cpu/sharc/sharcops.c +++ b/src/emu/cpu/sharc/sharcops.c @@ -1,14 +1,14 @@ #define SIGN_EXTEND6(x) (((x) & 0x20) ? (0xffffffc0 | (x)) : (x)) #define SIGN_EXTEND24(x) (((x) & 0x800000) ? (0xff000000 | (x)) : (x)) -#define PM_REG_I(x) (cpustate->dag2.i[x]) -#define PM_REG_M(x) (cpustate->dag2.m[x]) -#define PM_REG_B(x) (cpustate->dag2.b[x]) -#define PM_REG_L(x) (cpustate->dag2.l[x]) -#define DM_REG_I(x) (cpustate->dag1.i[x]) -#define DM_REG_M(x) (cpustate->dag1.m[x]) -#define DM_REG_B(x) (cpustate->dag1.b[x]) -#define DM_REG_L(x) (cpustate->dag1.l[x]) +#define PM_REG_I(x) (m_dag2.i[x]) +#define PM_REG_M(x) (m_dag2.m[x]) +#define PM_REG_B(x) (m_dag2.b[x]) +#define PM_REG_L(x) (m_dag2.l[x]) +#define DM_REG_I(x) (m_dag1.i[x]) +#define DM_REG_M(x) (m_dag1.m[x]) +#define DM_REG_B(x) (m_dag1.b[x]) +#define DM_REG_L(x) (m_dag1.l[x]) // ASTAT flags #define AZ 0x1 /* ALU result zero */ @@ -87,8 +87,8 @@ -#define REG(x) (cpustate->r[x].r) -#define FREG(x) (cpustate->r[x].f) +#define REG(x) (m_r[x].r) +#define FREG(x) (m_r[x].f) #define UPDATE_CIRCULAR_BUFFER_PM(x) \ { \ @@ -123,41 +123,39 @@ /*****************************************************************************/ -static void systemreg_write_latency_effect(SHARC_REGS *cpustate); - -static void add_systemreg_write_latency_effect(SHARC_REGS *cpustate, int sysreg, UINT32 data, UINT32 prev_data) +void adsp21062_device::add_systemreg_write_latency_effect(int sysreg, UINT32 data, UINT32 prev_data) { - if (cpustate->systemreg_latency_cycles > 0) + if (m_systemreg_latency_cycles > 0) { - //fatalerror("SHARC: add_systemreg_write_latency_effect: already scheduled! (reg: %02X, data: %08X, PC: %08X)\n", systemreg_latency_reg, systemreg_latency_data, cpustate->pc); - systemreg_write_latency_effect(cpustate); + //fatalerror("SHARC: add_systemreg_write_latency_effect: already scheduled! (reg: %02X, data: %08X, PC: %08X)\n", systemreg_latency_reg, systemreg_latency_data, m_pc); + systemreg_write_latency_effect(); } - cpustate->systemreg_latency_cycles = 2; - cpustate->systemreg_latency_reg = sysreg; - cpustate->systemreg_latency_data = data; - cpustate->systemreg_previous_data = prev_data; + m_systemreg_latency_cycles = 2; + m_systemreg_latency_reg = sysreg; + m_systemreg_latency_data = data; + m_systemreg_previous_data = prev_data; } -INLINE void swap_register(UINT32 *a, UINT32 *b) +void adsp21062_device::swap_register(UINT32 *a, UINT32 *b) { UINT32 temp = *a; *a = *b; *b = temp; } -static void systemreg_write_latency_effect(SHARC_REGS *cpustate) +void adsp21062_device::systemreg_write_latency_effect() { int i; - UINT32 data = cpustate->systemreg_latency_data; - UINT32 old_data = cpustate->systemreg_previous_data; + UINT32 data = m_systemreg_latency_data; + UINT32 old_data = m_systemreg_previous_data; - switch(cpustate->systemreg_latency_reg) + switch(m_systemreg_latency_reg) { case 0xb: /* MODE1 */ { UINT32 oldreg = old_data; - cpustate->mode1 = data; + m_mode1 = data; if ((data & 0x1) != (oldreg & 0x1)) { @@ -174,117 +172,117 @@ static void systemreg_write_latency_effect(SHARC_REGS *cpustate) if ((data & 0x8) != (oldreg & 0x8)) /* Switch DAG1 7-4 */ { - swap_register(&cpustate->dag1.i[4], &cpustate->dag1_alt.i[4]); - swap_register(&cpustate->dag1.i[5], &cpustate->dag1_alt.i[5]); - swap_register(&cpustate->dag1.i[6], &cpustate->dag1_alt.i[6]); - swap_register(&cpustate->dag1.i[7], &cpustate->dag1_alt.i[7]); - swap_register(&cpustate->dag1.m[4], &cpustate->dag1_alt.m[4]); - swap_register(&cpustate->dag1.m[5], &cpustate->dag1_alt.m[5]); - swap_register(&cpustate->dag1.m[6], &cpustate->dag1_alt.m[6]); - swap_register(&cpustate->dag1.m[7], &cpustate->dag1_alt.m[7]); - swap_register(&cpustate->dag1.l[4], &cpustate->dag1_alt.l[4]); - swap_register(&cpustate->dag1.l[5], &cpustate->dag1_alt.l[5]); - swap_register(&cpustate->dag1.l[6], &cpustate->dag1_alt.l[6]); - swap_register(&cpustate->dag1.l[7], &cpustate->dag1_alt.l[7]); - swap_register(&cpustate->dag1.b[4], &cpustate->dag1_alt.b[4]); - swap_register(&cpustate->dag1.b[5], &cpustate->dag1_alt.b[5]); - swap_register(&cpustate->dag1.b[6], &cpustate->dag1_alt.b[6]); - swap_register(&cpustate->dag1.b[7], &cpustate->dag1_alt.b[7]); + swap_register(&m_dag1.i[4], &m_dag1_alt.i[4]); + swap_register(&m_dag1.i[5], &m_dag1_alt.i[5]); + swap_register(&m_dag1.i[6], &m_dag1_alt.i[6]); + swap_register(&m_dag1.i[7], &m_dag1_alt.i[7]); + swap_register(&m_dag1.m[4], &m_dag1_alt.m[4]); + swap_register(&m_dag1.m[5], &m_dag1_alt.m[5]); + swap_register(&m_dag1.m[6], &m_dag1_alt.m[6]); + swap_register(&m_dag1.m[7], &m_dag1_alt.m[7]); + swap_register(&m_dag1.l[4], &m_dag1_alt.l[4]); + swap_register(&m_dag1.l[5], &m_dag1_alt.l[5]); + swap_register(&m_dag1.l[6], &m_dag1_alt.l[6]); + swap_register(&m_dag1.l[7], &m_dag1_alt.l[7]); + swap_register(&m_dag1.b[4], &m_dag1_alt.b[4]); + swap_register(&m_dag1.b[5], &m_dag1_alt.b[5]); + swap_register(&m_dag1.b[6], &m_dag1_alt.b[6]); + swap_register(&m_dag1.b[7], &m_dag1_alt.b[7]); } if ((data & 0x10) != (oldreg & 0x10)) /* Switch DAG1 3-0 */ { - swap_register(&cpustate->dag1.i[0], &cpustate->dag1_alt.i[0]); - swap_register(&cpustate->dag1.i[1], &cpustate->dag1_alt.i[1]); - swap_register(&cpustate->dag1.i[2], &cpustate->dag1_alt.i[2]); - swap_register(&cpustate->dag1.i[3], &cpustate->dag1_alt.i[3]); - swap_register(&cpustate->dag1.m[0], &cpustate->dag1_alt.m[0]); - swap_register(&cpustate->dag1.m[1], &cpustate->dag1_alt.m[1]); - swap_register(&cpustate->dag1.m[2], &cpustate->dag1_alt.m[2]); - swap_register(&cpustate->dag1.m[3], &cpustate->dag1_alt.m[3]); - swap_register(&cpustate->dag1.l[0], &cpustate->dag1_alt.l[0]); - swap_register(&cpustate->dag1.l[1], &cpustate->dag1_alt.l[1]); - swap_register(&cpustate->dag1.l[2], &cpustate->dag1_alt.l[2]); - swap_register(&cpustate->dag1.l[3], &cpustate->dag1_alt.l[3]); - swap_register(&cpustate->dag1.b[0], &cpustate->dag1_alt.b[0]); - swap_register(&cpustate->dag1.b[1], &cpustate->dag1_alt.b[1]); - swap_register(&cpustate->dag1.b[2], &cpustate->dag1_alt.b[2]); - swap_register(&cpustate->dag1.b[3], &cpustate->dag1_alt.b[3]); + swap_register(&m_dag1.i[0], &m_dag1_alt.i[0]); + swap_register(&m_dag1.i[1], &m_dag1_alt.i[1]); + swap_register(&m_dag1.i[2], &m_dag1_alt.i[2]); + swap_register(&m_dag1.i[3], &m_dag1_alt.i[3]); + swap_register(&m_dag1.m[0], &m_dag1_alt.m[0]); + swap_register(&m_dag1.m[1], &m_dag1_alt.m[1]); + swap_register(&m_dag1.m[2], &m_dag1_alt.m[2]); + swap_register(&m_dag1.m[3], &m_dag1_alt.m[3]); + swap_register(&m_dag1.l[0], &m_dag1_alt.l[0]); + swap_register(&m_dag1.l[1], &m_dag1_alt.l[1]); + swap_register(&m_dag1.l[2], &m_dag1_alt.l[2]); + swap_register(&m_dag1.l[3], &m_dag1_alt.l[3]); + swap_register(&m_dag1.b[0], &m_dag1_alt.b[0]); + swap_register(&m_dag1.b[1], &m_dag1_alt.b[1]); + swap_register(&m_dag1.b[2], &m_dag1_alt.b[2]); + swap_register(&m_dag1.b[3], &m_dag1_alt.b[3]); } if ((data & 0x20) != (oldreg & 0x20)) /* Switch DAG2 15-12 */ { - swap_register(&cpustate->dag2.i[4], &cpustate->dag2_alt.i[4]); - swap_register(&cpustate->dag2.i[5], &cpustate->dag2_alt.i[5]); - swap_register(&cpustate->dag2.i[6], &cpustate->dag2_alt.i[6]); - swap_register(&cpustate->dag2.i[7], &cpustate->dag2_alt.i[7]); - swap_register(&cpustate->dag2.m[4], &cpustate->dag2_alt.m[4]); - swap_register(&cpustate->dag2.m[5], &cpustate->dag2_alt.m[5]); - swap_register(&cpustate->dag2.m[6], &cpustate->dag2_alt.m[6]); - swap_register(&cpustate->dag2.m[7], &cpustate->dag2_alt.m[7]); - swap_register(&cpustate->dag2.l[4], &cpustate->dag2_alt.l[4]); - swap_register(&cpustate->dag2.l[5], &cpustate->dag2_alt.l[5]); - swap_register(&cpustate->dag2.l[6], &cpustate->dag2_alt.l[6]); - swap_register(&cpustate->dag2.l[7], &cpustate->dag2_alt.l[7]); - swap_register(&cpustate->dag2.b[4], &cpustate->dag2_alt.b[4]); - swap_register(&cpustate->dag2.b[5], &cpustate->dag2_alt.b[5]); - swap_register(&cpustate->dag2.b[6], &cpustate->dag2_alt.b[6]); - swap_register(&cpustate->dag2.b[7], &cpustate->dag2_alt.b[7]); + swap_register(&m_dag2.i[4], &m_dag2_alt.i[4]); + swap_register(&m_dag2.i[5], &m_dag2_alt.i[5]); + swap_register(&m_dag2.i[6], &m_dag2_alt.i[6]); + swap_register(&m_dag2.i[7], &m_dag2_alt.i[7]); + swap_register(&m_dag2.m[4], &m_dag2_alt.m[4]); + swap_register(&m_dag2.m[5], &m_dag2_alt.m[5]); + swap_register(&m_dag2.m[6], &m_dag2_alt.m[6]); + swap_register(&m_dag2.m[7], &m_dag2_alt.m[7]); + swap_register(&m_dag2.l[4], &m_dag2_alt.l[4]); + swap_register(&m_dag2.l[5], &m_dag2_alt.l[5]); + swap_register(&m_dag2.l[6], &m_dag2_alt.l[6]); + swap_register(&m_dag2.l[7], &m_dag2_alt.l[7]); + swap_register(&m_dag2.b[4], &m_dag2_alt.b[4]); + swap_register(&m_dag2.b[5], &m_dag2_alt.b[5]); + swap_register(&m_dag2.b[6], &m_dag2_alt.b[6]); + swap_register(&m_dag2.b[7], &m_dag2_alt.b[7]); } if ((data & 0x40) != (oldreg & 0x40)) /* Switch DAG2 11-8 */ { - swap_register(&cpustate->dag2.i[0], &cpustate->dag2_alt.i[0]); - swap_register(&cpustate->dag2.i[1], &cpustate->dag2_alt.i[1]); - swap_register(&cpustate->dag2.i[2], &cpustate->dag2_alt.i[2]); - swap_register(&cpustate->dag2.i[3], &cpustate->dag2_alt.i[3]); - swap_register(&cpustate->dag2.m[0], &cpustate->dag2_alt.m[0]); - swap_register(&cpustate->dag2.m[1], &cpustate->dag2_alt.m[1]); - swap_register(&cpustate->dag2.m[2], &cpustate->dag2_alt.m[2]); - swap_register(&cpustate->dag2.m[3], &cpustate->dag2_alt.m[3]); - swap_register(&cpustate->dag2.l[0], &cpustate->dag2_alt.l[0]); - swap_register(&cpustate->dag2.l[1], &cpustate->dag2_alt.l[1]); - swap_register(&cpustate->dag2.l[2], &cpustate->dag2_alt.l[2]); - swap_register(&cpustate->dag2.l[3], &cpustate->dag2_alt.l[3]); - swap_register(&cpustate->dag2.b[0], &cpustate->dag2_alt.b[0]); - swap_register(&cpustate->dag2.b[1], &cpustate->dag2_alt.b[1]); - swap_register(&cpustate->dag2.b[2], &cpustate->dag2_alt.b[2]); - swap_register(&cpustate->dag2.b[3], &cpustate->dag2_alt.b[3]); + swap_register(&m_dag2.i[0], &m_dag2_alt.i[0]); + swap_register(&m_dag2.i[1], &m_dag2_alt.i[1]); + swap_register(&m_dag2.i[2], &m_dag2_alt.i[2]); + swap_register(&m_dag2.i[3], &m_dag2_alt.i[3]); + swap_register(&m_dag2.m[0], &m_dag2_alt.m[0]); + swap_register(&m_dag2.m[1], &m_dag2_alt.m[1]); + swap_register(&m_dag2.m[2], &m_dag2_alt.m[2]); + swap_register(&m_dag2.m[3], &m_dag2_alt.m[3]); + swap_register(&m_dag2.l[0], &m_dag2_alt.l[0]); + swap_register(&m_dag2.l[1], &m_dag2_alt.l[1]); + swap_register(&m_dag2.l[2], &m_dag2_alt.l[2]); + swap_register(&m_dag2.l[3], &m_dag2_alt.l[3]); + swap_register(&m_dag2.b[0], &m_dag2_alt.b[0]); + swap_register(&m_dag2.b[1], &m_dag2_alt.b[1]); + swap_register(&m_dag2.b[2], &m_dag2_alt.b[2]); + swap_register(&m_dag2.b[3], &m_dag2_alt.b[3]); } if ((data & 0x80) != (oldreg & 0x80)) { for (i=8; i<16; i++) - swap_register((UINT32*)&cpustate->r[i].r, (UINT32*)&cpustate->reg_alt[i].r); + swap_register((UINT32*)&m_r[i].r, (UINT32*)&m_reg_alt[i].r); } if ((data & 0x400) != (oldreg & 0x400)) { for (i=0; i<8; i++) - swap_register((UINT32*)&cpustate->r[i].r, (UINT32*)&cpustate->reg_alt[i].r); + swap_register((UINT32*)&m_r[i].r, (UINT32*)&m_reg_alt[i].r); } break; } - default: fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X\n", cpustate->systemreg_latency_reg, cpustate->pc); + default: fatalerror("SHARC: systemreg_latency_op: unknown register %02X at %08X\n", m_systemreg_latency_reg, m_pc); } - cpustate->systemreg_latency_reg = -1; + m_systemreg_latency_reg = -1; } -static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) +UINT32 adsp21062_device::GET_UREG(int ureg) { int reg = ureg & 0xf; switch((ureg >> 4) & 0xf) { case 0x0: /* R0 - R15 */ { - return cpustate->r[reg].r; + return m_r[reg].r; } case 0x1: { if (reg & 0x8) /* I8 - I15 */ { - return cpustate->dag2.i[reg & 0x7]; + return m_dag2.i[reg & 0x7]; } else /* I0 - I7 */ { - return cpustate->dag1.i[reg & 0x7]; + return m_dag1.i[reg & 0x7]; } } @@ -292,14 +290,14 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) { if (reg & 0x8) /* M8 - M15 */ { - INT32 r = cpustate->dag2.m[reg & 0x7]; + INT32 r = m_dag2.m[reg & 0x7]; if (r & 0x800000) r |= 0xff000000; return r; } else /* M0 - M7 */ { - return cpustate->dag1.m[reg & 0x7]; + return m_dag1.m[reg & 0x7]; } } @@ -307,11 +305,11 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) { if (reg & 0x8) /* L8 - L15 */ { - return cpustate->dag2.l[reg & 0x7]; + return m_dag2.l[reg & 0x7]; } else /* L0 - L7 */ { - return cpustate->dag1.l[reg & 0x7]; + return m_dag1.l[reg & 0x7]; } } @@ -319,11 +317,11 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) { if (reg & 0x8) /* B8 - B15 */ { - return cpustate->dag2.b[reg & 0x7]; + return m_dag2.b[reg & 0x7]; } else /* B0 - B7 */ { - return cpustate->dag1.b[reg & 0x7]; + return m_dag1.b[reg & 0x7]; } } @@ -331,8 +329,8 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) { switch(reg) { - case 0x4: return cpustate->pcstack[cpustate->pcstkp]; /* PCSTK */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + case 0x4: return m_pcstack[m_pcstkp]; /* PCSTK */ + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } break; } @@ -341,24 +339,24 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) { switch(reg) { - case 0x0: return cpustate->ustat1; /* USTAT1 */ - case 0x1: return cpustate->ustat2; /* USTAT2 */ - case 0x9: return cpustate->irptl; /* IRPTL */ - case 0xa: return cpustate->mode2; /* MODE2 */ - case 0xb: return cpustate->mode1; /* MODE1 */ + case 0x0: return m_ustat1; /* USTAT1 */ + case 0x1: return m_ustat2; /* USTAT2 */ + case 0x9: return m_irptl; /* IRPTL */ + case 0xa: return m_mode2; /* MODE2 */ + case 0xb: return m_mode1; /* MODE1 */ case 0xc: /* ASTAT */ { - UINT32 r = cpustate->astat; + UINT32 r = m_astat; r &= ~0x00780000; - r |= (cpustate->flag[0] << 19); - r |= (cpustate->flag[1] << 20); - r |= (cpustate->flag[2] << 21); - r |= (cpustate->flag[3] << 22); + r |= (m_flag[0] << 19); + r |= (m_flag[1] << 20); + r |= (m_flag[2] << 21); + r |= (m_flag[3] << 22); return r; } - case 0xd: return cpustate->imask; /* IMASK */ - case 0xe: return cpustate->stky; /* STKY */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + case 0xd: return m_imask; /* IMASK */ + case 0xe: return m_stky; /* STKY */ + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } break; } @@ -368,57 +366,57 @@ static UINT32 GET_UREG(SHARC_REGS *cpustate, int ureg) switch(reg) { /* PX needs to be handled separately if the whole 48 bits are needed */ - case 0xb: return (UINT32)(cpustate->px); /* PX */ - case 0xc: return (UINT16)(cpustate->px); /* PX1 */ - case 0xd: return (UINT32)(cpustate->px >> 16); /* PX2 */ - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + case 0xb: return (UINT32)(m_px); /* PX */ + case 0xc: return (UINT16)(m_px); /* PX1 */ + case 0xd: return (UINT32)(m_px >> 16); /* PX2 */ + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } break; } - default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + default: fatalerror("SHARC: GET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } } -static void SET_UREG(SHARC_REGS *cpustate, int ureg, UINT32 data) +void adsp21062_device::SET_UREG(int ureg, UINT32 data) { int reg = ureg & 0xf; switch((ureg >> 4) & 0xf) { case 0x0: /* R0 - R15 */ - cpustate->r[reg].r = data; + m_r[reg].r = data; break; case 0x1: if (reg & 0x8) /* I8 - I15 */ { - cpustate->dag2.i[reg & 0x7] = data; + m_dag2.i[reg & 0x7] = data; } else /* I0 - I7 */ { - cpustate->dag1.i[reg & 0x7] = data; + m_dag1.i[reg & 0x7] = data; } break; case 0x2: if (reg & 0x8) /* M8 - M15 */ { - cpustate->dag2.m[reg & 0x7] = data; + m_dag2.m[reg & 0x7] = data; } else /* M0 - M7 */ { - cpustate->dag1.m[reg & 0x7] = data; + m_dag1.m[reg & 0x7] = data; } break; case 0x3: if (reg & 0x8) /* L8 - L15 */ { - cpustate->dag2.l[reg & 0x7] = data; + m_dag2.l[reg & 0x7] = data; } else /* L0 - L7 */ { - cpustate->dag1.l[reg & 0x7] = data; + m_dag1.l[reg & 0x7] = data; } break; @@ -426,83 +424,83 @@ static void SET_UREG(SHARC_REGS *cpustate, int ureg, UINT32 data) // Note: loading B also loads the same value in I if (reg & 0x8) /* B8 - B15 */ { - cpustate->dag2.b[reg & 0x7] = data; - cpustate->dag2.i[reg & 0x7] = data; + m_dag2.b[reg & 0x7] = data; + m_dag2.i[reg & 0x7] = data; } else /* B0 - B7 */ { - cpustate->dag1.b[reg & 0x7] = data; - cpustate->dag1.i[reg & 0x7] = data; + m_dag1.b[reg & 0x7] = data; + m_dag1.i[reg & 0x7] = data; } break; case 0x6: switch (reg) { - case 0x5: cpustate->pcstkp = data; break; /* PCSTKP */ - case 0x8: cpustate->lcntr = data; break; /* LCNTR */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + case 0x5: m_pcstkp = data; break; /* PCSTKP */ + case 0x8: m_lcntr = data; break; /* LCNTR */ + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } break; case 0x7: /* system regs */ switch(reg) { - case 0x0: cpustate->ustat1 = data; break; /* USTAT1 */ - case 0x1: cpustate->ustat2 = data; break; /* USTAT2 */ + case 0x0: m_ustat1 = data; break; /* USTAT1 */ + case 0x1: m_ustat2 = data; break; /* USTAT2 */ - case 0x9: cpustate->irptl = data; break; /* IRPTL */ - case 0xa: cpustate->mode2 = data; break; /* MODE2 */ + case 0x9: m_irptl = data; break; /* IRPTL */ + case 0xa: m_mode2 = data; break; /* MODE2 */ case 0xb: /* MODE1 */ { - add_systemreg_write_latency_effect(cpustate, reg, data, cpustate->mode1); - cpustate->mode1 = data; + add_systemreg_write_latency_effect(reg, data, m_mode1); + m_mode1 = data; break; } - case 0xc: cpustate->astat = data; break; /* ASTAT */ + case 0xc: m_astat = data; break; /* ASTAT */ case 0xd: /* IMASK */ { - check_interrupts(cpustate); - cpustate->imask = data; + check_interrupts(); + m_imask = data; break; } - case 0xe: cpustate->stky = data; break; /* STKY */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + case 0xe: m_stky = data; break; /* STKY */ + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } break; case 0xd: switch(reg) { - case 0xc: cpustate->px &= U64(0xffffffffffff0000); cpustate->px |= (data & 0xffff); break; /* PX1 */ - case 0xd: cpustate->px &= U64(0x000000000000ffff); cpustate->px |= (UINT64)data << 16; break; /* PX2 */ - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + case 0xc: m_px &= U64(0xffffffffffff0000); m_px |= (data & 0xffff); break; /* PX1 */ + case 0xd: m_px &= U64(0x000000000000ffff); m_px |= (UINT64)data << 16; break; /* PX2 */ + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } break; - default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, cpustate->pc); + default: fatalerror("SHARC: SET_UREG: unknown register %08X at %08X\n", ureg, m_pc); } } /*****************************************************************************/ -#define SET_FLAG_SV_LSHIFT(x, shift) if((x) & ((UINT32)0xffffffff << shift)) cpustate->astat |= SV -#define SET_FLAG_SV_RSHIFT(x, shift) if((x) & ((UINT32)0xffffffff >> shift)) cpustate->astat |= SV +#define SET_FLAG_SV_LSHIFT(x, shift) if((x) & ((UINT32)0xffffffff << shift)) m_astat |= SV +#define SET_FLAG_SV_RSHIFT(x, shift) if((x) & ((UINT32)0xffffffff >> shift)) m_astat |= SV -#define SET_FLAG_SZ(x) if((x) == 0) cpustate->astat |= SZ +#define SET_FLAG_SZ(x) if((x) == 0) m_astat |= SZ #define MAKE_EXTRACT_MASK(start_bit, length) ((0xffffffff << start_bit) & (((UINT32)0xffffffff) >> (32 - (start_bit + length)))) -static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int rn, int rx) +void adsp21062_device::SHIFT_OPERATION_IMM(int shiftop, int data, int rn, int rx) { INT8 shift = data & 0xff; int bit = data & 0x3f; int len = (data >> 6) & 0x3f; - cpustate->astat &= ~(SZ|SV|SS); + m_astat &= ~(SZ|SV|SS); switch(shiftop) { @@ -514,7 +512,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int REG(rn) = (shift < 32) ? (REG(rx) << shift) : 0; if (shift > 0) { - cpustate->astat |= SV; + m_astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -532,7 +530,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int REG(rn) = (shift < 32) ? ((INT32)REG(rx) << shift) : 0; if (shift > 0) { - cpustate->astat |= SV; + m_astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -566,7 +564,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int r = (shift < 32) ? (REG(rx) << shift) : 0; if (shift > 0) { - cpustate->astat |= SV; + m_astat |= SV; } } SET_FLAG_SZ(r); @@ -583,7 +581,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -599,7 +597,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -615,7 +613,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -629,7 +627,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -643,7 +641,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int } else { - cpustate->astat |= SV; + m_astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -658,7 +656,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int } else { - cpustate->astat |= SV; + m_astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -673,7 +671,7 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int } else { - cpustate->astat |= SV; + m_astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -689,18 +687,18 @@ static void SHIFT_OPERATION_IMM(SHARC_REGS *cpustate, int shiftop, int data, int } else { - cpustate->astat |= SZ | SV; + m_astat |= SZ | SV; } break; } - default: fatalerror("SHARC: unimplemented shift operation %02X at %08X\n", shiftop, cpustate->pc); + default: fatalerror("SHARC: unimplemented shift operation %02X at %08X\n", shiftop, m_pc); } } #include "compute.c" -static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) +void adsp21062_device::COMPUTE(UINT32 opcode) { int multiop; int op = (opcode >> 12) & 0xff; @@ -724,54 +722,54 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) multiop = (opcode >> 16) & 0x3f; switch(multiop) { - case 0x00: compute_multi_mr_to_reg(cpustate, op & 0xf, rn); break; - case 0x01: compute_multi_reg_to_mr(cpustate, op & 0xf, rn); break; + case 0x00: compute_multi_mr_to_reg(op & 0xf, rn); break; + case 0x01: compute_multi_reg_to_mr(op & 0xf, rn); break; case 0x04: /* Rm = Rxm * Rym (SSFR), Ra = Rxa + Rya */ { - compute_mul_ssfr_add(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_mul_ssfr_add(fm, fxm, fym, fa, fxa, fya); break; } case 0x05: /* Rm = Rxm * Rym (SSFR), Ra = Rxa - Rya */ { - compute_mul_ssfr_sub(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_mul_ssfr_sub(fm, fxm, fym, fa, fxa, fya); break; } case 0x18: /* Fm = Fxm * Fym, Fa = Fxa + Fya */ { - compute_fmul_fadd(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_fmul_fadd(fm, fxm, fym, fa, fxa, fya); break; } case 0x19: /* Fm = Fxm * Fym, Fa = Fxa - Fya */ { - compute_fmul_fsub(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_fmul_fsub(fm, fxm, fym, fa, fxa, fya); break; } case 0x1a: /* Fm = Fxm * Fym, Fa = FLOAT Fxa BY Fya */ { - compute_fmul_float_scaled(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_fmul_float_scaled(fm, fxm, fym, fa, fxa, fya); break; } case 0x1b: /* Fm = Fxm * Fym, Fa = FIX Fxa BY Fya */ { - compute_fmul_fix_scaled(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_fmul_fix_scaled(fm, fxm, fym, fa, fxa, fya); break; } case 0x1e: /* Fm = Fxm * Fym, Fa = MAX(Fxa, Fya) */ { - compute_fmul_fmax(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_fmul_fmax(fm, fxm, fym, fa, fxa, fya); break; } case 0x1f: /* Fm = Fxm * Fym, Fa = MIN(Fxa, Fya) */ { - compute_fmul_fmin(cpustate, fm, fxm, fym, fa, fxa, fya); + compute_fmul_fmin(fm, fxm, fym, fa, fxa, fya); break; } @@ -781,12 +779,12 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) /* Parallel Multiplier & Dual Add/Subtract */ /* Floating-point */ int fs = (opcode >> 16) & 0xf; - compute_fmul_dual_fadd_fsub(cpustate, fm, fxm, fym, fa, fs, fxa, fya); + compute_fmul_dual_fadd_fsub(fm, fxm, fym, fa, fs, fxa, fya); break; } default: - fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)\n", multiop, cpustate->pc, opcode); + fatalerror("SHARC: compute: multi-function opcode %02X not implemented ! (%08X, %08X)\n", multiop, m_pc, opcode); break; } } @@ -799,39 +797,39 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) { switch(op) { - case 0x01: compute_add(cpustate, rn, rx, ry); break; - case 0x02: compute_sub(cpustate, rn, rx, ry); break; - case 0x05: compute_add_ci(cpustate, rn, rx, ry); break; - case 0x06: compute_sub_ci(cpustate, rn, rx, ry); break; - case 0x0a: compute_comp(cpustate, rx, ry); break; - case 0x21: compute_pass(cpustate, rn, rx); break; - case 0x22: compute_neg(cpustate, rn, rx); break; - case 0x29: compute_inc(cpustate, rn, rx); break; - case 0x2a: compute_dec(cpustate, rn, rx); break; - case 0x40: compute_and(cpustate, rn, rx, ry); break; - case 0x41: compute_or(cpustate, rn, rx, ry); break; - case 0x42: compute_xor(cpustate, rn, rx, ry); break; - case 0x43: compute_not(cpustate, rn, rx); break; - case 0x61: compute_min(cpustate, rn, rx, ry); break; - case 0x62: compute_max(cpustate, rn, rx, ry); break; - case 0x81: compute_fadd(cpustate, rn, rx, ry); break; - case 0x82: compute_fsub(cpustate, rn, rx, ry); break; - case 0x8a: compute_fcomp(cpustate, rx, ry); break; - case 0x91: compute_fabs_plus(cpustate, rn, rx, ry); break; - case 0xa1: compute_fpass(cpustate, rn, rx); break; - case 0xa2: compute_fneg(cpustate, rn, rx); break; - case 0xb0: compute_fabs(cpustate, rn, rx); break; - case 0xbd: compute_scalb(cpustate, rn, rx, ry); break; - case 0xc1: compute_logb(cpustate, rn, rx); break; - case 0xc4: compute_recips(cpustate, rn, rx); break; - case 0xc5: compute_rsqrts(cpustate, rn, rx); break; - case 0xc9: compute_fix(cpustate, rn, rx); break; - case 0xca: compute_float(cpustate, rn, rx); break; - case 0xd9: compute_fix_scaled(cpustate, rn, rx, ry); break; - case 0xda: compute_float_scaled(cpustate, rn, rx, ry); break; - case 0xe1: compute_fmin(cpustate, rn, rx, ry); break; - case 0xe2: compute_fmax(cpustate, rn, rx, ry); break; - case 0xe3: compute_fclip(cpustate, rn, rx, ry); break; + case 0x01: compute_add(rn, rx, ry); break; + case 0x02: compute_sub(rn, rx, ry); break; + case 0x05: compute_add_ci(rn, rx, ry); break; + case 0x06: compute_sub_ci(rn, rx, ry); break; + case 0x0a: compute_comp(rx, ry); break; + case 0x21: compute_pass(rn, rx); break; + case 0x22: compute_neg(rn, rx); break; + case 0x29: compute_inc(rn, rx); break; + case 0x2a: compute_dec(rn, rx); break; + case 0x40: compute_and(rn, rx, ry); break; + case 0x41: compute_or(rn, rx, ry); break; + case 0x42: compute_xor(rn, rx, ry); break; + case 0x43: compute_not(rn, rx); break; + case 0x61: compute_min(rn, rx, ry); break; + case 0x62: compute_max(rn, rx, ry); break; + case 0x81: compute_fadd(rn, rx, ry); break; + case 0x82: compute_fsub(rn, rx, ry); break; + case 0x8a: compute_fcomp(rx, ry); break; + case 0x91: compute_fabs_plus(rn, rx, ry); break; + case 0xa1: compute_fpass(rn, rx); break; + case 0xa2: compute_fneg(rn, rx); break; + case 0xb0: compute_fabs(rn, rx); break; + case 0xbd: compute_scalb(rn, rx, ry); break; + case 0xc1: compute_logb(rn, rx); break; + case 0xc4: compute_recips(rn, rx); break; + case 0xc5: compute_rsqrts(rn, rx); break; + case 0xc9: compute_fix(rn, rx); break; + case 0xca: compute_float(rn, rx); break; + case 0xd9: compute_fix_scaled(rn, rx, ry); break; + case 0xda: compute_float_scaled(rn, rx, ry); break; + case 0xe1: compute_fmin(rn, rx, ry); break; + case 0xe2: compute_fmax(rn, rx, ry); break; + case 0xe3: compute_fclip(rn, rx, ry); break; case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: @@ -839,7 +837,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) /* Fixed-point Dual Add/Subtract */ int rs = (opcode >> 12) & 0xf; int ra = (opcode >> 8) & 0xf; - compute_dual_add_sub(cpustate, ra, rs, rx, ry); + compute_dual_add_sub(ra, rs, rx, ry); break; } @@ -849,11 +847,11 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) /* Floating-point Dual Add/Subtract */ int rs = (opcode >> 12) & 0xf; int ra = (opcode >> 8) & 0xf; - compute_dual_fadd_fsub(cpustate, ra, rs, rx, ry); + compute_dual_fadd_fsub(ra, rs, rx, ry); break; } - default: fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)\n", op, cpustate->pc, opcode); + default: fatalerror("SHARC: compute: unimplemented ALU operation %02X (%08X, %08X)\n", op, m_pc, opcode); } break; } @@ -864,18 +862,18 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) { switch(op) { - case 0x14: cpustate->mrf = 0; break; - case 0x16: cpustate->mrb = 0; break; + case 0x14: m_mrf = 0; break; + case 0x16: m_mrb = 0; break; - case 0x30: compute_fmul(cpustate, rn, rx, ry); break; - case 0x40: compute_mul_uuin(cpustate, rn, rx, ry); break; - case 0x70: compute_mul_ssin(cpustate, rn, rx, ry); break; + case 0x30: compute_fmul(rn, rx, ry); break; + case 0x40: compute_mul_uuin(rn, rx, ry); break; + case 0x70: compute_mul_ssin(rn, rx, ry); break; - case 0xb0: REG(rn) = compute_mrf_plus_mul_ssin(cpustate, rx, ry); break; - case 0xb2: REG(rn) = compute_mrb_plus_mul_ssin(cpustate, rx, ry); break; + case 0xb0: REG(rn) = compute_mrf_plus_mul_ssin(rx, ry); break; + case 0xb2: REG(rn) = compute_mrb_plus_mul_ssin(rx, ry); break; default: - fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)\n", op, cpustate->pc, opcode); + fatalerror("SHARC: compute: multiplier operation %02X not implemented ! (%08X, %08X)\n", op, m_pc, opcode); break; } break; @@ -885,7 +883,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) /* Shifter operations */ case 2: { - cpustate->astat &= ~(SZ|SV|SS); + m_astat &= ~(SZ|SV|SS); op >>= 2; switch(op) @@ -902,7 +900,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) REG(rn) = (shift < 32) ? (REG(rx) << shift) : 0; if (shift > 0) { - cpustate->astat |= SV; + m_astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -925,7 +923,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) (((UINT32)REG(rx) >> (32-s)) & ((UINT32)(0xffffffff) >> (32-s))); if (shift > 0) { - cpustate->astat |= SV; + m_astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -941,7 +939,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) REG(rn) = REG(rn) | ((shift < 32) ? (REG(rx) << shift) : 0); if (shift > 0) { - cpustate->astat |= SV; + m_astat |= SV; } } SET_FLAG_SZ(REG(rn)); @@ -958,7 +956,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -976,7 +974,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -992,7 +990,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) SET_FLAG_SZ(REG(rn)); if (bit+len > 32) { - cpustate->astat |= SV; + m_astat |= SV; } break; } @@ -1007,7 +1005,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) } else { - cpustate->astat |= SV; + m_astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -1023,7 +1021,7 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) } else { - cpustate->astat |= SV; + m_astat |= SV; } SET_FLAG_SZ(REG(rn)); break; @@ -1040,13 +1038,13 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) } else { - cpustate->astat |= SZ | SV; + m_astat |= SZ | SV; } break; } default: - fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)\n", op, cpustate->pc, opcode); + fatalerror("SHARC: compute: shift operation %02X not implemented ! (%08X, %08X)\n", op, m_pc, opcode); } break; } @@ -1057,222 +1055,222 @@ static void COMPUTE(SHARC_REGS *cpustate, UINT32 opcode) } } -INLINE void PUSH_PC(SHARC_REGS *cpustate, UINT32 pc) +void adsp21062_device::PUSH_PC(UINT32 pc) { - cpustate->pcstkp++; - if(cpustate->pcstkp >= 32) + m_pcstkp++; + if(m_pcstkp >= 32) { fatalerror("SHARC: PC Stack overflow!\n"); } - if (cpustate->pcstkp == 0) + if (m_pcstkp == 0) { - cpustate->stky |= 0x400000; + m_stky |= 0x400000; } else { - cpustate->stky &= ~0x400000; + m_stky &= ~0x400000; } - cpustate->pcstk = pc; - cpustate->pcstack[cpustate->pcstkp] = pc; + m_pcstk = pc; + m_pcstack[m_pcstkp] = pc; } -INLINE UINT32 POP_PC(SHARC_REGS *cpustate) +UINT32 adsp21062_device::POP_PC() { - cpustate->pcstk = cpustate->pcstack[cpustate->pcstkp]; + m_pcstk = m_pcstack[m_pcstkp]; - if(cpustate->pcstkp == 0) + if(m_pcstkp == 0) { fatalerror("SHARC: PC Stack underflow!\n"); } - cpustate->pcstkp--; + m_pcstkp--; - if (cpustate->pcstkp == 0) + if (m_pcstkp == 0) { - cpustate->stky |= 0x400000; + m_stky |= 0x400000; } else { - cpustate->stky &= ~0x400000; + m_stky &= ~0x400000; } - return cpustate->pcstk; + return m_pcstk; } -INLINE UINT32 TOP_PC(SHARC_REGS *cpustate) +UINT32 adsp21062_device::TOP_PC() { - return cpustate->pcstack[cpustate->pcstkp]; + return m_pcstack[m_pcstkp]; } -INLINE void PUSH_LOOP(SHARC_REGS *cpustate, UINT32 addr, UINT32 code, UINT32 type, UINT32 count) +void adsp21062_device::PUSH_LOOP(UINT32 addr, UINT32 code, UINT32 type, UINT32 count) { - cpustate->lstkp++; - if(cpustate->lstkp >= 6) + m_lstkp++; + if(m_lstkp >= 6) { fatalerror("SHARC: Loop Stack overflow!\n"); } - if (cpustate->lstkp == 0) + if (m_lstkp == 0) { - cpustate->stky |= 0x4000000; + m_stky |= 0x4000000; } else { - cpustate->stky &= ~0x4000000; + m_stky &= ~0x4000000; } - cpustate->lcstack[cpustate->lstkp] = count; - cpustate->lastack[cpustate->lstkp] = (type << 30) | (code << 24) | addr; - cpustate->curlcntr = count; + m_lcstack[m_lstkp] = count; + m_lastack[m_lstkp] = (type << 30) | (code << 24) | addr; + m_curlcntr = count; - cpustate->laddr.addr = addr; - cpustate->laddr.code = code; - cpustate->laddr.loop_type = type; + m_laddr.addr = addr; + m_laddr.code = code; + m_laddr.loop_type = type; } -INLINE void POP_LOOP(SHARC_REGS *cpustate) +void adsp21062_device::POP_LOOP() { - if(cpustate->lstkp == 0) + if(m_lstkp == 0) { fatalerror("SHARC: Loop Stack underflow!\n"); } - cpustate->lstkp--; + m_lstkp--; - if (cpustate->lstkp == 0) + if (m_lstkp == 0) { - cpustate->stky |= 0x4000000; + m_stky |= 0x4000000; } else { - cpustate->stky &= ~0x4000000; + m_stky &= ~0x4000000; } - cpustate->curlcntr = cpustate->lcstack[cpustate->lstkp]; + m_curlcntr = m_lcstack[m_lstkp]; - cpustate->laddr.addr = cpustate->lastack[cpustate->lstkp] & 0xffffff; - cpustate->laddr.code = (cpustate->lastack[cpustate->lstkp] >> 24) & 0x1f; - cpustate->laddr.loop_type = (cpustate->lastack[cpustate->lstkp] >> 30) & 0x3; + m_laddr.addr = m_lastack[m_lstkp] & 0xffffff; + m_laddr.code = (m_lastack[m_lstkp] >> 24) & 0x1f; + m_laddr.loop_type = (m_lastack[m_lstkp] >> 30) & 0x3; } -INLINE void PUSH_STATUS_STACK(SHARC_REGS *cpustate) +void adsp21062_device::PUSH_STATUS_STACK() { - cpustate->status_stkp++; - if (cpustate->status_stkp >= 5) + m_status_stkp++; + if (m_status_stkp >= 5) { fatalerror("SHARC: Status stack overflow!\n"); } - if (cpustate->status_stkp == 0) + if (m_status_stkp == 0) { - cpustate->stky |= 0x1000000; + m_stky |= 0x1000000; } else { - cpustate->stky &= ~0x1000000; + m_stky &= ~0x1000000; } - cpustate->status_stack[cpustate->status_stkp].mode1 = GET_UREG(cpustate, REG_MODE1); - cpustate->status_stack[cpustate->status_stkp].astat = GET_UREG(cpustate, REG_ASTAT); + m_status_stack[m_status_stkp].mode1 = GET_UREG(REG_MODE1); + m_status_stack[m_status_stkp].astat = GET_UREG(REG_ASTAT); } -INLINE void POP_STATUS_STACK(SHARC_REGS *cpustate) +void adsp21062_device::POP_STATUS_STACK() { - SET_UREG(cpustate, REG_MODE1, cpustate->status_stack[cpustate->status_stkp].mode1); - SET_UREG(cpustate, REG_ASTAT, cpustate->status_stack[cpustate->status_stkp].astat); + SET_UREG(REG_MODE1, m_status_stack[m_status_stkp].mode1); + SET_UREG(REG_ASTAT, m_status_stack[m_status_stkp].astat); - cpustate->status_stkp--; - if (cpustate->status_stkp < 0) + m_status_stkp--; + if (m_status_stkp < 0) { fatalerror("SHARC: Status stack underflow!\n"); } - if (cpustate->status_stkp == 0) + if (m_status_stkp == 0) { - cpustate->stky |= 0x1000000; + m_stky |= 0x1000000; } else { - cpustate->stky &= ~0x1000000; + m_stky &= ~0x1000000; } } -INLINE int IF_CONDITION_CODE(SHARC_REGS *cpustate, int cond) +int adsp21062_device::IF_CONDITION_CODE(int cond) { switch(cond) { - case 0x00: return cpustate->astat & AZ; /* EQ */ - case 0x01: return !(cpustate->astat & AZ) && (cpustate->astat & AN); /* LT */ - case 0x02: return (cpustate->astat & AZ) || (cpustate->astat & AN); /* LE */ - case 0x03: return (cpustate->astat & AC); /* AC */ - case 0x04: return (cpustate->astat & AV); /* AV */ - case 0x05: return (cpustate->astat & MV); /* MV */ - case 0x06: return (cpustate->astat & MN); /* MS */ - case 0x07: return (cpustate->astat & SV); /* SV */ - case 0x08: return (cpustate->astat & SZ); /* SZ */ - case 0x09: return (cpustate->flag[0] != 0); /* FLAG0 */ - case 0x0a: return (cpustate->flag[1] != 0); /* FLAG1 */ - case 0x0b: return (cpustate->flag[2] != 0); /* FLAG2 */ - case 0x0c: return (cpustate->flag[3] != 0); /* FLAG3 */ - case 0x0d: return (cpustate->astat & BTF); /* TF */ + case 0x00: return m_astat & AZ; /* EQ */ + case 0x01: return !(m_astat & AZ) && (m_astat & AN); /* LT */ + case 0x02: return (m_astat & AZ) || (m_astat & AN); /* LE */ + case 0x03: return (m_astat & AC); /* AC */ + case 0x04: return (m_astat & AV); /* AV */ + case 0x05: return (m_astat & MV); /* MV */ + case 0x06: return (m_astat & MN); /* MS */ + case 0x07: return (m_astat & SV); /* SV */ + case 0x08: return (m_astat & SZ); /* SZ */ + case 0x09: return (m_flag[0] != 0); /* FLAG0 */ + case 0x0a: return (m_flag[1] != 0); /* FLAG1 */ + case 0x0b: return (m_flag[2] != 0); /* FLAG2 */ + case 0x0c: return (m_flag[3] != 0); /* FLAG3 */ + case 0x0d: return (m_astat & BTF); /* TF */ case 0x0e: return 0; /* BM */ - case 0x0f: return (cpustate->curlcntr!=1); /* NOT LCE */ - case 0x10: return !(cpustate->astat & AZ); /* NOT EQUAL */ - case 0x11: return (cpustate->astat & AZ) || !(cpustate->astat & AN); /* GE */ - case 0x12: return !(cpustate->astat & AZ) && !(cpustate->astat & AN); /* GT */ - case 0x13: return !(cpustate->astat & AC); /* NOT AC */ - case 0x14: return !(cpustate->astat & AV); /* NOT AV */ - case 0x15: return !(cpustate->astat & MV); /* NOT MV */ - case 0x16: return !(cpustate->astat & MN); /* NOT MS */ - case 0x17: return !(cpustate->astat & SV); /* NOT SV */ - case 0x18: return !(cpustate->astat & SZ); /* NOT SZ */ - case 0x19: return (cpustate->flag[0] == 0); /* NOT FLAG0 */ - case 0x1a: return (cpustate->flag[1] == 0); /* NOT FLAG1 */ - case 0x1b: return (cpustate->flag[2] == 0); /* NOT FLAG2 */ - case 0x1c: return (cpustate->flag[3] == 0); /* NOT FLAG3 */ - case 0x1d: return !(cpustate->astat & BTF); /* NOT TF */ + case 0x0f: return (m_curlcntr!=1); /* NOT LCE */ + case 0x10: return !(m_astat & AZ); /* NOT EQUAL */ + case 0x11: return (m_astat & AZ) || !(m_astat & AN); /* GE */ + case 0x12: return !(m_astat & AZ) && !(m_astat & AN); /* GT */ + case 0x13: return !(m_astat & AC); /* NOT AC */ + case 0x14: return !(m_astat & AV); /* NOT AV */ + case 0x15: return !(m_astat & MV); /* NOT MV */ + case 0x16: return !(m_astat & MN); /* NOT MS */ + case 0x17: return !(m_astat & SV); /* NOT SV */ + case 0x18: return !(m_astat & SZ); /* NOT SZ */ + case 0x19: return (m_flag[0] == 0); /* NOT FLAG0 */ + case 0x1a: return (m_flag[1] == 0); /* NOT FLAG1 */ + case 0x1b: return (m_flag[2] == 0); /* NOT FLAG2 */ + case 0x1c: return (m_flag[3] == 0); /* NOT FLAG3 */ + case 0x1d: return !(m_astat & BTF); /* NOT TF */ case 0x1e: return 1; /* NOT BM */ case 0x1f: return 1; /* TRUE */ } return 1; } -INLINE int DO_CONDITION_CODE(SHARC_REGS *cpustate, int cond) +int adsp21062_device::DO_CONDITION_CODE(int cond) { switch(cond) { - case 0x00: return cpustate->astat & AZ; /* EQ */ - case 0x01: return !(cpustate->astat & AZ) && (cpustate->astat & AN); /* LT */ - case 0x02: return (cpustate->astat & AZ) || (cpustate->astat & AN); /* LE */ - case 0x03: return (cpustate->astat & AC); /* AC */ - case 0x04: return (cpustate->astat & AV); /* AV */ - case 0x05: return (cpustate->astat & MV); /* MV */ - case 0x06: return (cpustate->astat & MN); /* MS */ - case 0x07: return (cpustate->astat & SV); /* SV */ - case 0x08: return (cpustate->astat & SZ); /* SZ */ - case 0x09: return (cpustate->flag[0] != 0); /* FLAG0 */ - case 0x0a: return (cpustate->flag[1] != 0); /* FLAG1 */ - case 0x0b: return (cpustate->flag[2] != 0); /* FLAG2 */ - case 0x0c: return (cpustate->flag[3] != 0); /* FLAG3 */ - case 0x0d: return (cpustate->astat & BTF); /* TF */ + case 0x00: return m_astat & AZ; /* EQ */ + case 0x01: return !(m_astat & AZ) && (m_astat & AN); /* LT */ + case 0x02: return (m_astat & AZ) || (m_astat & AN); /* LE */ + case 0x03: return (m_astat & AC); /* AC */ + case 0x04: return (m_astat & AV); /* AV */ + case 0x05: return (m_astat & MV); /* MV */ + case 0x06: return (m_astat & MN); /* MS */ + case 0x07: return (m_astat & SV); /* SV */ + case 0x08: return (m_astat & SZ); /* SZ */ + case 0x09: return (m_flag[0] != 0); /* FLAG0 */ + case 0x0a: return (m_flag[1] != 0); /* FLAG1 */ + case 0x0b: return (m_flag[2] != 0); /* FLAG2 */ + case 0x0c: return (m_flag[3] != 0); /* FLAG3 */ + case 0x0d: return (m_astat & BTF); /* TF */ case 0x0e: return 0; /* BM */ - case 0x0f: return (cpustate->curlcntr==1); /* LCE */ - case 0x10: return !(cpustate->astat & AZ); /* NOT EQUAL */ - case 0x11: return (cpustate->astat & AZ) || !(cpustate->astat & AN); /* GE */ - case 0x12: return !(cpustate->astat & AZ) && !(cpustate->astat & AN); /* GT */ - case 0x13: return !(cpustate->astat & AC); /* NOT AC */ - case 0x14: return !(cpustate->astat & AV); /* NOT AV */ - case 0x15: return !(cpustate->astat & MV); /* NOT MV */ - case 0x16: return !(cpustate->astat & MN); /* NOT MS */ - case 0x17: return !(cpustate->astat & SV); /* NOT SV */ - case 0x18: return !(cpustate->astat & SZ); /* NOT SZ */ - case 0x19: return (cpustate->flag[0] == 0); /* NOT FLAG0 */ - case 0x1a: return (cpustate->flag[1] == 0); /* NOT FLAG1 */ - case 0x1b: return (cpustate->flag[2] == 0); /* NOT FLAG2 */ - case 0x1c: return (cpustate->flag[3] == 0); /* NOT FLAG3 */ - case 0x1d: return !(cpustate->astat & BTF); /* NOT TF */ + case 0x0f: return (m_curlcntr==1); /* LCE */ + case 0x10: return !(m_astat & AZ); /* NOT EQUAL */ + case 0x11: return (m_astat & AZ) || !(m_astat & AN); /* GE */ + case 0x12: return !(m_astat & AZ) && !(m_astat & AN); /* GT */ + case 0x13: return !(m_astat & AC); /* NOT AC */ + case 0x14: return !(m_astat & AV); /* NOT AV */ + case 0x15: return !(m_astat & MV); /* NOT MV */ + case 0x16: return !(m_astat & MN); /* NOT MS */ + case 0x17: return !(m_astat & SV); /* NOT SV */ + case 0x18: return !(m_astat & SZ); /* NOT SZ */ + case 0x19: return (m_flag[0] == 0); /* NOT FLAG0 */ + case 0x1a: return (m_flag[1] == 0); /* NOT FLAG1 */ + case 0x1b: return (m_flag[2] == 0); /* NOT FLAG2 */ + case 0x1c: return (m_flag[3] == 0); /* NOT FLAG3 */ + case 0x1d: return !(m_astat & BTF); /* NOT TF */ case 0x1e: return 1; /* NOT BM */ case 0x1f: return 0; /* FALSE (FOREVER) */ } @@ -1283,17 +1281,17 @@ INLINE int DO_CONDITION_CODE(SHARC_REGS *cpustate, int cond) /* | 001xxxxxx | */ /* compute / dreg <-> DM / dreg <-> PM */ -static void sharcop_compute_dreg_dm_dreg_pm(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_dreg_dm_dreg_pm() { - int pm_dreg = (cpustate->opcode >> 23) & 0xf; - int pmm = (cpustate->opcode >> 27) & 0x7; - int pmi = (cpustate->opcode >> 30) & 0x7; - int dm_dreg = (cpustate->opcode >> 33) & 0xf; - int dmm = (cpustate->opcode >> 38) & 0x7; - int dmi = (cpustate->opcode >> 41) & 0x7; - int pmd = (cpustate->opcode >> 37) & 0x1; - int dmd = (cpustate->opcode >> 44) & 0x1; - int compute = cpustate->opcode & 0x7fffff; + int pm_dreg = (m_opcode >> 23) & 0xf; + int pmm = (m_opcode >> 27) & 0x7; + int pmi = (m_opcode >> 30) & 0x7; + int dm_dreg = (m_opcode >> 33) & 0xf; + int dmm = (m_opcode >> 38) & 0x7; + int dmi = (m_opcode >> 41) & 0x7; + int pmd = (m_opcode >> 37) & 0x1; + int dmd = (m_opcode >> 44) & 0x1; + int compute = m_opcode & 0x7fffff; /* due to parallelity issues, source DREGs must be saved */ /* because the compute operation may change them */ @@ -1302,31 +1300,31 @@ static void sharcop_compute_dreg_dm_dreg_pm(SHARC_REGS *cpustate) if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (pmd) // dreg -> PM { - pm_write32(cpustate, PM_REG_I(pmi), parallel_pm_dreg); + pm_write32(PM_REG_I(pmi), parallel_pm_dreg); PM_REG_I(pmi) += PM_REG_M(pmm); UPDATE_CIRCULAR_BUFFER_PM(pmi); } else // PM -> dreg { - REG(pm_dreg) = pm_read32(cpustate, PM_REG_I(pmi)); + REG(pm_dreg) = pm_read32(PM_REG_I(pmi)); PM_REG_I(pmi) += PM_REG_M(pmm); UPDATE_CIRCULAR_BUFFER_PM(pmi); } if (dmd) // dreg -> DM { - dm_write32(cpustate, DM_REG_I(dmi), parallel_dm_dreg); + dm_write32(DM_REG_I(dmi), parallel_dm_dreg); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } else // DM -> dreg { - REG(dm_dreg) = dm_read32(cpustate, DM_REG_I(dmi)); + REG(dm_dreg) = dm_read32(DM_REG_I(dmi)); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } @@ -1336,14 +1334,14 @@ static void sharcop_compute_dreg_dm_dreg_pm(SHARC_REGS *cpustate) /* | 00000001x | */ /* compute */ -static void sharcop_compute(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int compute = m_opcode & 0x7fffff; - if (IF_CONDITION_CODE(cpustate, cond) && compute != 0) + if (IF_CONDITION_CODE(cond) && compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } @@ -1351,25 +1349,25 @@ static void sharcop_compute(SHARC_REGS *cpustate) /* | 010xxxxxx | */ /* compute / ureg <-> DM|PM, pre-modify */ -static void sharcop_compute_ureg_dmpm_premod(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_ureg_dmpm_premod() { - int i = (cpustate->opcode >> 41) & 0x7; - int m = (cpustate->opcode >> 38) & 0x7; - int cond = (cpustate->opcode >> 33) & 0x1f; - int g = (cpustate->opcode >> 32) & 0x1; - int d = (cpustate->opcode >> 31) & 0x1; - int ureg = (cpustate->opcode >> 23) & 0xff; - int compute = cpustate->opcode & 0x7fffff; + int i = (m_opcode >> 41) & 0x7; + int m = (m_opcode >> 38) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int g = (m_opcode >> 32) & 0x1; + int d = (m_opcode >> 31) & 0x1; + int ureg = (m_opcode >> 23) & 0xff; + int compute = m_opcode & 0x7fffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { /* due to parallelity issues, source UREG must be saved */ /* because the compute operation may change it */ - UINT32 parallel_ureg = GET_UREG(cpustate, ureg); + UINT32 parallel_ureg = GET_UREG(ureg); if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (g) /* PM */ @@ -1378,22 +1376,22 @@ static void sharcop_compute_ureg_dmpm_premod(SHARC_REGS *cpustate) { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - pm_write48(cpustate, PM_REG_I(i)+PM_REG_M(m), cpustate->px); + pm_write48(PM_REG_I(i)+PM_REG_M(m), m_px); } else { - pm_write32(cpustate, PM_REG_I(i)+PM_REG_M(m), parallel_ureg); + pm_write32(PM_REG_I(i)+PM_REG_M(m), parallel_ureg); } } else /* PM <- ureg */ { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - cpustate->px = pm_read48(cpustate, PM_REG_I(i)+PM_REG_M(m)); + m_px = pm_read48(PM_REG_I(i)+PM_REG_M(m)); } else { - SET_UREG(cpustate, ureg, pm_read32(cpustate, PM_REG_I(i)+PM_REG_M(m))); + SET_UREG(ureg, pm_read32(PM_REG_I(i)+PM_REG_M(m))); } } } @@ -1401,36 +1399,36 @@ static void sharcop_compute_ureg_dmpm_premod(SHARC_REGS *cpustate) { if (d) /* ureg -> DM */ { - dm_write32(cpustate, DM_REG_I(i)+DM_REG_M(m), parallel_ureg); + dm_write32(DM_REG_I(i)+DM_REG_M(m), parallel_ureg); } else /* DM <- ureg */ { - SET_UREG(cpustate, ureg, dm_read32(cpustate, DM_REG_I(i)+DM_REG_M(m))); + SET_UREG(ureg, dm_read32(DM_REG_I(i)+DM_REG_M(m))); } } } } /* compute / ureg <-> DM|PM, post-modify */ -static void sharcop_compute_ureg_dmpm_postmod(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_ureg_dmpm_postmod() { - int i = (cpustate->opcode >> 41) & 0x7; - int m = (cpustate->opcode >> 38) & 0x7; - int cond = (cpustate->opcode >> 33) & 0x1f; - int g = (cpustate->opcode >> 32) & 0x1; - int d = (cpustate->opcode >> 31) & 0x1; - int ureg = (cpustate->opcode >> 23) & 0xff; - int compute = cpustate->opcode & 0x7fffff; + int i = (m_opcode >> 41) & 0x7; + int m = (m_opcode >> 38) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int g = (m_opcode >> 32) & 0x1; + int d = (m_opcode >> 31) & 0x1; + int ureg = (m_opcode >> 23) & 0xff; + int compute = m_opcode & 0x7fffff; - if(IF_CONDITION_CODE(cpustate, cond)) + if(IF_CONDITION_CODE(cond)) { /* due to parallelity issues, source UREG must be saved */ /* because the compute operation may change it */ - UINT32 parallel_ureg = GET_UREG(cpustate, ureg); + UINT32 parallel_ureg = GET_UREG(ureg); if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (g) /* PM */ @@ -1439,11 +1437,11 @@ static void sharcop_compute_ureg_dmpm_postmod(SHARC_REGS *cpustate) { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - pm_write48(cpustate, PM_REG_I(i), cpustate->px); + pm_write48(PM_REG_I(i), m_px); } else { - pm_write32(cpustate, PM_REG_I(i), parallel_ureg); + pm_write32(PM_REG_I(i), parallel_ureg); } PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); @@ -1452,11 +1450,11 @@ static void sharcop_compute_ureg_dmpm_postmod(SHARC_REGS *cpustate) { if (ureg == 0xdb) /* PX register access is always 48-bit */ { - cpustate->px = pm_read48(cpustate, PM_REG_I(i)); + m_px = pm_read48(PM_REG_I(i)); } else { - SET_UREG(cpustate, ureg, pm_read32(cpustate, PM_REG_I(i))); + SET_UREG(ureg, pm_read32(PM_REG_I(i))); } PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); @@ -1466,13 +1464,13 @@ static void sharcop_compute_ureg_dmpm_postmod(SHARC_REGS *cpustate) { if (d) /* ureg -> DM */ { - dm_write32(cpustate, DM_REG_I(i), parallel_ureg); + dm_write32(DM_REG_I(i), parallel_ureg); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } else /* DM <- ureg */ { - SET_UREG(cpustate, ureg, dm_read32(cpustate, DM_REG_I(i))); + SET_UREG(ureg, dm_read32(DM_REG_I(i))); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } @@ -1484,129 +1482,129 @@ static void sharcop_compute_ureg_dmpm_postmod(SHARC_REGS *cpustate) /* | 0110xxxxx | */ /* compute / dreg <- DM, immediate modify */ -static void sharcop_compute_dm_to_dreg_immmod(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_dm_to_dreg_immmod() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int u = (cpustate->opcode >> 38) & 0x1; - int dreg = (cpustate->opcode >> 23) & 0xf; - int i = (cpustate->opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int u = (m_opcode >> 38) & 0x1; + int dreg = (m_opcode >> 23) & 0xf; + int i = (m_opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((m_opcode >> 27) & 0x3f); + int compute = m_opcode & 0x7fffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (u) /* post-modify with update */ { - REG(dreg) = dm_read32(cpustate, DM_REG_I(i)); + REG(dreg) = dm_read32(DM_REG_I(i)); DM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_DM(i); } else /* pre-modify, no update */ { - REG(dreg) = dm_read32(cpustate, DM_REG_I(i) + mod); + REG(dreg) = dm_read32(DM_REG_I(i) + mod); } } } /* compute / dreg -> DM, immediate modify */ -static void sharcop_compute_dreg_to_dm_immmod(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_dreg_to_dm_immmod() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int u = (cpustate->opcode >> 38) & 0x1; - int dreg = (cpustate->opcode >> 23) & 0xf; - int i = (cpustate->opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int u = (m_opcode >> 38) & 0x1; + int dreg = (m_opcode >> 23) & 0xf; + int i = (m_opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((m_opcode >> 27) & 0x3f); + int compute = m_opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the shift operation may change it */ UINT32 parallel_dreg = REG(dreg); - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (u) /* post-modify with update */ { - dm_write32(cpustate, DM_REG_I(i), parallel_dreg); + dm_write32(DM_REG_I(i), parallel_dreg); DM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_DM(i); } else /* pre-modify, no update */ { - dm_write32(cpustate, DM_REG_I(i) + mod, parallel_dreg); + dm_write32(DM_REG_I(i) + mod, parallel_dreg); } } } /* compute / dreg <- PM, immediate modify */ -static void sharcop_compute_pm_to_dreg_immmod(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_pm_to_dreg_immmod() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int u = (cpustate->opcode >> 38) & 0x1; - int dreg = (cpustate->opcode >> 23) & 0xf; - int i = (cpustate->opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int u = (m_opcode >> 38) & 0x1; + int dreg = (m_opcode >> 23) & 0xf; + int i = (m_opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((m_opcode >> 27) & 0x3f); + int compute = m_opcode & 0x7fffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (u) /* post-modify with update */ { - REG(dreg) = pm_read32(cpustate, PM_REG_I(i)); + REG(dreg) = pm_read32(PM_REG_I(i)); PM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_PM(i); } else /* pre-modify, no update */ { - REG(dreg) = pm_read32(cpustate, PM_REG_I(i) + mod); + REG(dreg) = pm_read32(PM_REG_I(i) + mod); } } } /* compute / dreg -> PM, immediate modify */ -static void sharcop_compute_dreg_to_pm_immmod(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_dreg_to_pm_immmod() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int u = (cpustate->opcode >> 38) & 0x1; - int dreg = (cpustate->opcode >> 23) & 0xf; - int i = (cpustate->opcode >> 41) & 0x7; - int mod = SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f); - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int u = (m_opcode >> 38) & 0x1; + int dreg = (m_opcode >> 23) & 0xf; + int i = (m_opcode >> 41) & 0x7; + int mod = SIGN_EXTEND6((m_opcode >> 27) & 0x3f); + int compute = m_opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the compute operation may change it */ UINT32 parallel_dreg = REG(dreg); - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (u) /* post-modify with update */ { - pm_write32(cpustate, PM_REG_I(i), parallel_dreg); + pm_write32(PM_REG_I(i), parallel_dreg); PM_REG_I(i) += mod; UPDATE_CIRCULAR_BUFFER_PM(i); } else /* pre-modify, no update */ { - pm_write32(cpustate, PM_REG_I(i) + mod, parallel_dreg); + pm_write32(PM_REG_I(i) + mod, parallel_dreg); } } } @@ -1615,25 +1613,25 @@ static void sharcop_compute_dreg_to_pm_immmod(SHARC_REGS *cpustate) /* | 0111xxxxx | */ /* compute / ureg <-> ureg */ -static void sharcop_compute_ureg_to_ureg(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_ureg_to_ureg() { - int src_ureg = (cpustate->opcode >> 36) & 0xff; - int dst_ureg = (cpustate->opcode >> 23) & 0xff; - int cond = (cpustate->opcode >> 31) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; + int src_ureg = (m_opcode >> 36) & 0xff; + int dst_ureg = (m_opcode >> 23) & 0xff; + int cond = (m_opcode >> 31) & 0x1f; + int compute = m_opcode & 0x7fffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { /* due to parallelity issues, source UREG must be saved */ /* because the compute operation may change it */ - UINT32 parallel_ureg = GET_UREG(cpustate, src_ureg); + UINT32 parallel_ureg = GET_UREG(src_ureg); if (compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } - SET_UREG(cpustate, dst_ureg, parallel_ureg); + SET_UREG(dst_ureg, parallel_ureg); } } @@ -1641,38 +1639,38 @@ static void sharcop_compute_ureg_to_ureg(SHARC_REGS *cpustate) /* | 1000xxxxx | */ /* immediate shift / dreg <-> DM|PM */ -static void sharcop_imm_shift_dreg_dmpm(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_imm_shift_dreg_dmpm() { - int i = (cpustate->opcode >> 41) & 0x7; - int m = (cpustate->opcode >> 38) & 0x7; - int g = (cpustate->opcode >> 32) & 0x1; - int d = (cpustate->opcode >> 31) & 0x1; - int dreg = (cpustate->opcode >> 23) & 0xf; - int cond = (cpustate->opcode >> 33) & 0x1f; - int data = ((cpustate->opcode >> 8) & 0xff) | ((cpustate->opcode >> 19) & 0xf00); - int shiftop = (cpustate->opcode >> 16) & 0x3f; - int rn = (cpustate->opcode >> 4) & 0xf; - int rx = (cpustate->opcode & 0xf); + int i = (m_opcode >> 41) & 0x7; + int m = (m_opcode >> 38) & 0x7; + int g = (m_opcode >> 32) & 0x1; + int d = (m_opcode >> 31) & 0x1; + int dreg = (m_opcode >> 23) & 0xf; + int cond = (m_opcode >> 33) & 0x1f; + int data = ((m_opcode >> 8) & 0xff) | ((m_opcode >> 19) & 0xf00); + int shiftop = (m_opcode >> 16) & 0x3f; + int rn = (m_opcode >> 4) & 0xf; + int rx = (m_opcode & 0xf); - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { /* due to parallelity issues, source REG must be saved */ /* because the shift operation may change it */ UINT32 parallel_dreg = REG(dreg); - SHIFT_OPERATION_IMM(cpustate, shiftop, data, rn, rx); + SHIFT_OPERATION_IMM(shiftop, data, rn, rx); if (g) /* PM */ { if (d) /* dreg -> PM */ { - pm_write32(cpustate, PM_REG_I(i), parallel_dreg); + pm_write32(PM_REG_I(i), parallel_dreg); PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); } else /* PM <- dreg */ { - REG(dreg) = pm_read32(cpustate, PM_REG_I(i)); + REG(dreg) = pm_read32(PM_REG_I(i)); PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); } @@ -1681,13 +1679,13 @@ static void sharcop_imm_shift_dreg_dmpm(SHARC_REGS *cpustate) { if (d) /* dreg -> DM */ { - dm_write32(cpustate, DM_REG_I(i), parallel_dreg); + dm_write32(DM_REG_I(i), parallel_dreg); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } else /* DM <- dreg */ { - REG(dreg) = dm_read32(cpustate, DM_REG_I(i)); + REG(dreg) = dm_read32(DM_REG_I(i)); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } @@ -1699,17 +1697,17 @@ static void sharcop_imm_shift_dreg_dmpm(SHARC_REGS *cpustate) /* | 00000010x | */ /* immediate shift */ -static void sharcop_imm_shift(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_imm_shift() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int data = ((cpustate->opcode >> 8) & 0xff) | ((cpustate->opcode >> 19) & 0xf00); - int shiftop = (cpustate->opcode >> 16) & 0x3f; - int rn = (cpustate->opcode >> 4) & 0xf; - int rx = (cpustate->opcode & 0xf); + int cond = (m_opcode >> 33) & 0x1f; + int data = ((m_opcode >> 8) & 0xff) | ((m_opcode >> 19) & 0xf00); + int shiftop = (m_opcode >> 16) & 0x3f; + int rn = (m_opcode >> 4) & 0xf; + int rx = (m_opcode & 0xf); - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { - SHIFT_OPERATION_IMM(cpustate, shiftop, data, rn, rx); + SHIFT_OPERATION_IMM(shiftop, data, rn, rx); } } @@ -1717,19 +1715,19 @@ static void sharcop_imm_shift(SHARC_REGS *cpustate) /* | 00000100x | */ /* compute / modify */ -static void sharcop_compute_modify(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_compute_modify() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; - int g = (cpustate->opcode >> 38) & 0x1; - int m = (cpustate->opcode >> 27) & 0x7; - int i = (cpustate->opcode >> 30) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int compute = m_opcode & 0x7fffff; + int g = (m_opcode >> 38) & 0x1; + int m = (m_opcode >> 27) & 0x7; + int i = (m_opcode >> 30) & 0x7; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute != 0) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (g) /* Modify PM */ @@ -1749,66 +1747,66 @@ static void sharcop_compute_modify(SHARC_REGS *cpustate) /* | 00000110x | */ /* direct call to absolute address */ -static void sharcop_direct_call(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_direct_call() { - int j = (cpustate->opcode >> 26) & 0x1; - int cond = (cpustate->opcode >> 33) & 0x1f; - UINT32 address = cpustate->opcode & 0xffffff; + int j = (m_opcode >> 26) & 0x1; + int cond = (m_opcode >> 33) & 0x1f; + UINT32 address = m_opcode & 0xffffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (j) { - //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(cpustate, address); + //PUSH_PC(m_pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(m_nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(address); } else { - //PUSH_PC(cpustate, cpustate->pc+1); - PUSH_PC(cpustate, cpustate->daddr); - CHANGE_PC(cpustate, address); + //PUSH_PC(m_pc+1); + PUSH_PC(m_daddr); + CHANGE_PC(address); } } } /* direct jump to absolute address */ -static void sharcop_direct_jump(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_direct_jump() { - int la = (cpustate->opcode >> 38) & 0x1; - int ci = (cpustate->opcode >> 24) & 0x1; - int j = (cpustate->opcode >> 26) & 0x1; - int cond = (cpustate->opcode >> 33) & 0x1f; - UINT32 address = cpustate->opcode & 0xffffff; + int la = (m_opcode >> 38) & 0x1; + int ci = (m_opcode >> 24) & 0x1; + int j = (m_opcode >> 26) & 0x1; + int cond = (m_opcode >> 33) & 0x1f; + UINT32 address = m_opcode & 0xffffff; - if(IF_CONDITION_CODE(cpustate, cond)) + if(IF_CONDITION_CODE(cond)) { // Clear Interrupt if (ci) { // TODO: anything else? - if (cpustate->status_stkp > 0) + if (m_status_stkp > 0) { - POP_STATUS_STACK(cpustate); + POP_STATUS_STACK(); } - cpustate->interrupt_active = 0; - cpustate->irptl &= ~(1 << cpustate->active_irq_num); + m_interrupt_active = 0; + m_irptl &= ~(1 << m_active_irq_num); } if (la) { - POP_PC(cpustate); - POP_LOOP(cpustate); + POP_PC(); + POP_LOOP(); } if (j) { - CHANGE_PC_DELAYED(cpustate, address); + CHANGE_PC_DELAYED(address); } else { - CHANGE_PC(cpustate, address); + CHANGE_PC(address); } } } @@ -1817,64 +1815,64 @@ static void sharcop_direct_jump(SHARC_REGS *cpustate) /* | 00000111x | */ /* direct call to relative address */ -static void sharcop_relative_call(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_relative_call() { - int j = (cpustate->opcode >> 26) & 0x1; - int cond = (cpustate->opcode >> 33) & 0x1f; - UINT32 address = cpustate->opcode & 0xffffff; + int j = (m_opcode >> 26) & 0x1; + int cond = (m_opcode >> 33) & 0x1f; + UINT32 address = m_opcode & 0xffffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (j) { - PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND24(address)); + PUSH_PC(m_pc+3); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(m_pc + SIGN_EXTEND24(address)); } else { - PUSH_PC(cpustate, cpustate->pc+1); - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND24(address)); + PUSH_PC(m_pc+1); + CHANGE_PC(m_pc + SIGN_EXTEND24(address)); } } } /* direct jump to relative address */ -static void sharcop_relative_jump(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_relative_jump() { - int la = (cpustate->opcode >> 38) & 0x1; - int ci = (cpustate->opcode >> 24) & 0x1; - int j = (cpustate->opcode >> 26) & 0x1; - int cond = (cpustate->opcode >> 33) & 0x1f; - UINT32 address = cpustate->opcode & 0xffffff; + int la = (m_opcode >> 38) & 0x1; + int ci = (m_opcode >> 24) & 0x1; + int j = (m_opcode >> 26) & 0x1; + int cond = (m_opcode >> 33) & 0x1f; + UINT32 address = m_opcode & 0xffffff; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { // Clear Interrupt if (ci) { // TODO: anything else? - if (cpustate->status_stkp > 0) + if (m_status_stkp > 0) { - POP_STATUS_STACK(cpustate); + POP_STATUS_STACK(); } - cpustate->interrupt_active = 0; - cpustate->irptl &= ~(1 << cpustate->active_irq_num); + m_interrupt_active = 0; + m_irptl &= ~(1 << m_active_irq_num); } if (la) { - POP_PC(cpustate); - POP_LOOP(cpustate); + POP_PC(); + POP_LOOP(); } if (j) { - CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND24(address)); + CHANGE_PC_DELAYED(m_pc + SIGN_EXTEND24(address)); } else { - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND24(address)); + CHANGE_PC(m_pc + SIGN_EXTEND24(address)); } } } @@ -1883,139 +1881,139 @@ static void sharcop_relative_jump(SHARC_REGS *cpustate) /* | 00001000x | */ /* indirect jump */ -static void sharcop_indirect_jump(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_indirect_jump() { - int la = (cpustate->opcode >> 38) & 0x1; - int ci = (cpustate->opcode >> 24) & 0x1; - int j = (cpustate->opcode >> 26) & 0x1; - int e = (cpustate->opcode >> 25) & 0x1; - int pmi = (cpustate->opcode >> 30) & 0x7; - int pmm = (cpustate->opcode >> 27) & 0x7; - int cond = (cpustate->opcode >> 33) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; + int la = (m_opcode >> 38) & 0x1; + int ci = (m_opcode >> 24) & 0x1; + int j = (m_opcode >> 26) & 0x1; + int e = (m_opcode >> 25) & 0x1; + int pmi = (m_opcode >> 30) & 0x7; + int pmm = (m_opcode >> 27) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int compute = m_opcode & 0x7fffff; // Clear Interrupt if (ci) { // TODO: anything else? - if (cpustate->status_stkp > 0) + if (m_status_stkp > 0) { - POP_STATUS_STACK(cpustate); + POP_STATUS_STACK(); } - cpustate->interrupt_active = 0; - cpustate->irptl &= ~(1 << cpustate->active_irq_num); + m_interrupt_active = 0; + m_irptl &= ~(1 << m_active_irq_num); } if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (la) { - POP_PC(cpustate); - POP_LOOP(cpustate); + POP_PC(); + POP_LOOP(); } if(j) { - CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); } } else { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (la) { - POP_PC(cpustate); - POP_LOOP(cpustate); + POP_PC(); + POP_LOOP(); } if(j) { - CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); } } } } /* indirect call */ -static void sharcop_indirect_call(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_indirect_call() { - int j = (cpustate->opcode >> 26) & 0x1; - int e = (cpustate->opcode >> 25) & 0x1; - int pmi = (cpustate->opcode >> 30) & 0x7; - int pmm = (cpustate->opcode >> 27) & 0x7; - int cond = (cpustate->opcode >> 33) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; + int j = (m_opcode >> 26) & 0x1; + int e = (m_opcode >> 25) & 0x1; + int pmi = (m_opcode >> 30) & 0x7; + int pmm = (m_opcode >> 27) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int compute = m_opcode & 0x7fffff; if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (j) { - //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(m_pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(m_nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - //PUSH_PC(cpustate, cpustate->pc+1); - PUSH_PC(cpustate, cpustate->daddr); - CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(m_pc+1); + PUSH_PC(m_daddr); + CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); } } else { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (j) { - //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(m_pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(m_nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - //PUSH_PC(cpustate, cpustate->pc+1); - PUSH_PC(cpustate, cpustate->daddr); - CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + //PUSH_PC(m_pc+1); + PUSH_PC(m_daddr); + CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); } } } @@ -2025,135 +2023,135 @@ static void sharcop_indirect_call(SHARC_REGS *cpustate) /* | 00001001x | */ /* indirect jump to relative address */ -static void sharcop_relative_jump_compute(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_relative_jump_compute() { - int la = (cpustate->opcode >> 38) & 0x1; - int ci = (cpustate->opcode >> 24) & 0x1; - int j = (cpustate->opcode >> 26) & 0x1; - int e = (cpustate->opcode >> 25) & 0x1; - int cond = (cpustate->opcode >> 33) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; + int la = (m_opcode >> 38) & 0x1; + int ci = (m_opcode >> 24) & 0x1; + int j = (m_opcode >> 26) & 0x1; + int e = (m_opcode >> 25) & 0x1; + int cond = (m_opcode >> 33) & 0x1f; + int compute = m_opcode & 0x7fffff; // Clear Interrupt if (ci) { // TODO: anything else? - if (cpustate->status_stkp > 0) + if (m_status_stkp > 0) { - POP_STATUS_STACK(cpustate); + POP_STATUS_STACK(); } - cpustate->interrupt_active = 0; - cpustate->irptl &= ~(1 << cpustate->active_irq_num); + m_interrupt_active = 0; + m_irptl &= ~(1 << m_active_irq_num); } if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (la) { - POP_PC(cpustate); - POP_LOOP(cpustate); + POP_PC(); + POP_LOOP(); } if (j) { - CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + CHANGE_PC_DELAYED(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } else { - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + CHANGE_PC(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } } else { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (la) { - POP_PC(cpustate); - POP_LOOP(cpustate); + POP_PC(); + POP_LOOP(); } if (j) { - CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + CHANGE_PC_DELAYED(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } else { - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + CHANGE_PC(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } } } } /* indirect call to relative address */ -static void sharcop_relative_call_compute(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_relative_call_compute() { - int j = (cpustate->opcode >> 26) & 0x1; - int e = (cpustate->opcode >> 25) & 0x1; - int cond = (cpustate->opcode >> 33) & 0x1f; - int compute = cpustate->opcode & 0x7fffff; + int j = (m_opcode >> 26) & 0x1; + int e = (m_opcode >> 25) & 0x1; + int cond = (m_opcode >> 33) & 0x1f; + int compute = m_opcode & 0x7fffff; if (e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (j) { - //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + //PUSH_PC(m_pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(m_nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } else { - //PUSH_PC(cpustate, cpustate->pc+1); - PUSH_PC(cpustate, cpustate->daddr); - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + //PUSH_PC(m_pc+1); + PUSH_PC(m_daddr); + CHANGE_PC(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } } else { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (j) { - //PUSH_PC(cpustate, cpustate->pc+3); /* 1 instruction + 2 delayed instructions */ - PUSH_PC(cpustate, cpustate->nfaddr); /* 1 instruction + 2 delayed instructions */ - CHANGE_PC_DELAYED(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + //PUSH_PC(m_pc+3); /* 1 instruction + 2 delayed instructions */ + PUSH_PC(m_nfaddr); /* 1 instruction + 2 delayed instructions */ + CHANGE_PC_DELAYED(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } else { - //PUSH_PC(cpustate, cpustate->pc+1); - PUSH_PC(cpustate, cpustate->daddr); - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + //PUSH_PC(m_pc+1); + PUSH_PC(m_daddr); + CHANGE_PC(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } } } @@ -2163,41 +2161,41 @@ static void sharcop_relative_call_compute(SHARC_REGS *cpustate) /* | 110xxxxxx | */ /* indirect jump / compute / dreg <-> DM */ -static void sharcop_indirect_jump_compute_dreg_dm(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_indirect_jump_compute_dreg_dm() { - int d = (cpustate->opcode >> 44) & 0x1; - int dmi = (cpustate->opcode >> 41) & 0x7; - int dmm = (cpustate->opcode >> 38) & 0x7; - int pmi = (cpustate->opcode >> 30) & 0x7; - int pmm = (cpustate->opcode >> 27) & 0x7; - int cond = (cpustate->opcode >> 33) & 0x1f; - int dreg = (cpustate->opcode >> 23) & 0xf; + int d = (m_opcode >> 44) & 0x1; + int dmi = (m_opcode >> 41) & 0x7; + int dmm = (m_opcode >> 38) & 0x7; + int pmi = (m_opcode >> 30) & 0x7; + int pmm = (m_opcode >> 27) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int dreg = (m_opcode >> 23) & 0xf; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { - CHANGE_PC(cpustate, PM_REG_I(pmi) + PM_REG_M(pmm)); + CHANGE_PC(PM_REG_I(pmi) + PM_REG_M(pmm)); } else { - UINT32 compute = cpustate->opcode & 0x7fffff; + UINT32 compute = m_opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the compute operation may change it */ UINT32 parallel_dreg = REG(dreg); if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (d) /* dreg -> DM */ { - dm_write32(cpustate, DM_REG_I(dmi), parallel_dreg); + dm_write32(DM_REG_I(dmi), parallel_dreg); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } else /* DM <- dreg */ { - REG(dreg) = dm_read32(cpustate, DM_REG_I(dmi)); + REG(dreg) = dm_read32(DM_REG_I(dmi)); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } @@ -2208,39 +2206,39 @@ static void sharcop_indirect_jump_compute_dreg_dm(SHARC_REGS *cpustate) /* | 111xxxxxx | */ /* relative jump / compute / dreg <-> DM */ -static void sharcop_relative_jump_compute_dreg_dm(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_relative_jump_compute_dreg_dm() { - int d = (cpustate->opcode >> 44) & 0x1; - int dmi = (cpustate->opcode >> 41) & 0x7; - int dmm = (cpustate->opcode >> 38) & 0x7; - int cond = (cpustate->opcode >> 33) & 0x1f; - int dreg = (cpustate->opcode >> 23) & 0xf; + int d = (m_opcode >> 44) & 0x1; + int dmi = (m_opcode >> 41) & 0x7; + int dmm = (m_opcode >> 38) & 0x7; + int cond = (m_opcode >> 33) & 0x1f; + int dreg = (m_opcode >> 23) & 0xf; - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { - CHANGE_PC(cpustate, cpustate->pc + SIGN_EXTEND6((cpustate->opcode >> 27) & 0x3f)); + CHANGE_PC(m_pc + SIGN_EXTEND6((m_opcode >> 27) & 0x3f)); } else { - UINT32 compute = cpustate->opcode & 0x7fffff; + UINT32 compute = m_opcode & 0x7fffff; /* due to parallelity issues, source REG must be saved */ /* because the compute operation may change it */ UINT32 parallel_dreg = REG(dreg); if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (d) /* dreg -> DM */ { - dm_write32(cpustate, DM_REG_I(dmi), parallel_dreg); + dm_write32(DM_REG_I(dmi), parallel_dreg); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } else /* DM <- dreg */ { - REG(dreg) = dm_read32(cpustate, DM_REG_I(dmi)); + REG(dreg) = dm_read32(DM_REG_I(dmi)); DM_REG_I(dmi) += DM_REG_M(dmm); UPDATE_CIRCULAR_BUFFER_DM(dmi); } @@ -2251,54 +2249,54 @@ static void sharcop_relative_jump_compute_dreg_dm(SHARC_REGS *cpustate) /* | 00001010x | */ /* return from subroutine / compute */ -static void sharcop_rts(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_rts() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int j = (cpustate->opcode >> 26) & 0x1; - int e = (cpustate->opcode >> 25) & 0x1; - //int lr = (cpustate->opcode >> 24) & 0x1; - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int j = (m_opcode >> 26) & 0x1; + int e = (m_opcode >> 25) & 0x1; + //int lr = (m_opcode >> 24) & 0x1; + int compute = m_opcode & 0x7fffff; //if(lr) // fatalerror("SHARC: rts: loop reentry not implemented!\n"); if (e) /* IF...ELSE */ { - if(IF_CONDITION_CODE(cpustate, cond)) + if(IF_CONDITION_CODE(cond)) { if (j) { - CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); + CHANGE_PC_DELAYED(POP_PC()); } else { - CHANGE_PC(cpustate, POP_PC(cpustate)); + CHANGE_PC(POP_PC()); } } else { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (j) { - CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); + CHANGE_PC_DELAYED(POP_PC()); } else { - CHANGE_PC(cpustate, POP_PC(cpustate)); + CHANGE_PC(POP_PC()); } } } @@ -2308,74 +2306,74 @@ static void sharcop_rts(SHARC_REGS *cpustate) /* | 00001011x | */ /* return from interrupt / compute */ -static void sharcop_rti(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_rti() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int j = (cpustate->opcode >> 26) & 0x1; - int e = (cpustate->opcode >> 25) & 0x1; - int compute = cpustate->opcode & 0x7fffff; + int cond = (m_opcode >> 33) & 0x1f; + int j = (m_opcode >> 26) & 0x1; + int e = (m_opcode >> 25) & 0x1; + int compute = m_opcode & 0x7fffff; - cpustate->irptl &= ~(1 << cpustate->active_irq_num); + m_irptl &= ~(1 << m_active_irq_num); if(e) /* IF...ELSE */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (j) { - CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); + CHANGE_PC_DELAYED(POP_PC()); } else { - CHANGE_PC(cpustate, POP_PC(cpustate)); + CHANGE_PC(POP_PC()); } } else { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } } } else /* IF */ { - if (IF_CONDITION_CODE(cpustate, cond)) + if (IF_CONDITION_CODE(cond)) { if (compute) { - COMPUTE(cpustate, compute); + COMPUTE(compute); } if (j) { - CHANGE_PC_DELAYED(cpustate, POP_PC(cpustate)); + CHANGE_PC_DELAYED(POP_PC()); } else { - CHANGE_PC(cpustate, POP_PC(cpustate)); + CHANGE_PC(POP_PC()); } } } - if (cpustate->status_stkp > 0) + if (m_status_stkp > 0) { - POP_STATUS_STACK(cpustate); + POP_STATUS_STACK(); } - cpustate->interrupt_active = 0; - check_interrupts(cpustate); + m_interrupt_active = 0; + check_interrupts(); } /*****************************************************************************/ /* | 00001100x | */ /* do until counter expired, LCNTR immediate */ -static void sharcop_do_until_counter_imm(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_do_until_counter_imm() { - UINT16 data = (UINT16)(cpustate->opcode >> 24); - int offset = SIGN_EXTEND24(cpustate->opcode & 0xffffff); - UINT32 address = cpustate->pc + offset; + UINT16 data = (UINT16)(m_opcode >> 24); + int offset = SIGN_EXTEND24(m_opcode & 0xffffff); + UINT32 address = m_pc + offset; int type; int cond = 0xf; /* until LCE (loop counter expired */ int distance = abs(offset); @@ -2393,11 +2391,11 @@ static void sharcop_do_until_counter_imm(SHARC_REGS *cpustate) type = 3; } - cpustate->lcntr = data; - if (cpustate->lcntr > 0) + m_lcntr = data; + if (m_lcntr > 0) { - PUSH_PC(cpustate, cpustate->pc+1); - PUSH_LOOP(cpustate, address, cond, type, cpustate->lcntr); + PUSH_PC(m_pc+1); + PUSH_LOOP(address, cond, type, m_lcntr); } } @@ -2405,11 +2403,11 @@ static void sharcop_do_until_counter_imm(SHARC_REGS *cpustate) /* | 00001101x | */ /* do until counter expired, LCNTR from UREG */ -static void sharcop_do_until_counter_ureg(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_do_until_counter_ureg() { - int ureg = (cpustate->opcode >> 32) & 0xff; - int offset = SIGN_EXTEND24(cpustate->opcode & 0xffffff); - UINT32 address = cpustate->pc + offset; + int ureg = (m_opcode >> 32) & 0xff; + int offset = SIGN_EXTEND24(m_opcode & 0xffffff); + UINT32 address = m_pc + offset; int type; int cond = 0xf; /* until LCE (loop counter expired */ int distance = abs(offset); @@ -2427,11 +2425,11 @@ static void sharcop_do_until_counter_ureg(SHARC_REGS *cpustate) type = 3; } - cpustate->lcntr = GET_UREG(cpustate, ureg); - if (cpustate->lcntr > 0) + m_lcntr = GET_UREG(ureg); + if (m_lcntr > 0) { - PUSH_PC(cpustate, cpustate->pc+1); - PUSH_LOOP(cpustate, address, cond, type, cpustate->lcntr); + PUSH_PC(m_pc+1); + PUSH_LOOP(address, cond, type, m_lcntr); } } @@ -2439,66 +2437,66 @@ static void sharcop_do_until_counter_ureg(SHARC_REGS *cpustate) /* | 00001110x | */ /* do until */ -static void sharcop_do_until(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_do_until() { - int cond = (cpustate->opcode >> 33) & 0x1f; - int offset = SIGN_EXTEND24(cpustate->opcode & 0xffffff); - UINT32 address = (cpustate->pc + offset); + int cond = (m_opcode >> 33) & 0x1f; + int offset = SIGN_EXTEND24(m_opcode & 0xffffff); + UINT32 address = (m_pc + offset); - PUSH_PC(cpustate, cpustate->pc+1); - PUSH_LOOP(cpustate, address, cond, 0, 0); + PUSH_PC(m_pc+1); + PUSH_LOOP(address, cond, 0, 0); } /*****************************************************************************/ /* | 000100 | G | D | */ /* ureg <- DM (direct addressing) */ -static void sharcop_dm_to_ureg_direct(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_dm_to_ureg_direct() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 address = (UINT32)(cpustate->opcode); + int ureg = (m_opcode >> 32) & 0xff; + UINT32 address = (UINT32)(m_opcode); - SET_UREG(cpustate, ureg, dm_read32(cpustate, address)); + SET_UREG(ureg, dm_read32(address)); } /* ureg -> DM (direct addressing) */ -static void sharcop_ureg_to_dm_direct(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_ureg_to_dm_direct() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 address = (UINT32)(cpustate->opcode); + int ureg = (m_opcode >> 32) & 0xff; + UINT32 address = (UINT32)(m_opcode); - dm_write32(cpustate, address, GET_UREG(cpustate, ureg)); + dm_write32(address, GET_UREG(ureg)); } /* ureg <- PM (direct addressing) */ -static void sharcop_pm_to_ureg_direct(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_pm_to_ureg_direct() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 address = (UINT32)(cpustate->opcode); + int ureg = (m_opcode >> 32) & 0xff; + UINT32 address = (UINT32)(m_opcode); if (ureg == 0xdb) // PX is 48-bit { - cpustate->px = pm_read48(cpustate, address); + m_px = pm_read48(address); } else { - SET_UREG(cpustate, ureg, pm_read32(cpustate, address)); + SET_UREG(ureg, pm_read32(address)); } } /* ureg -> PM (direct addressing) */ -static void sharcop_ureg_to_pm_direct(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_ureg_to_pm_direct() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 address = (UINT32)(cpustate->opcode); + int ureg = (m_opcode >> 32) & 0xff; + UINT32 address = (UINT32)(m_opcode); if (ureg == 0xdb) // PX is 48-bit { - pm_write48(cpustate, address, cpustate->px); + pm_write48(address, m_px); } else { - pm_write32(cpustate, address, GET_UREG(cpustate, ureg)); + pm_write32(address, GET_UREG(ureg)); } } @@ -2506,56 +2504,56 @@ static void sharcop_ureg_to_pm_direct(SHARC_REGS *cpustate) /* | 101 | G | III | D | */ /* ureg <- DM (indirect addressing) */ -static void sharcop_dm_to_ureg_indirect(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_dm_to_ureg_indirect() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 offset = (UINT32)cpustate->opcode; - int i = (cpustate->opcode >> 41) & 0x7; + int ureg = (m_opcode >> 32) & 0xff; + UINT32 offset = (UINT32)m_opcode; + int i = (m_opcode >> 41) & 0x7; - SET_UREG(cpustate, ureg, dm_read32(cpustate, DM_REG_I(i) + offset)); + SET_UREG(ureg, dm_read32(DM_REG_I(i) + offset)); } /* ureg -> DM (indirect addressing) */ -static void sharcop_ureg_to_dm_indirect(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_ureg_to_dm_indirect() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 offset = (UINT32)cpustate->opcode; - int i = (cpustate->opcode >> 41) & 0x7; + int ureg = (m_opcode >> 32) & 0xff; + UINT32 offset = (UINT32)m_opcode; + int i = (m_opcode >> 41) & 0x7; - dm_write32(cpustate, DM_REG_I(i) + offset, GET_UREG(cpustate, ureg)); + dm_write32(DM_REG_I(i) + offset, GET_UREG(ureg)); } /* ureg <- PM (indirect addressing) */ -static void sharcop_pm_to_ureg_indirect(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_pm_to_ureg_indirect() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 offset = cpustate->opcode & 0xffffff; - int i = (cpustate->opcode >> 41) & 0x7; + int ureg = (m_opcode >> 32) & 0xff; + UINT32 offset = m_opcode & 0xffffff; + int i = (m_opcode >> 41) & 0x7; if (ureg == 0xdb) /* PX is 48-bit */ { - cpustate->px = pm_read48(cpustate, PM_REG_I(i) + offset); + m_px = pm_read48(PM_REG_I(i) + offset); } else { - SET_UREG(cpustate, ureg, pm_read32(cpustate, PM_REG_I(i) + offset)); + SET_UREG(ureg, pm_read32(PM_REG_I(i) + offset)); } } /* ureg -> PM (indirect addressing) */ -static void sharcop_ureg_to_pm_indirect(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_ureg_to_pm_indirect() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 offset = (UINT32)cpustate->opcode; - int i = (cpustate->opcode >> 41) & 0x7; + int ureg = (m_opcode >> 32) & 0xff; + UINT32 offset = (UINT32)m_opcode; + int i = (m_opcode >> 41) & 0x7; if (ureg == 0xdb) /* PX is 48-bit */ { - pm_write48(cpustate, PM_REG_I(i) + offset, cpustate->px); + pm_write48(PM_REG_I(i) + offset, m_px); } else { - pm_write32(cpustate, PM_REG_I(i) + offset, GET_UREG(cpustate, ureg)); + pm_write32(PM_REG_I(i) + offset, GET_UREG(ureg)); } } @@ -2563,24 +2561,24 @@ static void sharcop_ureg_to_pm_indirect(SHARC_REGS *cpustate) /* | 1001xxxxx | */ /* immediate data -> DM|PM */ -static void sharcop_imm_to_dmpm(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_imm_to_dmpm() { - int i = (cpustate->opcode >> 41) & 0x7; - int m = (cpustate->opcode >> 38) & 0x7; - int g = (cpustate->opcode >> 37) & 0x1; - UINT32 data = (UINT32)cpustate->opcode; + int i = (m_opcode >> 41) & 0x7; + int m = (m_opcode >> 38) & 0x7; + int g = (m_opcode >> 37) & 0x1; + UINT32 data = (UINT32)m_opcode; if (g) { /* program memory (PM) */ - pm_write32(cpustate, PM_REG_I(i), data); + pm_write32(PM_REG_I(i), data); PM_REG_I(i) += PM_REG_M(m); UPDATE_CIRCULAR_BUFFER_PM(i); } else { /* data memory (DM) */ - dm_write32(cpustate, DM_REG_I(i), data); + dm_write32(DM_REG_I(i), data); DM_REG_I(i) += DM_REG_M(m); UPDATE_CIRCULAR_BUFFER_DM(i); } @@ -2590,25 +2588,25 @@ static void sharcop_imm_to_dmpm(SHARC_REGS *cpustate) /* | 00001111x | */ /* immediate data -> ureg */ -static void sharcop_imm_to_ureg(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_imm_to_ureg() { - int ureg = (cpustate->opcode >> 32) & 0xff; - UINT32 data = (UINT32)cpustate->opcode; + int ureg = (m_opcode >> 32) & 0xff; + UINT32 data = (UINT32)m_opcode; - SET_UREG(cpustate, ureg, data); + SET_UREG(ureg, data); } /*****************************************************************************/ /* | 00010100x | */ /* system register bit manipulation */ -static void sharcop_sysreg_bitop(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_sysreg_bitop() { - int bop = (cpustate->opcode >> 37) & 0x7; - int sreg = (cpustate->opcode >> 32) & 0xf; - UINT32 data = (UINT32)cpustate->opcode; + int bop = (m_opcode >> 37) & 0x7; + int sreg = (m_opcode >> 32) & 0xf; + UINT32 data = (UINT32)m_opcode; - UINT32 src = GET_UREG(cpustate, 0x70 | sreg); + UINT32 src = GET_UREG(0x70 | sreg); switch(bop) { @@ -2631,11 +2629,11 @@ static void sharcop_sysreg_bitop(SHARC_REGS *cpustate) { if ((src & data) == data) { - cpustate->astat |= BTF; + m_astat |= BTF; } else { - cpustate->astat &= ~BTF; + m_astat &= ~BTF; } break; } @@ -2643,11 +2641,11 @@ static void sharcop_sysreg_bitop(SHARC_REGS *cpustate) { if (src == data) { - cpustate->astat |= BTF; + m_astat |= BTF; } else { - cpustate->astat &= ~BTF; + m_astat &= ~BTF; } break; } @@ -2656,18 +2654,18 @@ static void sharcop_sysreg_bitop(SHARC_REGS *cpustate) break; } - SET_UREG(cpustate, 0x70 | sreg, src); + SET_UREG(0x70 | sreg, src); } /*****************************************************************************/ /* | 000101100 | */ /* I register modify */ -static void sharcop_modify(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_modify() { - int g = (cpustate->opcode >> 38) & 0x1; - int i = (cpustate->opcode >> 32) & 0x7; - INT32 data = (cpustate->opcode); + int g = (m_opcode >> 38) & 0x1; + int i = (m_opcode >> 32) & 0x7; + INT32 data = (m_opcode); if (g) // PM { @@ -2685,7 +2683,7 @@ static void sharcop_modify(SHARC_REGS *cpustate) /* | 000101101 | */ /* I register bit-reverse */ -static void sharcop_bit_reverse(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_bit_reverse() { fatalerror("SHARC: sharcop_bit_reverse unimplemented\n"); } @@ -2694,63 +2692,64 @@ static void sharcop_bit_reverse(SHARC_REGS *cpustate) /* | 00010111x | */ /* push/pop stacks / flush cache */ -static void sharcop_push_pop_stacks(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_push_pop_stacks() { - if (cpustate->opcode & U64(0x008000000000)) + if (m_opcode & U64(0x008000000000)) { fatalerror("sharcop_push_pop_stacks: push loop not implemented\n"); } - if (cpustate->opcode & U64(0x004000000000)) + if (m_opcode & U64(0x004000000000)) { fatalerror("sharcop_push_pop_stacks: pop loop not implemented\n"); } - if (cpustate->opcode & U64(0x002000000000)) + if (m_opcode & U64(0x002000000000)) { //fatalerror("sharcop_push_pop_stacks: push sts not implemented\n"); - PUSH_STATUS_STACK(cpustate); + PUSH_STATUS_STACK(); } - if (cpustate->opcode & U64(0x001000000000)) + if (m_opcode & U64(0x001000000000)) { //fatalerror("sharcop_push_pop_stacks: pop sts not implemented\n"); - POP_STATUS_STACK(cpustate); + POP_STATUS_STACK(); } - if (cpustate->opcode & U64(0x000800000000)) + if (m_opcode & U64(0x000800000000)) { - PUSH_PC(cpustate, cpustate->pcstk); + PUSH_PC(m_pcstk); } - if (cpustate->opcode & U64(0x000400000000)) + if (m_opcode & U64(0x000400000000)) { - POP_PC(cpustate); + POP_PC(); } } /*****************************************************************************/ /* | 000000000 | */ -static void sharcop_nop(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_nop() { } /*****************************************************************************/ /* | 000000001 | */ -static void sharcop_idle(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_idle() { - //CHANGE_PC(cpustate, cpustate->pc); + //CHANGE_PC(m_pc); - cpustate->daddr = cpustate->pc; - cpustate->faddr = cpustate->pc+1; - cpustate->nfaddr = cpustate->pc+2; + m_daddr = m_pc; + m_faddr = m_pc+1; + m_nfaddr = m_pc+2; - cpustate->idle = 1; + m_idle = 1; } /*****************************************************************************/ -static void sharcop_unimplemented(SHARC_REGS *cpustate) +void adsp21062_device::sharcop_unimplemented() { + extern CPU_DISASSEMBLE(sharc); char dasm[1000]; - CPU_DISASSEMBLE_NAME(sharc)(NULL, dasm, cpustate->pc, NULL, NULL, 0); - mame_printf_debug("SHARC: %08X: %s\n", cpustate->pc, dasm); - fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X\n", (UINT16)(cpustate->opcode >> 32), (UINT32)(cpustate->opcode), cpustate->pc); + CPU_DISASSEMBLE_NAME(sharc)(NULL, dasm, m_pc, NULL, NULL, 0); + mame_printf_debug("SHARC: %08X: %s\n", m_pc, dasm); + fatalerror("SHARC: Unimplemented opcode %04X%08X at %08X\n", (UINT16)(m_opcode >> 32), (UINT32)(m_opcode), m_pc); } diff --git a/src/emu/cpu/sharc/sharcops.h b/src/emu/cpu/sharc/sharcops.h index 2a29f7b1e07..a4a46576333 100644 --- a/src/emu/cpu/sharc/sharcops.h +++ b/src/emu/cpu/sharc/sharcops.h @@ -1,138 +1,132 @@ -struct SHARC_OP -{ - UINT32 op_mask; - UINT32 op_bits; - void (*handler)(SHARC_REGS *cpustate); -}; -static const SHARC_OP sharc_opcode_table[] = +const adsp21062_device::SHARC_OP adsp21062_device::s_sharc_opcode_table[] = { // |0 0 1| - { 0xe000, 0x2000, sharcop_compute_dreg_dm_dreg_pm }, + { 0xe000, 0x2000, &adsp21062_device::sharcop_compute_dreg_dm_dreg_pm }, // |0 0 0|0 0 0 0 1| - { 0xff00, 0x0100, sharcop_compute }, + { 0xff00, 0x0100, &adsp21062_device::sharcop_compute }, // |0 1 0|0| - { 0xf000, 0x4000, sharcop_compute_ureg_dmpm_premod }, + { 0xf000, 0x4000, &adsp21062_device::sharcop_compute_ureg_dmpm_premod }, // |0 1 0|1| - { 0xf000, 0x5000, sharcop_compute_ureg_dmpm_postmod }, + { 0xf000, 0x5000, &adsp21062_device::sharcop_compute_ureg_dmpm_postmod }, // |0 1 1|0|x x x|0|0| - { 0xf180, 0x6000, sharcop_compute_dm_to_dreg_immmod }, + { 0xf180, 0x6000, &adsp21062_device::sharcop_compute_dm_to_dreg_immmod }, // |0 1 1|0|x x x|0|1| - { 0xf180, 0x6080, sharcop_compute_dreg_to_dm_immmod }, + { 0xf180, 0x6080, &adsp21062_device::sharcop_compute_dreg_to_dm_immmod }, // |0 1 1|0|x x x|1|0| - { 0xf180, 0x6100, sharcop_compute_pm_to_dreg_immmod }, + { 0xf180, 0x6100, &adsp21062_device::sharcop_compute_pm_to_dreg_immmod }, // |0 1 1|0|x x x|1|1| - { 0xf180, 0x6180, sharcop_compute_dreg_to_pm_immmod }, + { 0xf180, 0x6180, &adsp21062_device::sharcop_compute_dreg_to_pm_immmod }, // |0 1 1|1| - { 0xf000, 0x7000, sharcop_compute_ureg_to_ureg }, + { 0xf000, 0x7000, &adsp21062_device::sharcop_compute_ureg_to_ureg }, // |1 0 0|0| - { 0xf000, 0x8000, sharcop_imm_shift_dreg_dmpm }, + { 0xf000, 0x8000, &adsp21062_device::sharcop_imm_shift_dreg_dmpm }, // |0 0 0|0 0 0 1 0| - { 0xff00, 0x0200, sharcop_imm_shift }, + { 0xff00, 0x0200, &adsp21062_device::sharcop_imm_shift }, // |0 0 0|0 0 1 0 0| - { 0xff00, 0x0400, sharcop_compute_modify }, + { 0xff00, 0x0400, &adsp21062_device::sharcop_compute_modify }, // |0 0 0|0 0 1 1 0|0| - { 0xff80, 0x0600, sharcop_direct_jump }, + { 0xff80, 0x0600, &adsp21062_device::sharcop_direct_jump }, // |0 0 0|0 0 1 1 0|1| - { 0xff80, 0x0680, sharcop_direct_call }, + { 0xff80, 0x0680, &adsp21062_device::sharcop_direct_call }, // |0 0 0|0 0 1 1 1|0| - { 0xff80, 0x0700, sharcop_relative_jump }, + { 0xff80, 0x0700, &adsp21062_device::sharcop_relative_jump }, // |0 0 0|0 0 1 1 1|1| - { 0xff80, 0x0780, sharcop_relative_call }, + { 0xff80, 0x0780, &adsp21062_device::sharcop_relative_call }, // |0 0 0|0 1 0 0 0|0| - { 0xff80, 0x0800, sharcop_indirect_jump }, + { 0xff80, 0x0800, &adsp21062_device::sharcop_indirect_jump }, // |0 0 0|0 1 0 0 0|1| - { 0xff80, 0x0880, sharcop_indirect_call }, + { 0xff80, 0x0880, &adsp21062_device::sharcop_indirect_call }, // |0 0 0|0 1 0 0 1|0| - { 0xff80, 0x0900, sharcop_relative_jump_compute }, + { 0xff80, 0x0900, &adsp21062_device::sharcop_relative_jump_compute }, // |0 0 0|0 1 0 0 1|1| - { 0xff80, 0x0980, sharcop_relative_call_compute }, + { 0xff80, 0x0980, &adsp21062_device::sharcop_relative_call_compute }, // |1 1 0| - { 0xe000, 0xc000, sharcop_indirect_jump_compute_dreg_dm }, + { 0xe000, 0xc000, &adsp21062_device::sharcop_indirect_jump_compute_dreg_dm }, // |1 1 1| - { 0xe000, 0xe000, sharcop_relative_jump_compute_dreg_dm }, + { 0xe000, 0xe000, &adsp21062_device::sharcop_relative_jump_compute_dreg_dm }, // |0 0 0|0 1 0 1 0| - { 0xff00, 0x0a00, sharcop_rts }, + { 0xff00, 0x0a00, &adsp21062_device::sharcop_rts }, // |0 0 0|0 1 0 1 1| - { 0xff00, 0x0b00, sharcop_rti }, + { 0xff00, 0x0b00, &adsp21062_device::sharcop_rti }, // |0 0 0|0 1 1 0 0| - { 0xff00, 0x0c00, sharcop_do_until_counter_imm }, + { 0xff00, 0x0c00, &adsp21062_device::sharcop_do_until_counter_imm }, // |0 0 0|0 1 1 0 1| - { 0xff00, 0x0d00, sharcop_do_until_counter_ureg }, + { 0xff00, 0x0d00, &adsp21062_device::sharcop_do_until_counter_ureg }, // |0 0 0|0 1 1 1 0| - { 0xff00, 0x0e00, sharcop_do_until }, + { 0xff00, 0x0e00, &adsp21062_device::sharcop_do_until }, // |0 0 0|1 0 0|0|0| - { 0xff00, 0x1000, sharcop_dm_to_ureg_direct }, + { 0xff00, 0x1000, &adsp21062_device::sharcop_dm_to_ureg_direct }, // |0 0 0|1 0 0|0|1| - { 0xff00, 0x1100, sharcop_ureg_to_dm_direct }, + { 0xff00, 0x1100, &adsp21062_device::sharcop_ureg_to_dm_direct }, // |0 0 0|1 0 0|1|0| - { 0xff00, 0x1200, sharcop_pm_to_ureg_direct }, + { 0xff00, 0x1200, &adsp21062_device::sharcop_pm_to_ureg_direct }, // |0 0 0|1 0 0|1|1| - { 0xff00, 0x1300, sharcop_ureg_to_pm_direct }, + { 0xff00, 0x1300, &adsp21062_device::sharcop_ureg_to_pm_direct }, // |1 0 1|0|x x x|0| - { 0xf100, 0xa000, sharcop_dm_to_ureg_indirect }, + { 0xf100, 0xa000, &adsp21062_device::sharcop_dm_to_ureg_indirect }, // |1 0 1|0|x x x|1| - { 0xf100, 0xa100, sharcop_ureg_to_dm_indirect }, + { 0xf100, 0xa100, &adsp21062_device::sharcop_ureg_to_dm_indirect }, // |1 0 1|1|x x x|0| - { 0xf100, 0xb000, sharcop_pm_to_ureg_indirect }, + { 0xf100, 0xb000, &adsp21062_device::sharcop_pm_to_ureg_indirect }, // |1 0 1|1|x x x|1| - { 0xf100, 0xb100, sharcop_ureg_to_pm_indirect }, + { 0xf100, 0xb100, &adsp21062_device::sharcop_ureg_to_pm_indirect }, // |1 0 0|1| - { 0xf000, 0x9000, sharcop_imm_to_dmpm }, + { 0xf000, 0x9000, &adsp21062_device::sharcop_imm_to_dmpm }, // |0 0 0|0 1 1 1 1| - { 0xff00, 0x0f00, sharcop_imm_to_ureg }, + { 0xff00, 0x0f00, &adsp21062_device::sharcop_imm_to_ureg }, // |0 0 0|1 0 1 0 0| - { 0xff00, 0x1400, sharcop_sysreg_bitop }, + { 0xff00, 0x1400, &adsp21062_device::sharcop_sysreg_bitop }, // |0 0 0|1 0 1 1 0|0| - { 0xff80, 0x1600, sharcop_modify }, + { 0xff80, 0x1600, &adsp21062_device::sharcop_modify }, // |0 0 0|1 0 1 1 0|1| - { 0xff80, 0x1680, sharcop_bit_reverse }, + { 0xff80, 0x1680, &adsp21062_device::sharcop_bit_reverse }, // |0 0 0|1 0 1 1 1| - { 0xff00, 0x1700, sharcop_push_pop_stacks }, + { 0xff00, 0x1700, &adsp21062_device::sharcop_push_pop_stacks }, // |0 0 0|0 0 0 0 0|0| - { 0xff80, 0x0000, sharcop_nop }, + { 0xff80, 0x0000, &adsp21062_device::sharcop_nop }, // |0 0 0|0 0 0 0 0|1| - { 0xff80, 0x0080, sharcop_idle }, + { 0xff80, 0x0080, &adsp21062_device::sharcop_idle }, }; diff --git a/src/mame/drivers/gticlub.c b/src/mame/drivers/gticlub.c index dbd671c844c..d1dc384a1de 100644 --- a/src/mame/drivers/gticlub.c +++ b/src/mame/drivers/gticlub.c @@ -256,7 +256,7 @@ public: required_shared_ptr m_work_ram; required_device m_maincpu; required_device m_audiocpu; - required_device m_dsp; + required_device m_dsp; optional_device m_dsp2; required_device m_k056800; required_device m_adc1038; @@ -748,12 +748,6 @@ INTERRUPT_GEN_MEMBER(gticlub_state::gticlub_vblank) } -static const sharc_config sharc_cfg = -{ - BOOT_MODE_EPROM -}; - - static int adc1038_input_callback( device_t *device, int input ) { int value = 0; @@ -917,7 +911,7 @@ UINT32 gticlub_state::screen_update_gticlub(screen_device &screen, bitmap_rgb32 draw_7segment_led(bitmap, 9, 3, gticlub_led_reg[1]); //machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(machine().device("dsp"), 1, ASSERT_LINE); + m_dsp->set_flag_input(1, ASSERT_LINE); return 0; } @@ -964,7 +958,7 @@ static MACHINE_CONFIG_START( gticlub, gticlub_state ) MCFG_CPU_PROGRAM_MAP(sound_memmap) MCFG_CPU_ADD("dsp", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(sharc_map) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) @@ -1068,11 +1062,11 @@ static MACHINE_CONFIG_START( hangplt, gticlub_state ) MCFG_CPU_PROGRAM_MAP(sound_memmap) MCFG_CPU_ADD("dsp", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(hangplt_sharc0_map) MCFG_CPU_ADD("dsp2", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(hangplt_sharc1_map) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) diff --git a/src/mame/drivers/hornet.c b/src/mame/drivers/hornet.c index 9554759bae0..d8d41b4c0a2 100644 --- a/src/mame/drivers/hornet.c +++ b/src/mame/drivers/hornet.c @@ -885,10 +885,6 @@ static INPUT_PORTS_START( sscope ) PORT_BIT( 0x7ff, 0x3ff, IPT_AD_STICK_Y ) PORT_MINMAX(0x000, 0x7ff) PORT_SENSITIVITY(35) PORT_KEYDELTA(5) PORT_INVERT INPUT_PORTS_END -static const sharc_config sharc_cfg = -{ - BOOT_MODE_EPROM -}; /* PowerPC interrupts @@ -984,7 +980,7 @@ static MACHINE_CONFIG_START( hornet, hornet_state ) MCFG_CPU_PROGRAM_MAP(sound_memmap) MCFG_CPU_ADD("dsp", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(sharc0_map) MCFG_QUANTUM_TIME(attotime::from_hz(6000)) @@ -1067,7 +1063,7 @@ static const voodoo_config voodoo_r_intf = static MACHINE_CONFIG_DERIVED( hornet_2board, hornet ) MCFG_CPU_ADD("dsp2", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(sharc1_map) MCFG_MACHINE_RESET_OVERRIDE(hornet_state,hornet_2board) diff --git a/src/mame/drivers/model2.c b/src/mame/drivers/model2.c index 42edbd60999..469ac038604 100644 --- a/src/mame/drivers/model2.c +++ b/src/mame/drivers/model2.c @@ -134,11 +134,11 @@ static int copro_fifoin_pop(device_t *device, UINT32 *result) { if (state->m_copro_fifoin_num == 0) { - sharc_set_flag_input(device, 0, ASSERT_LINE); + dynamic_cast(device)->set_flag_input(0, ASSERT_LINE); } else { - sharc_set_flag_input(device, 0, CLEAR_LINE); + dynamic_cast(device)->set_flag_input(0, CLEAR_LINE); } } @@ -195,7 +195,7 @@ static void copro_fifoin_push(device_t *device, UINT32 data) // clear FIFO empty flag on SHARC if (state->m_dsp_type == DSP_TYPE_SHARC) { - sharc_set_flag_input(device, 0, CLEAR_LINE); + dynamic_cast(device)->set_flag_input(0, CLEAR_LINE); } } @@ -233,11 +233,11 @@ static UINT32 copro_fifoout_pop(address_space &space) { if (state->m_copro_fifoout_num == COPRO_FIFOOUT_SIZE) { - sharc_set_flag_input(space.machine().device("dsp"), 1, ASSERT_LINE); + space.machine().device("dsp")->set_flag_input(1, ASSERT_LINE); } else { - sharc_set_flag_input(space.machine().device("dsp"), 1, CLEAR_LINE); + space.machine().device("dsp")->set_flag_input(1, CLEAR_LINE); } } @@ -269,13 +269,13 @@ static void copro_fifoout_push(device_t *device, UINT32 data) { if (state->m_copro_fifoout_num == COPRO_FIFOOUT_SIZE) { - sharc_set_flag_input(device, 1, ASSERT_LINE); + dynamic_cast(device)->set_flag_input(1, ASSERT_LINE); //device->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); } else { - sharc_set_flag_input(device, 1, CLEAR_LINE); + dynamic_cast(device)->set_flag_input(1, CLEAR_LINE); //device->execute().set_input_line(SHARC_INPUT_FLAG1, CLEAR_LINE); } @@ -689,7 +689,7 @@ WRITE32_MEMBER(model2_state::copro_fifo_w) { if (m_dsp_type == DSP_TYPE_SHARC) { - sharc_external_dma_write(machine().device("dsp"), m_coprocnt, data & 0xffff); + machine().device("dsp")->external_dma_write(m_coprocnt, data & 0xffff); } else if (m_dsp_type == DSP_TYPE_TGP) { @@ -721,7 +721,7 @@ WRITE32_MEMBER(model2_state::copro_sharc_iop_w) (strcmp(machine().system().name, "vonj" ) == 0) || (strcmp(machine().system().name, "rchase2" ) == 0)) { - sharc_external_iop_write(machine().device("dsp"), offset, data); + machine().device("dsp")->external_iop_write(offset, data); } else { @@ -732,7 +732,7 @@ WRITE32_MEMBER(model2_state::copro_sharc_iop_w) else { m_iop_data |= (data & 0xffff) << 16; - sharc_external_iop_write(machine().device("dsp"), offset, m_iop_data); + machine().device("dsp")->external_iop_write(offset, m_iop_data); } m_iop_write_num++; } @@ -805,7 +805,7 @@ WRITE32_MEMBER(model2_state::geo_sharc_fifo_w) { if (m_geoctl & 0x80000000) { - sharc_external_dma_write(machine().device("dsp2"), m_geocnt, data & 0xffff); + machine().device("dsp2")->external_dma_write(m_geocnt, data & 0xffff); m_geocnt++; } @@ -819,7 +819,7 @@ WRITE32_MEMBER(model2_state::geo_sharc_iop_w) { if ((strcmp(machine().system().name, "schamp" ) == 0)) { - sharc_external_iop_write(machine().device("dsp2"), offset, data); + machine().device("dsp2")->external_iop_write(offset, data); } else { @@ -830,7 +830,7 @@ WRITE32_MEMBER(model2_state::geo_sharc_iop_w) else { m_geo_iop_data |= (data & 0xffff) << 16; - sharc_external_iop_write(machine().device("dsp2"), offset, m_geo_iop_data); + machine().device("dsp2")->external_iop_write(offset, m_geo_iop_data); } m_geo_iop_write_num++; } @@ -2087,11 +2087,6 @@ static MACHINE_CONFIG_DERIVED( srallyc, model2a ) MCFG_CPU_VBLANK_INT_DRIVER("screen", model2_state, irq0_line_hold) MACHINE_CONFIG_END -static const sharc_config sharc_cfg = -{ - BOOT_MODE_HOST -}; - /* 2B-CRX */ static MACHINE_CONFIG_START( model2b, model2_state ) MCFG_CPU_ADD("maincpu", I960, 25000000) @@ -2102,11 +2097,11 @@ static MACHINE_CONFIG_START( model2b, model2_state ) MCFG_CPU_PROGRAM_MAP(model2_snd) MCFG_CPU_ADD("dsp", ADSP21062, 40000000) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_HOST) MCFG_CPU_DATA_MAP(copro_sharc_map) //MCFG_CPU_ADD("dsp2", ADSP21062, 40000000) - //MCFG_CPU_CONFIG(sharc_cfg) + //MCFG_SHARC_BOOT_MODE(BOOT_MODE_HOST) //MCFG_CPU_DATA_MAP(geo_sharc_map) MCFG_QUANTUM_TIME(attotime::from_hz(18000)) diff --git a/src/mame/drivers/nwk-tr.c b/src/mame/drivers/nwk-tr.c index c76d93be2b8..19aa2145fa5 100644 --- a/src/mame/drivers/nwk-tr.c +++ b/src/mame/drivers/nwk-tr.c @@ -686,11 +686,6 @@ static INPUT_PORTS_START( nwktr ) INPUT_PORTS_END -static const sharc_config sharc_cfg = -{ - BOOT_MODE_EPROM -}; - static double adc12138_input_callback( device_t *device, UINT8 input ) { @@ -757,7 +752,7 @@ static MACHINE_CONFIG_START( nwktr, nwktr_state ) MCFG_CPU_PROGRAM_MAP(sound_memmap) MCFG_CPU_ADD("dsp", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(sharc_map) MCFG_QUANTUM_TIME(attotime::from_hz(9000)) diff --git a/src/mame/drivers/zr107.c b/src/mame/drivers/zr107.c index da3670389c9..e45db28a49c 100644 --- a/src/mame/drivers/zr107.c +++ b/src/mame/drivers/zr107.c @@ -257,7 +257,7 @@ UINT32 zr107_state::screen_update_jetwave(screen_device &screen, bitmap_rgb32 &b draw_7segment_led(bitmap, 3, 3, m_led_reg0); draw_7segment_led(bitmap, 9, 3, m_led_reg1); - sharc_set_flag_input(machine().device("dsp"), 1, ASSERT_LINE); + machine().device("dsp")->set_flag_input(1, ASSERT_LINE); return 0; } @@ -305,7 +305,7 @@ UINT32 zr107_state::screen_update_zr107(screen_device &screen, bitmap_rgb32 &bit draw_7segment_led(bitmap, 3, 3, m_led_reg0); draw_7segment_led(bitmap, 9, 3, m_led_reg1); - sharc_set_flag_input(machine().device("dsp"), 1, ASSERT_LINE); + machine().device("dsp")->set_flag_input(1, ASSERT_LINE); return 0; } @@ -670,11 +670,6 @@ static INPUT_PORTS_START( jetwave ) INPUT_PORTS_END -static const sharc_config sharc_cfg = -{ - BOOT_MODE_EPROM -}; - /* ADC0838 Interface */ @@ -758,7 +753,7 @@ static MACHINE_CONFIG_START( zr107, zr107_state ) MCFG_CPU_PROGRAM_MAP(sound_memmap) MCFG_CPU_ADD("dsp", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(sharc_map) MCFG_QUANTUM_TIME(attotime::from_hz(750000))// Very high sync needed to prevent lockups - why? @@ -818,7 +813,7 @@ static MACHINE_CONFIG_START( jetwave, zr107_state ) MCFG_CPU_PROGRAM_MAP(sound_memmap) MCFG_CPU_ADD("dsp", ADSP21062, XTAL_36MHz) - MCFG_CPU_CONFIG(sharc_cfg) + MCFG_SHARC_BOOT_MODE(BOOT_MODE_EPROM) MCFG_CPU_DATA_MAP(sharc_map) MCFG_QUANTUM_TIME(attotime::from_hz(2000000)) // Very high sync needed to prevent lockups - why? diff --git a/src/mame/machine/konppc.c b/src/mame/machine/konppc.c index fb822d563af..f68c5e04059 100644 --- a/src/mame/machine/konppc.c +++ b/src/mame/machine/konppc.c @@ -225,12 +225,12 @@ static void dsp_comm_sharc_w(address_space &space, int board, int offset, UINT32 case CGBOARD_TYPE_GTICLUB: { //machine.device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG0, ASSERT_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 0, ASSERT_LINE); + space.machine().device("dsp")->set_flag_input(0, ASSERT_LINE); if (offset == 1) { if (data & 0x03) - space.machine().device("dsp")->execute().set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE); + space.machine().device("dsp")->set_input_line(INPUT_LINE_IRQ2, ASSERT_LINE); } break; } @@ -239,7 +239,7 @@ static void dsp_comm_sharc_w(address_space &space, int board, int offset, UINT32 case CGBOARD_TYPE_HANGPLT: { const char *dsptag = (board == 0) ? "dsp" : "dsp2"; - device_t *device = space.machine().device(dsptag); + adsp21062_device *device = space.machine().device(dsptag); if (offset == 1) { @@ -247,7 +247,7 @@ static void dsp_comm_sharc_w(address_space &space, int board, int offset, UINT32 if (data & 0x01 || data & 0x10) { - sharc_set_flag_input(device, 1, ASSERT_LINE); + device->set_flag_input(1, ASSERT_LINE); } if (texture_bank[board] != NULL) @@ -354,25 +354,25 @@ WRITE32_HANDLER( cgboard_1_shared_sharc_w ) static UINT32 nwk_fifo_r(address_space &space, int board) { const char *dsptag = (board == 0) ? "dsp" : "dsp2"; - device_t *device = space.machine().device(dsptag); + adsp21062_device *device = space.machine().device(dsptag); UINT32 data; if (nwk_fifo_read_ptr[board] < nwk_fifo_half_full_r) { - sharc_set_flag_input(device, 1, CLEAR_LINE); + device->set_flag_input(1, CLEAR_LINE); } else { - sharc_set_flag_input(device, 1, ASSERT_LINE); + device->set_flag_input(1, ASSERT_LINE); } if (nwk_fifo_read_ptr[board] < nwk_fifo_full) { - sharc_set_flag_input(device, 2, ASSERT_LINE); + device->set_flag_input(2, ASSERT_LINE); } else { - sharc_set_flag_input(device, 2, CLEAR_LINE); + device->set_flag_input(2, CLEAR_LINE); } data = nwk_fifo[board][nwk_fifo_read_ptr[board]]; @@ -385,18 +385,18 @@ static UINT32 nwk_fifo_r(address_space &space, int board) static void nwk_fifo_w(running_machine &machine, int board, UINT32 data) { const char *dsptag = (board == 0) ? "dsp" : "dsp2"; - device_t *device = machine.device(dsptag); + adsp21062_device *device = machine.device(dsptag); if (nwk_fifo_write_ptr[board] < nwk_fifo_half_full_w) { - sharc_set_flag_input(device, 1, ASSERT_LINE); + device->set_flag_input(1, ASSERT_LINE); } else { - sharc_set_flag_input(device, 1, CLEAR_LINE); + device->set_flag_input(1, CLEAR_LINE); } - sharc_set_flag_input(device, 2, ASSERT_LINE); + device->set_flag_input(2, ASSERT_LINE); nwk_fifo[board][nwk_fifo_write_ptr[board]] = data; nwk_fifo_write_ptr[board]++; diff --git a/src/mame/video/gticlub.c b/src/mame/video/gticlub.c index a2e84d369ec..5167e707aa4 100644 --- a/src/mame/video/gticlub.c +++ b/src/mame/video/gticlub.c @@ -351,18 +351,18 @@ READ32_HANDLER( K001005_r ) if (K001005_fifo_read_ptr < 0x3ff) { //space.machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, CLEAR_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 1, CLEAR_LINE); + space.machine().device("dsp")->set_flag_input(1, CLEAR_LINE); } else { //space.machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 1, ASSERT_LINE); + space.machine().device("dsp")->set_flag_input(1, ASSERT_LINE); } } else { //space.machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 1, ASSERT_LINE); + space.machine().device("dsp")->set_flag_input(1, ASSERT_LINE); } K001005_fifo_read_ptr++; @@ -404,18 +404,18 @@ WRITE32_HANDLER( K001005_w ) if (K001005_fifo_write_ptr < 0x400) { //space.machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 1, ASSERT_LINE); + space.machine().device("dsp")->set_flag_input(1, ASSERT_LINE); } else { //space.machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, CLEAR_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 1, CLEAR_LINE); + space.machine().device("dsp")->set_flag_input(1, CLEAR_LINE); } } else { //space.machine().device("dsp")->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(space.machine().device("dsp"), 1, ASSERT_LINE); + space.machine().device("dsp")->set_flag_input(1, ASSERT_LINE); } // mame_printf_debug("K001005 FIFO write: %08X at %08X\n", data, space.device().safe_pc()); diff --git a/src/mame/video/k001005.c b/src/mame/video/k001005.c index b13f541897d..dc87ac29b35 100644 --- a/src/mame/video/k001005.c +++ b/src/mame/video/k001005.c @@ -97,7 +97,7 @@ void k001005_device::device_start() int i, width, height; m_cpu = machine().device(m_cpu_tag); - m_dsp = machine().device(m_dsp_tag); + m_dsp = machine().device(m_dsp_tag); m_k001006_1 = machine().device(m_k001006_1_tag); m_k001006_2 = machine().device(m_k001006_2_tag); @@ -271,18 +271,18 @@ READ32_MEMBER( k001005_device::read ) if (m_fifo_read_ptr < 0x3ff) { //m_dsp->execute().set_input_line(SHARC_INPUT_FLAG1, CLEAR_LINE); - sharc_set_flag_input(m_dsp, 1, CLEAR_LINE); + m_dsp->set_flag_input(1, CLEAR_LINE); } else { //m_dsp->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(m_dsp, 1, ASSERT_LINE); + m_dsp->set_flag_input(1, ASSERT_LINE); } } else { //m_dsp->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(m_dsp, 1, ASSERT_LINE); + m_dsp->set_flag_input(1, ASSERT_LINE); } m_fifo_read_ptr++; @@ -324,18 +324,18 @@ WRITE32_MEMBER( k001005_device::write ) if (m_fifo_write_ptr < 0x400) { //m_dsp->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(m_dsp, 1, ASSERT_LINE); + m_dsp->set_flag_input(1, ASSERT_LINE); } else { //m_dsp->execute().set_input_line(SHARC_INPUT_FLAG1, CLEAR_LINE); - sharc_set_flag_input(m_dsp, 1, CLEAR_LINE); + m_dsp->set_flag_input(1, CLEAR_LINE); } } else { //m_dsp->execute().set_input_line(SHARC_INPUT_FLAG1, ASSERT_LINE); - sharc_set_flag_input(m_dsp, 1, ASSERT_LINE); + m_dsp->set_flag_input(1, ASSERT_LINE); } // mame_printf_debug("K001005 FIFO write: %08X at %08X\n", data, space.device().safe_pc()); diff --git a/src/mame/video/k001005.h b/src/mame/video/k001005.h index 71c7c1dfa57..95d068e9261 100644 --- a/src/mame/video/k001005.h +++ b/src/mame/video/k001005.h @@ -53,7 +53,7 @@ protected: private: // internal state device_t *m_cpu; - device_t *m_dsp; + adsp21062_device *m_dsp; device_t *m_k001006_1; device_t *m_k001006_2;