Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-21 07:52:35 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

bbc: Fixed Shadow RAM corruption in Master/B+, and sideways RAM access in Model B.

Browse Source
This commit is contained in:
Nigel Barnes 2018-03-20 21:31:17 +00:00
parent 069c9c8e2c
commit e5bccf8de1
4 changed files with 367 additions and 474 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

156
src/mame/drivers/bbc.cpp
View File

@ -145,8 +145,8 @@ READ8_MEMBER(bbc_state::bbc_fe_r)
void bbc_state::bbca_mem(address_map &map)
{
map.unmap_value_high(); /* Hardware marked with a # is not present in a Model A */
map(0x0000, 0x3fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorya1_w)); /* 0000-3fff Regular Ram */
map(0x4000, 0x7fff).bankr("bank3").w(this, FUNC(bbc_state::bbc_memoryb3_w)); /* 4000-7fff Repeat of the Regular Ram */
map(0x0000, 0x3fff).bankrw("bank1"); /* 0000-3fff Regular RAM */
map(0x4000, 0x7fff).bankrw("bank3"); /* 4000-7fff Regular RAM mirrored */
map(0x8000, 0xbfff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memoryb4_w)); /* 8000-bfff Paged ROM */
map(0xc000, 0xfbff).bankr("bank7"); /* c000-fbff OS ROM */
map(0xfc00, 0xfdff).noprw(); /* fc00-fdff FRED & JIM Pages */
@ -158,8 +158,7 @@ void bbc_state::bbca_mem(address_map &map)
map(0xfe18, 0xfe1f).noprw(); /* fe18-fe1f INTOFF/STATID # ECONET Interrupt Off / ID No. */
map(0xfe20, 0xfe2f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_videoULA_w)); /* R: fe20-fe2f INTON # ECONET Interrupt On */
/* W: fe20-fe2f Video ULA Video system chip */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_page_selecta_w)); /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 74LS161 Paged ROM selector */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::page_selecta_w)); /* W: fe30-fe3f 74LS161 Paged ROM selector */
map(0xfe40, 0xfe5f).rw(m_via6522_0, FUNC(via6522_device::read), FUNC(via6522_device::write)); /* fe40-fe5f 6522 VIA SYSTEM VIA */
map(0xfe60, 0xfe7f).noprw(); /* fe60-fe7f 6522 VIA # USER VIA */
map(0xfe80, 0xfe9f).noprw(); /* fe80-fe9f 8271/1770 FDC # Floppy disc controller */
@ -175,7 +174,7 @@ void bbc_state::bbc_base(address_map &map)
map.unmap_value_high();
map(0xc000, 0xfbff).bankr("bank7"); /* c000-fbff OS ROM */
map(0xfc00, 0xfdff).noprw(); /* fc00-fdff FRED & JIM Pages */
/* fe00-feff SHEILA Address Page */
map(0xfe00, 0xfeff).r(this, FUNC(bbc_state::bbc_fe_r)); /* fe00-feff SHEILA Address Page */
map(0xfe00, 0xfe00).mirror(0x06).rw(m_hd6845, FUNC(hd6845_device::status_r), FUNC(hd6845_device::address_w)); /* fe00-fe07 6845 CRTC Video controller */
map(0xfe01, 0xfe01).mirror(0x06).rw(m_hd6845, FUNC(hd6845_device::register_r), FUNC(hd6845_device::register_w));
map(0xfe08, 0xfe09).mirror(0x06).rw(m_acia, FUNC(acia6850_device::read), FUNC(acia6850_device::write)); /* fe08-fe0f 6850 ACIA Serial controller */
@ -196,11 +195,10 @@ void bbc_state::bbc_base(address_map &map)
void bbc_state::bbcb_mem(address_map &map)
{
bbc_base(map);
map(0x0000, 0x3fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorya1_w)); /* 0000-3fff Regular Ram */
map(0x4000, 0x7fff).bankr("bank3").w(this, FUNC(bbc_state::bbc_memoryb3_w)); /* 4000-7fff Regular Ram */
map(0x8000, 0xbfff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memoryb4_w)); /* 8000-bfff Paged ROM */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_page_selectb_w)); /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0x0000, 0x3fff).bankrw("bank1"); /* 0000-3fff Regular RAM */
map(0x4000, 0x7fff).bankrw("bank3"); /* 4000-7fff Regular RAM */
map(0x8000, 0xbfff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memoryb4_w)); /* 8000-bfff Paged ROM/RAM */
map(0xfe30, 0xfe3f).w(this, FUNC(bbc_state::page_selectb_w)); /* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).m(m_i8271, FUNC(i8271_device::map)); /* fe80-fe83 8271 FDC Floppy disc controller */
map(0xfe84, 0xfe9f).rw(m_i8271, FUNC(i8271_device::data_r), FUNC(i8271_device::data_w)); /* fe84-fe9f 8271 FDC Floppy disc controller */
}
@ -209,25 +207,22 @@ void bbc_state::bbcb_mem(address_map &map)
void bbc_state::bbcb_nofdc_mem(address_map &map)
{
bbc_base(map);
map(0x0000, 0x3fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorya1_w)); /* 0000-3fff Regular Ram */
map(0x4000, 0x7fff).bankr("bank3").w(this, FUNC(bbc_state::bbc_memoryb3_w)); /* 4000-7fff Regular Ram */
map(0x8000, 0xbfff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memoryb4_w)); /* 8000-bfff Paged ROM */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_page_selectb_w)); /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).noprw(); /* fe80-fe9f Floppy disc controller */
map(0x0000, 0x3fff).bankrw("bank1"); /* 0000-3fff Regular RAM */
map(0x4000, 0x7fff).bankrw("bank3"); /* 4000-7fff Regular RAM */
map(0x8000, 0xbfff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memoryb4_w)); /* 8000-bfff Paged ROM/RAM */
map(0xfe30, 0xfe3f).w(this, FUNC(bbc_state::page_selectb_w)); /* W: fe30-fe3f 84LS161 Paged ROM selector */
}
void bbc_state::bbcbp_mem(address_map &map)
{
bbc_base(map);
map(0x0000, 0x2fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorybp1_w)); /* 0000-2fff Regular Ram */
map(0x3000, 0x7fff).bankr("bank2").w(this, FUNC(bbc_state::bbc_memorybp2_w)); /* 3000-7fff Video/Shadow Ram */
map(0x0000, 0x2fff).bankrw("bank1"); /* 0000-2fff Regular RAM */
map(0x3000, 0x7fff).bankrw("bank2"); /* 3000-7fff Video/Shadow RAM */
map(0x8000, 0xafff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memorybp4_w)); /* 8000-afff Paged ROM or 12K of SWRAM */
map(0xb000, 0xbfff).bankr("bank6"); /* b000-bfff Rest of paged ROM area */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_page_selectbp_w)); /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_wd1770_status_w)); /* fe80-fe83 1770 FDC Drive control register */
map(0xb000, 0xbfff).bankr("bank6").w(this, FUNC(bbc_state::bbc_memorybp6_w)); /* b000-bfff Rest of paged ROM area */
map(0xfe30, 0xfe3f).w(this, FUNC(bbc_state::page_selectbp_w)); /* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).w(this, FUNC(bbc_state::bbc_wd1770_status_w)); /* fe80-fe83 1770 FDC Drive control register */
map(0xfe84, 0xfe9f).rw(m_wd1770, FUNC(wd1770_device::read), FUNC(wd1770_device::write)); /* fe84-fe9f 1770 FDC Floppy disc controller */
map(0xfee0, 0xfeff).rw(m_tube, FUNC(bbc_tube_slot_device::host_r), FUNC(bbc_tube_slot_device::host_w)); /* fee0-feff Tube ULA Tube system interface */
}
@ -236,13 +231,12 @@ void bbc_state::bbcbp_mem(address_map &map)
void bbc_state::bbcbp128_mem(address_map &map)
{
bbc_base(map);
map(0x0000, 0x2fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorybp1_w)); /* 0000-2fff Regular Ram */
map(0x3000, 0x7fff).bankr("bank2").w(this, FUNC(bbc_state::bbc_memorybp2_w)); /* 3000-7fff Video/Shadow Ram */
map(0x8000, 0xafff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memorybp4_128_w)); /* 8000-afff Paged ROM or 12K of SWRAM */
map(0xb000, 0xbfff).bankr("bank6").w(this, FUNC(bbc_state::bbc_memorybp6_128_w)); /* b000-bfff Rest of paged ROM area */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_page_selectbp_w)); /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_wd1770_status_w)); /* fe80-fe83 1770 FDC Drive control register */
map(0x0000, 0x2fff).bankrw("bank1"); /* 0000-2fff Regular RAM */
map(0x3000, 0x7fff).bankrw("bank2"); /* 3000-7fff Video/Shadow RAM */
map(0x8000, 0xafff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memorybp4_w)); /* 8000-afff Paged ROM or 12K of SWRAM */
map(0xb000, 0xbfff).bankr("bank6").w(this, FUNC(bbc_state::bbc_memorybp6_w)); /* b000-bfff Rest of paged ROM area */
map(0xfe30, 0xfe3f).w(this, FUNC(bbc_state::page_selectbp128_w)); /* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).w(this, FUNC(bbc_state::bbc_wd1770_status_w)); /* fe80-fe83 1770 FDC Drive control register */
map(0xfe84, 0xfe9f).rw(m_wd1770, FUNC(wd1770_device::read), FUNC(wd1770_device::write)); /* fe84-fe9f 1770 FDC Floppy disc controller */
map(0xfee0, 0xfeff).rw(m_tube, FUNC(bbc_tube_slot_device::host_r), FUNC(bbc_tube_slot_device::host_w)); /* fee0-feff Tube ULA Tube system interface */
}
@ -251,17 +245,21 @@ void bbc_state::bbcbp128_mem(address_map &map)
void bbc_state::reutapm_mem(address_map &map)
{
bbc_base(map);
map(0x0000, 0x2fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorybp1_w)); /* 0000-2fff Regular Ram */
map(0x3000, 0x7fff).bankr("bank2").w(this, FUNC(bbc_state::bbc_memorybp2_w)); /* 3000-7fff Video/Shadow Ram */
map(0x0000, 0x2fff).bankrw("bank1"); /* 0000-2fff Regular RAM */
map(0x3000, 0x7fff).bankrw("bank2"); /* 3000-7fff Video/Shadow RAM */
map(0x8000, 0xafff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memorybp4_w)); /* 8000-afff Paged ROM or 12K of SWRAM */
map(0xb000, 0xbfff).bankr("bank6"); /* b000-bfff Rest of paged ROM area */
map(0xfe30, 0xfe3f).rw(this, FUNC(bbc_state::bbc_fe_r), FUNC(bbc_state::bbc_page_selectbp_w)); /* R: fe30-fe3f NC Not Connected */
/* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfe80, 0xfe83).noprw(); /* fe80-fe83 1770 FDC Drive control register */
map(0xfe84, 0xfe9f).noprw(); /* fe84-fe9f 1770 FDC Floppy disc controller */
map(0xfee0, 0xfeff).r(this, FUNC(bbc_state::bbc_fe_r)); /* fee0-feff Tube ULA Tube system interface */
map(0xb000, 0xbfff).bankr("bank6").w(this, FUNC(bbc_state::bbc_memorybp6_w)); /* b000-bfff Rest of paged ROM area */
map(0xfe30, 0xfe3f).w(this, FUNC(bbc_state::page_selectbp_w)); /* W: fe30-fe3f 84LS161 Paged ROM selector */
map(0xfee0, 0xfeff).rw(m_tube, FUNC(bbc_tube_slot_device::host_r), FUNC(bbc_tube_slot_device::host_w)); /* fee0-feff Tube ULA Tube system interface */
}
void bbc_state::bbcbp_fetch(address_map &map)
{
map(0x0000, 0xffff).r(this, FUNC(bbc_state::bbcbp_fetch_r));
}
/******************************************************************************
&FC00-&FCFF FRED
&FD00-&FDFF JIM
@ -288,8 +286,8 @@ void bbc_state::reutapm_mem(address_map &map)
void bbc_state::bbcm_mem(address_map &map)
{
map(0x0000, 0x2fff).bankr("bank1").w(this, FUNC(bbc_state::bbc_memorybm1_w)); /* 0000-2fff Regular Ram */
map(0x3000, 0x7fff).bankr("bank2").w(this, FUNC(bbc_state::bbc_memorybm2_w)); /* 3000-7fff Video/Shadow Ram */
map(0x0000, 0x2fff).bankrw("bank1"); /* 0000-2fff Regular RAM */
map(0x3000, 0x7fff).bankrw("bank2"); /* 3000-7fff Video/Shadow RAM */
map(0x8000, 0x8fff).bankr("bank4").w(this, FUNC(bbc_state::bbc_memorybm4_w)); /* 8000-8fff Paged ROM/RAM or 4K of RAM ANDY */
map(0x9000, 0xbfff).bankr("bank5").w(this, FUNC(bbc_state::bbc_memorybm5_w)); /* 9000-bfff Rest of paged ROM/RAM area */
map(0xc000, 0xdfff).bankr("bank7").w(this, FUNC(bbc_state::bbc_memorybm7_w)); /* c000-dfff OS ROM or 8K of RAM HAZEL */
@ -297,6 +295,11 @@ void bbc_state::bbcm_mem(address_map &map)
map(0xfc00, 0xfeff).bankr("bank8").w(this, FUNC(bbc_state::bbcm_w)); /* processed directly because it can be ROM or hardware */
}
void bbc_state::bbcm_fetch(address_map &map)
{
map(0x0000, 0xffff).r(this, FUNC(bbc_state::bbcm_fetch_r));
}
INPUT_CHANGED_MEMBER(bbc_state::trigger_reset)
{
@ -672,14 +675,7 @@ INPUT_PORTS_END
INPUT_CHANGED_MEMBER(bbc_state::monitor_changed)
{
m_monitortype = m_bbcconfig.read_safe(0) &0x03;
}
INPUT_CHANGED_MEMBER(bbc_state::speech_changed)
{
// Switchable during runtime as some games (Hyper Sports, Space Fighter) are not compatible with Speech
m_Speech = m_bbcconfig.read_safe(0) & 0x04;
m_monitortype = m_bbcconfig.read_safe(0) & 0x03;
}
@ -700,26 +696,11 @@ static INPUT_PORTS_START(bbcb_config)
PORT_CONFSETTING( 0x01, "B&W")
PORT_CONFSETTING( 0x02, "Green")
PORT_CONFSETTING( 0x03, "Amber")
PORT_CONFNAME( 0x04, 0x04, "Speech Fitted" ) PORT_CHANGED_MEMBER(DEVICE_SELF, bbc_state, speech_changed, 0)
PORT_CONFSETTING( 0x00, DEF_STR( No ) )
PORT_CONFSETTING( 0x04, DEF_STR( Yes ) )
PORT_CONFNAME( 0x18, 0x00, "Sideways RAM Board")
PORT_CONFNAME( 0x0c, 0x00, "Sideways RAM Board")
PORT_CONFSETTING( 0x00, DEF_STR( None ) )
PORT_CONFSETTING( 0x08, "Solidisk 128K (fe62)" )
PORT_CONFSETTING( 0x10, "Acorn 64K (fe30)" )
PORT_CONFSETTING( 0x18, "Acorn 128K (fe30)" )
INPUT_PORTS_END
static INPUT_PORTS_START(bbcbp_config)
PORT_START("BBCCONFIG")
PORT_CONFNAME( 0x03, 0x00, "Monitor") PORT_CHANGED_MEMBER(DEVICE_SELF, bbc_state, monitor_changed, 0)
PORT_CONFSETTING( 0x00, "Colour")
PORT_CONFSETTING( 0x01, "B&W")
PORT_CONFSETTING( 0x02, "Green")
PORT_CONFSETTING( 0x03, "Amber")
PORT_CONFNAME( 0x04, 0x04, "Speech Fitted") PORT_CHANGED_MEMBER(DEVICE_SELF, bbc_state, speech_changed, 0)
PORT_CONFSETTING( 0x00, DEF_STR(No))
PORT_CONFSETTING( 0x04, DEF_STR(Yes))
//PORT_CONFSETTING( 0x04, "Solidisk 128K (fe62)" )
PORT_CONFSETTING( 0x08, "Acorn 64K (fe30)" )
PORT_CONFSETTING( 0x0c, "Acorn 128K (fe30)" )
INPUT_PORTS_END
static INPUT_PORTS_START(bbca)
@ -736,7 +717,7 @@ static INPUT_PORTS_START(bbcb)
INPUT_PORTS_END
static INPUT_PORTS_START(bbcbp)
PORT_INCLUDE(bbcbp_config)
PORT_INCLUDE(bbc_config)
PORT_INCLUDE(bbc_keyboard)
PORT_INCLUDE(bbc_dipswitch)
PORT_INCLUDE(bbcbp_links)
@ -782,26 +763,14 @@ INTERRUPT_GEN_MEMBER(bbc_state::bbcb_vsync)
FLOPPY_FORMATS_MEMBER( bbc_state::floppy_formats_bbc )
FLOPPY_ACORN_SSD_FORMAT,
FLOPPY_ACORN_DSD_FORMAT,
FLOPPY_ACORN_ADFS_OLD_FORMAT,
FLOPPY_ACORN_DOS_FORMAT,
FLOPPY_OPUS_DDOS_FORMAT,
FLOPPY_OPUS_DDCPM_FORMAT,
FLOPPY_FSD_FORMAT,
FLOPPY_PC_FORMAT
FLOPPY_FORMATS_END
FLOPPY_FORMATS_MEMBER( bbc_state::floppy_formats_bbcm )
FLOPPY_ACORN_SSD_FORMAT,
FLOPPY_ACORN_DSD_FORMAT,
FLOPPY_ACORN_ADFS_OLD_FORMAT,
FLOPPY_OPUS_DDCPM_FORMAT,
FLOPPY_ACORN_DOS_FORMAT,
FLOPPY_FSD_FORMAT,
FLOPPY_PC_FORMAT
FLOPPY_FORMATS_END
FLOPPY_FORMATS_MEMBER( bbc_state::floppy_formats_bbcmc )
FLOPPY_ACORN_ADFS_OLD_FORMAT
FLOPPY_FORMATS_END
static SLOT_INTERFACE_START( bbc_floppies_525 )
SLOT_INTERFACE("525sssd", FLOPPY_525_SSSD)
SLOT_INTERFACE("525sd", FLOPPY_525_SD)
@ -963,7 +932,7 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(bbc_state::bbcb)
bbca(config);
/* basic machine hardware */
MCFG_CPU_MODIFY( "maincpu" )
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(bbcb_nofdc_mem)
MCFG_MACHINE_START_OVERRIDE(bbc_state, bbcb)
@ -1090,8 +1059,9 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(bbc_state::bbcbp)
bbcb(config);
/* basic machine hardware */
MCFG_CPU_MODIFY( "maincpu" ) /* M6512 */
MCFG_CPU_MODIFY("maincpu") /* M6512 */
MCFG_CPU_PROGRAM_MAP(bbcbp_mem)
MCFG_CPU_OPCODES_MAP(bbcbp_fetch)
MCFG_MACHINE_START_OVERRIDE(bbc_state, bbcbp)
MCFG_MACHINE_RESET_OVERRIDE(bbc_state, bbcbp)
@ -1102,9 +1072,9 @@ MACHINE_CONFIG_START(bbc_state::bbcbp)
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(bbc_state, fdc_intrq_w))
MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(bbc_state, fdc_drq_w))
MCFG_FLOPPY_DRIVE_ADD("wd1770:0", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbcm)
MCFG_FLOPPY_DRIVE_ADD("wd1770:0", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbc)
MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_FLOPPY_DRIVE_ADD("wd1770:1", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbcm)
MCFG_FLOPPY_DRIVE_ADD("wd1770:1", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbc)
MCFG_FLOPPY_DRIVE_SOUND(true)
MACHINE_CONFIG_END
@ -1112,8 +1082,9 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(bbc_state::bbcbp128)
bbcbp(config);
/* basic machine hardware */
MCFG_CPU_MODIFY( "maincpu" ) /* M6512 */
MCFG_CPU_MODIFY("maincpu") /* M6512 */
MCFG_CPU_PROGRAM_MAP(bbcbp128_mem)
MCFG_CPU_OPCODES_MAP(bbcbp_fetch)
MCFG_MACHINE_START_OVERRIDE(bbc_state, bbcbp)
MCFG_MACHINE_RESET_OVERRIDE(bbc_state, bbcbp)
@ -1270,8 +1241,9 @@ MACHINE_CONFIG_END
MACHINE_CONFIG_START(bbc_state::reutapm)
bbcbp(config);
/* basic machine hardware */
MCFG_CPU_MODIFY( "maincpu" ) /* M6512 */
MCFG_CPU_MODIFY("maincpu") /* M6512 */
MCFG_CPU_PROGRAM_MAP(reutapm_mem)
MCFG_CPU_OPCODES_MAP(bbcbp_fetch)
/* sound hardware */
MCFG_DEVICE_REMOVE("mono")
@ -1294,7 +1266,6 @@ MACHINE_CONFIG_START(bbc_state::reutapm)
/* expansion ports */
MCFG_DEVICE_REMOVE("analogue")
MCFG_DEVICE_REMOVE("1mhzbus")
MACHINE_CONFIG_END
@ -1337,6 +1308,7 @@ MACHINE_CONFIG_START(bbc_state::bbcm)
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M65SC02, 16_MHz_XTAL/8) /* 2.00 MHz */
MCFG_CPU_PROGRAM_MAP(bbcm_mem)
MCFG_CPU_OPCODES_MAP(bbcm_fetch)
MCFG_CPU_VBLANK_INT_DRIVER("screen", bbc_state, bbcb_vsync) /* screen refresh interrupts */
MCFG_CPU_PERIODIC_INT_DRIVER(bbc_state, bbcb_keyscan, 1000) /* scan keyboard */
MCFG_QUANTUM_TIME(attotime::from_hz(60))
@ -1460,9 +1432,9 @@ MACHINE_CONFIG_START(bbc_state::bbcm)
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(bbc_state, fdc_intrq_w))
MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(bbc_state, fdc_drq_w))
MCFG_FLOPPY_DRIVE_ADD("wd1770:0", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbcm)
MCFG_FLOPPY_DRIVE_ADD("wd1770:0", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbc)
MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_FLOPPY_DRIVE_ADD("wd1770:1", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbcm)
MCFG_FLOPPY_DRIVE_ADD("wd1770:1", bbc_floppies_525, "525qd", bbc_state::floppy_formats_bbc)
MCFG_FLOPPY_DRIVE_SOUND(true)
/* econet */
@ -1654,9 +1626,9 @@ MACHINE_CONFIG_START(bbc_state::bbcmc)
MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(bbc_state, fdc_intrq_w))
MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(bbc_state, fdc_drq_w))
MCFG_FLOPPY_DRIVE_ADD_FIXED("wd1772:0", bbc_floppies_35, "35dd", bbc_state::floppy_formats_bbcmc)
MCFG_FLOPPY_DRIVE_ADD_FIXED("wd1772:0", bbc_floppies_35, "35dd", bbc_state::floppy_formats_bbc)
MCFG_FLOPPY_DRIVE_SOUND(true)
MCFG_FLOPPY_DRIVE_ADD("wd1772:1", bbc_floppies_35, nullptr, bbc_state::floppy_formats_bbcmc)
MCFG_FLOPPY_DRIVE_ADD("wd1772:1", bbc_floppies_35, nullptr, bbc_state::floppy_formats_bbc)
MCFG_FLOPPY_DRIVE_SOUND(true)
/* eeprom pcd8572 */

147
src/mame/includes/bbc.h
View File

@ -117,24 +117,20 @@ public:
};
DECLARE_FLOPPY_FORMATS(floppy_formats_bbc);
DECLARE_FLOPPY_FORMATS(floppy_formats_bbcm);
DECLARE_FLOPPY_FORMATS(floppy_formats_bbcmc);
DECLARE_WRITE8_MEMBER(bbc_page_selecta_w);
DECLARE_WRITE8_MEMBER(bbc_memorya1_w);
DECLARE_WRITE8_MEMBER(bbc_page_selectb_w);
DECLARE_WRITE8_MEMBER(bbc_memoryb3_w);
DECLARE_WRITE8_MEMBER(page_selecta_w);
DECLARE_WRITE8_MEMBER(page_selectb_w);
DECLARE_WRITE8_MEMBER(bbc_memoryb4_w);
DECLARE_WRITE8_MEMBER(bbc_page_selectbp_w);
DECLARE_WRITE8_MEMBER(bbc_memorybp1_w);
DECLARE_WRITE8_MEMBER(bbc_memorybp2_w);
DECLARE_READ8_MEMBER(bbcbp_fetch_r);
DECLARE_WRITE8_MEMBER(page_selectbp_w);
DECLARE_WRITE8_MEMBER(page_selectbp128_w);
DECLARE_WRITE8_MEMBER(bbc_memorybp4_w);
DECLARE_WRITE8_MEMBER(bbc_memorybp4_128_w);
DECLARE_WRITE8_MEMBER(bbc_memorybp6_128_w);
DECLARE_READ8_MEMBER(bbcm_ACCCON_read);
DECLARE_WRITE8_MEMBER(bbcm_ACCCON_write);
DECLARE_WRITE8_MEMBER(bbc_memorybp6_w);
DECLARE_READ8_MEMBER(bbcm_fetch_r);
DECLARE_READ8_MEMBER(bbcm_acccon_r);
DECLARE_WRITE8_MEMBER(bbcm_acccon_w);
DECLARE_WRITE8_MEMBER(page_selectbm_w);
DECLARE_WRITE8_MEMBER(bbc_memorybm1_w);
DECLARE_READ8_MEMBER(bbc_memorybm2_r);
DECLARE_WRITE8_MEMBER(bbc_memorybm2_w);
DECLARE_WRITE8_MEMBER(bbc_memorybm4_w);
DECLARE_WRITE8_MEMBER(bbc_memorybm5_w);
@ -184,7 +180,6 @@ public:
DECLARE_WRITE_LINE_MEMBER(bbc_vsync_changed);
DECLARE_WRITE_LINE_MEMBER(bbc_de_changed);
DECLARE_INPUT_CHANGED_MEMBER(monitor_changed);
DECLARE_INPUT_CHANGED_MEMBER(speech_changed);
void update_acia_rxd();
void update_acia_dcd();
void update_acia_cts();
@ -248,7 +243,9 @@ public:
void bbcb_nofdc_mem(address_map &map);
void bbcbp128_mem(address_map &map);
void bbcbp_mem(address_map &map);
void bbcbp_fetch(address_map &map);
void bbcm_mem(address_map &map);
void bbcm_fetch(address_map &map);
void reutapm_mem(address_map &map);
private:
@ -304,77 +301,70 @@ public: // HACK FOR MC6845
bool m_os01; // flag indicating whether OS 0.1 is being used
int m_monitortype; // monitor type (colour, green, amber)
int m_SWRAMtype; // this stores the setting for the SWRAM type being used
int m_Speech; // this stores the setting for Speech enabled/disabled
int m_swramtype; // this stores the setting for the SWRAM type being used
int m_ACCCON_IRR; // IRQ inputs
int m_swrbank; // This is the latch that holds the sideways ROM bank to read
bool m_swrbank_ram; // Does ROM bank contain RAM
int m_rombank; // This is the latch that holds the sideways ROM bank to read
int m_userport; // This stores the sideways RAM latch type.
// Acorn and others use the bbc_rombank latch to select the write bank to be used.(type 0)
// Solidisc use the BBC's userport to select the write bank to be used (type 1)
int m_pagedRAM; // BBC B+ memory handling
int m_paged_ram; // BBC B+ memory handling
int m_vdusel; // BBC B+ memory handling
bool m_lk18_ic41_paged_rom; // BBC Master Paged ROM/RAM select IC41
bool m_lk19_ic37_paged_rom; // BBC Master Paged ROM/RAM select IC37
/*
ACCCON
/*
ACCCON
b7 IRR 1=Causes an IRQ to the processor
b6 TST 1=Selects &FC00-&FEFF read from OS-ROM
b5 IFJ 1=Internal 1 MHz bus
0=External 1MHz bus
b4 ITU 1=Internal Tube
0=External Tube
b3 Y 1=Read/Write HAZEL &C000-&DFFF RAM
0=Read/Write ROM &C000-&DFFF OS-ROM
b2 X 1=Read/Write LYNNE
0=Read/WRITE main memory &3000-&8000
b1 E 1=Causes shadow if VDU code
0=Main all the time
b0 D 1=Display LYNNE as screen
0=Display main RAM screen
ACCCON is a read/write register
*/
b7 IRR 1=Causes an IRQ to the processor
b6 TST 1=Selects &FC00-&FEFF read from OS-ROM
b5 IFJ 1=Internal 1 MHz bus
0=External 1MHz bus
b4 ITU 1=Internal Tube
0=External Tube
b3 Y 1=Read/Write HAZEL &C000-&DFFF RAM
0=Read/Write ROM &C000-&DFFF OS-ROM
b2 X 1=Read/Write LYNNE
0=Read/WRITE main memory &3000-&8000
b1 E 1=Causes shadow if VDU code
0=Main all the time
b0 D 1=Display LYNNE as screen
0=Display main RAM screen
ACCCON is a read/write register
*/
int m_ACCCON;
int m_ACCCON_TST;
int m_ACCCON_IFJ;
int m_ACCCON_ITU;
int m_ACCCON_Y;
int m_ACCCON_X;
int m_ACCCON_E;
int m_ACCCON_D;
int m_acccon;
int m_acccon_irr;
int m_acccon_tst;
int m_acccon_ifj;
int m_acccon_itu;
int m_acccon_y;
int m_acccon_x;
int m_acccon_e;
int m_acccon_d;
/*
The addressable latch
This 8 bit addressable latch is operated from port B lines 0-3.
PB0-PB2 are set to the required address of the output bit to be set.
PB3 is set to the value which should be programmed at that bit.
The function of the 8 output bits from this latch are:-
/*
The addressable latch
This 8 bit addressable latch is operated from port B lines 0-3.
PB0-PB2 are set to the required address of the output bit to be set.
PB3 is set to the value which should be programmed at that bit.
The function of the 8 output bits from this latch are:-
B0 - Write Enable to the sound generator IC
B1 - READ select on the speech processor (B and B+)
R/nW control on CMOS RAM (Master only)
B2 - WRITE select on the speech processor
DS control on CMOS RAM (Master only)
B3 - Keyboard write enable
B4,B5 - these two outputs define the number to be added to the
start of screen address in hardware to control hardware scrolling:-
Mode Size Start of screen Size No.to add B5 B4
0,1,2 20K &3000 12K 1 1
3 16K &4000 16K 0 0
4,5 10K &5800 (or &1800) 22K 1 0
6 8K &6000 (or &2000) 24K 0 1
B6 - Operates the CAPS lock LED (Pin 17 keyboard connector)
B7 - Operates the SHIFT lock LED (Pin 16 keyboard connector)
*/
B0 - Write Enable to the sound generator IC
B1 - READ select on the speech processor (B and B+)
R/nW control on CMOS RAM (Master only)
B2 - WRITE select on the speech processor
DS control on CMOS RAM (Master only)
B3 - Keyboard write enable
B4,B5 - these two outputs define the number to be added to the
start of screen address in hardware to control hardware scrolling:-
Mode Size Start of screen Size No.to add B5 B4
0,1,2 20K &3000 12K 1 1
3 16K &4000 16K 0 0
4,5 10K &5800 (or &1800) 22K 1 0
6 8K &6000 (or &2000) 24K 0 1
B6 - Operates the CAPS lock LED (Pin 17 keyboard connector)
B7 - Operates the SHIFT lock LED (Pin 16 keyboard connector)
*/
int m_b0_sound;
int m_b1_speech_read;
@ -437,9 +427,6 @@ public: // HACK FOR MC6845
Video Code
***************************************/
int m_memorySize;
// this is the real location of the start of the BBC's ram in the emulation
// it can be changed if shadow ram is being used to point at the upper 32K of RAM
uint8_t *m_video_ram;
@ -470,10 +457,8 @@ public: // HACK FOR MC6845
rgb_t out_rgb(rgb_t entry);
void bbc_setvideoshadow(int vdusel);
void setvideoshadow(int vdusel);
void set_pixel_lookup();
int vdudriverset();
int bbcm_vdudriverset();
int bbc_keyboard(address_space &space, int data);
void bbcb_IC32_initialise(bbc_state *state);
void MC146818_set(address_space &space);

531
src/mame/machine/bbc.cpp
View File

@ -22,282 +22,254 @@
#include "imagedev/cassette.h"
/*************************
Model A memory handling functions
*************************/
/****************************************
BBC Model A memory handling functions
****************************************/
/* for the model A just address the 4 on board ROM sockets */
WRITE8_MEMBER(bbc_state::bbc_page_selecta_w)
WRITE8_MEMBER(bbc_state::page_selecta_w)
{
m_bank4->set_entry(data & 0x03);
/* for the Model A just address the 4 on board ROM sockets */
m_swrbank = data & 0x03;
m_swrbank_ram = false;
m_bank4->set_entry(m_swrbank);
}
WRITE8_MEMBER(bbc_state::bbc_memorya1_w)
/****************************************
BBC Model B memory handling functions
****************************************/
WRITE8_MEMBER(bbc_state::page_selectb_w)
{
m_region_maincpu->base()[offset]=data;
static const unsigned short swramtype[4][16] = {
// TODO: move sideways RAM boards to slot devices
{ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, // 0: none
{ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1 }, // 1: 128K (bank 8 to 15) Solidisk sideways ram userport bank latch (not implemented)
{ 0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0 }, // 2: 64K (banks 4 to 7) for Acorn sideways ram FE30 bank latch
{ 0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1 }, // 3: 128K (banks 8 to 15) for Acorn sideways ram FE30 bank latch
};
/* the Model B address all 16 of the ROM sockets */
m_swrbank = data & 0x0f;
m_swrbank_ram = swramtype[m_swramtype][m_swrbank] ? true : false;
m_bank4->set_entry(m_swrbank);
}
/*************************
Model B memory handling functions
*************************/
/* the model B address all 16 of the ROM sockets */
WRITE8_MEMBER(bbc_state::bbc_page_selectb_w)
{
m_rombank = data & 0x0f;
m_bank4->set_entry(m_rombank);
}
WRITE8_MEMBER(bbc_state::bbc_memoryb3_w)
{
if (m_ram->size() == 32*1024)
{
m_region_maincpu->base()[offset + 0x4000] = data;
}
else
{
m_region_maincpu->base()[offset] = data;
}
}
/* I have setup 3 types of sideways ram:
0: none
1: 128K (bank 8 to 15) Solidisc sideways ram userport bank latch
2: 64K (banks 4 to 7) for Acorn sideways ram FE30 bank latch
3: 128K (banks 8 to 15) for Acorn sideways ram FE30 bank latch
*/
static const unsigned short bbc_SWRAMtype1[16]={0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1};
static const unsigned short bbc_SWRAMtype2[16]={0,0,0,0,1,1,1,1,0,0,0,0,0,0,0,0};
static const unsigned short bbc_SWRAMtype3[16]={0,0,0,0,0,0,0,0,1,1,1,1,1,1,1,1};
WRITE8_MEMBER(bbc_state::bbc_memoryb4_w)
{
switch (m_SWRAMtype)
if (m_swrbank_ram)
{
case 1: if (bbc_SWRAMtype1[m_userport]) m_region_opt->base()[(m_userport << 14) + offset] = data;
case 2: if (bbc_SWRAMtype2[m_rombank]) m_region_opt->base()[(m_rombank << 14) + offset] = data;
case 3: if (bbc_SWRAMtype3[m_rombank]) m_region_opt->base()[(m_rombank << 14) + offset] = data;
m_region_opt->base()[(m_swrbank << 14) + offset] = data;
}
}
/****************************************/
/* BBC B Plus memory handling function */
/****************************************/
/****************************************
BBC Model B+ memory handling functions
****************************************/
/* this function should return true if
the instruction is in the VDU driver address ranged
these are set when:
PC is in the range c000 to dfff
or if pagedRAM set and PC is in the range a000 to afff
*/
int bbc_state::vdudriverset()
READ8_MEMBER(bbc_state::bbcbp_fetch_r)
{
int PC;
PC = machine().device("maincpu")->safe_pc(); // this needs to be set to the 6502 program counter
return (((PC >= 0xc000) && (PC <= 0xdfff)) || ((m_pagedRAM) && ((PC >= 0xa000) && (PC <= 0xafff))));
switch (offset & 0xf000)
{
case 0xa000:
/* Code executing from sideways RAM between 0xa000-0xafff will access the shadow RAM (if selected) */
if (m_vdusel && m_paged_ram)
{
m_bank2->set_base(m_region_maincpu->base() + 0xb000);
}
else
{
m_bank2->set_base(m_region_maincpu->base() + 0x3000);
}
break;
case 0xc000:
case 0xd000:
/* Access shadow RAM if VDU drivers and shadow RAM selected */
if (m_vdusel)
{
m_bank2->set_base(m_region_maincpu->base() + 0xb000);
}
else
{
m_bank2->set_base(m_region_maincpu->base() + 0x3000);
}
break;
default:
m_bank2->set_base(m_region_maincpu->base() + 0x3000);
break;
}
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
}
/* the model B Plus addresses all 16 of the ROM sockets plus the extra 12K of ram at 0x8000
and 20K of shadow ram at 0x3000 */
WRITE8_MEMBER(bbc_state::bbc_page_selectbp_w)
WRITE8_MEMBER(bbc_state::page_selectbp_w)
{
if ((offset&0x04)==0)
/* the Model B+ addresses all 16 ROM sockets and extra 12K of RAM at 0x8000 and 20K of shadow RAM at 0x3000 */
switch (offset & 0x07)
{
m_pagedRAM = BIT(data,7);
m_rombank = data & 0x0f;
case 0x00:
m_paged_ram = BIT(data,7);
if (m_pagedRAM)
m_swrbank = data & 0x0f;
m_swrbank_ram = false;
if (m_paged_ram)
{
/* if paged ram then set 8000 to afff to read from the ram 8000 to afff */
/* if paged RAM then set 0x8000 to 0xafff to read from the RAM 8000 to 0xafff */
m_bank4->set_entry(0x10);
}
else
{
/* if paged rom then set the rom to be read from 8000 to afff */
m_bank4->set_entry(m_rombank);
/* if paged ROM then set the ROM to be read from 0x8000 to 0xafff */
m_bank4->set_entry(m_swrbank);
};
/* set the rom to be read from b000 to bfff */
m_bank6->set_entry(m_rombank);
}
else
{
//the video display should now use this flag to display the shadow ram memory
m_vdusel=BIT(data,7);
bbc_setvideoshadow(m_vdusel);
//need to make the video display do a full screen refresh for the new memory area
m_bank2->set_base(m_region_maincpu->base() + 0x3000);
/* set the ROM to be read from 0xb000 to 0xbfff */
m_bank6->set_entry(m_swrbank);
break;
case 0x04:
/* the video display should now use this flag to display the shadow RAM memory */
m_vdusel = BIT(data,7);
setvideoshadow(m_vdusel);
break;
}
}
/* write to the normal memory from 0x0000 to 0x2fff
the writes to this memory are just done the normal
way */
WRITE8_MEMBER(bbc_state::bbc_memorybp1_w)
WRITE8_MEMBER(bbc_state::page_selectbp128_w)
{
m_region_maincpu->base()[offset]=data;
}
/* the BBC B+ 128K has extra RAM mapped in replacing the ROM banks 0,1,c and d. */
static const unsigned short swram_banks[16] = { 1,1,0,0,0,0,0,0,0,0,0,0,1,1,0,0 };
switch (offset & 0x07)
{
case 0x00:
m_paged_ram = BIT(data, 7);
WRITE8_MEMBER(bbc_state::bbc_memorybp2_w)
{
uint8_t *RAM = m_region_maincpu->base();
if (m_vdusel==0)
{
// not in shadow ram mode so just write to normal ram
RAM[offset + 0x3000] = data;
}
else
{
if (vdudriverset())
m_swrbank = data & 0x0f;
m_swrbank_ram = swram_banks[m_swrbank] ? true : false;
if (m_paged_ram)
{
// if VDUDriver set then write to shadow ram
RAM[offset + 0xb000] = data;
/* if paged RAM then set 0x8000 to 0xafff to read from the RAM 8000 to 0xafff */
m_bank4->set_entry(0x10);
}
else
{
// else write to normal ram
RAM[offset + 0x3000] = data;
/* if paged ROM then set the ROM to be read from 0x8000 to 0xafff */
m_bank4->set_entry(m_swrbank);
}
/* set the ROM to be read from 0xb000 to 0xbfff */
m_bank6->set_entry(m_swrbank);
break;
case 0x04:
/* the video display should now use this flag to display the shadow RAM memory */
m_vdusel = BIT(data, 7);
setvideoshadow(m_vdusel);
break;
}
}
/* if the pagedRAM is set write to RAM between 0x8000 to 0xafff
otherwise this area contains ROM so no write is required */
WRITE8_MEMBER(bbc_state::bbc_memorybp4_w)
{
if (m_pagedRAM)
if (m_paged_ram)
{
m_region_maincpu->base()[offset+0x8000]=data;
m_region_maincpu->base()[offset + 0x8000] = data;
}
else if (m_swrbank_ram)
{
m_region_opt->base()[offset + (m_swrbank << 14)] = data;
}
}
/* the BBC B plus 128K had extra ram mapped in replacing the
rom bank 0,1,c and d.
The function memorybp3_128_w handles memory writes from 0x8000 to 0xafff
which could either be sideways ROM, paged RAM, or sideways RAM.
The function memorybp4_128_w handles memory writes from 0xb000 to 0xbfff
which could either be sideways ROM or sideways RAM */
static const unsigned short bbc_b_plus_sideways_ram_banks[16]={ 1,1,0,0,0,0,0,0,0,0,0,0,1,1,0,0 };
WRITE8_MEMBER(bbc_state::bbc_memorybp4_128_w)
WRITE8_MEMBER(bbc_state::bbc_memorybp6_w)
{
if (m_pagedRAM)
if (m_swrbank_ram)
{
m_region_maincpu->base()[offset+0x8000]=data;
}
else
{
if (bbc_b_plus_sideways_ram_banks[m_rombank])
{
m_region_opt->base()[offset+(m_rombank<<14)]=data;
}
}
}
WRITE8_MEMBER(bbc_state::bbc_memorybp6_128_w)
{
if (bbc_b_plus_sideways_ram_banks[m_rombank])
{
m_region_opt->base()[offset+(m_rombank<<14)+0x3000]=data;
m_region_opt->base()[offset + (m_swrbank << 14) + 0x3000] = data;
}
}
/****************************************/
/* BBC Master functions */
/****************************************/
/****************************************
BBC Master memory handling functions
****************************************/
/*
ROMSEL - &FE30 write Only
B7 RAM 1=Page in ANDY &8000-&8FFF
0=Page in ROM &8000-&8FFF
B6 Not Used
B5 Not Used
B4 Not Used
B3-B0 Rom/Ram Bank Select
ROMSEL - &FE30 write only
b7 RAM 1 = Page in ANDY &8000-&8FFF
0 = Page in ROM &8000-&8FFF
b6 Not Used
b5 Not Used
b4 Not Used
b3-b0 ROM/RAM Bank Select
ACCCON
ACCCON - &FE34 read/write register
b7 IRR 1 = Causes an IRQ to the processor
b6 TST 1 = Selects &FC00-&FEFF read from OS-ROM
b5 IFJ 1 = Internal 1MHz bus
0 = External 1MHz bus
b4 ITU 1 = Internal Tube
0 = External Tube
b3 Y 1 = Read/Write HAZEL &C000-&DFFF RAM
0 = Read/Write ROM &C000-&DFFF OS-ROM
b2 X 1 = Read/Write LYNNE
0 = Read/Write main memory &3000-&8000
b1 E 1 = Causes shadow if VDU code
0 = Main all the time
b0 D 1 = Display LYNNE as screen
0 = Display main RAM screen
b7 IRR 1=Causes an IRQ to the processor
b6 TST 1=Selects &FC00-&FEFF read from OS-ROM
b5 IFJ 1=Internal 1MHz bus
0=External 1MHz bus
b4 ITU 1=Internal Tube
0=External Tube
b3 Y 1=Read/Write HAZEL &C000-&DFFF RAM
0=Read/Write ROM &C000-&DFFF OS-ROM
b2 X 1=Read/Write LYNNE
0=Read/WRITE main memory &3000-&8000
b1 E 1=Causes shadow if VDU code
0=Main all the time
b0 D 1=Display LYNNE as screen
0=Display main RAM screen
ACCCON is a read/write register
HAZEL is the 8K of RAM used by the MOS, filing system, and other ROMs at &C000-&DFFF
ANDY is the name of the 4K of RAM used by the MOS at &8000-&8FFF
b7:This causes an IRQ to occur. If you set this bit, you must write a routine on IRQ2V to clear it.
b6:If set, this switches in the ROM at &FD00-&FEFF for reading, writes to these addresses are still directed to the I/O
The MOS will not work properly with this but set. the Masters OS uses this feature to place some of the reset code in this area,
which is run at powerup.
b3:If set, access to &C000-&DFFF are directed to HAZEL, an 8K bank of RAM. IF clear, then operating system ROM is read.
b2:If set, read/write access to &3000-&7FFF are directed to the LYNNE, the shadow screen RAM. If clear access is made to the main RAM.
b1:If set, when the program counter is between &C000 and &DFFF, read/write access is directed to the LYNNE shadow RAM.
if the program counter is anywhere else main ram is accessed.
HAZEL is the 8K of RAM used by the MOS, filing system, and other ROMs at &C000-&DFFF
ANDY is the name of the 4K of RAM used by the MOS at &8000-&8FFF
*/
READ8_MEMBER(bbc_state::bbcm_ACCCON_read)
READ8_MEMBER(bbc_state::bbcm_fetch_r)
{
logerror("ACCCON read %d\n",offset);
return m_ACCCON;
if (offset >= 0xc000 && offset <= 0xdfff)
{
if (m_acccon_e)
{
m_bank2->set_base(m_region_maincpu->base() + 0xb000);
}
else
{
m_bank2->set_base(m_region_maincpu->base() + 0x3000);
}
}
return m_maincpu->space(AS_PROGRAM).read_byte(offset);
}
WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
READ8_MEMBER(bbc_state::bbcm_acccon_r)
{
int tempIRR;
m_ACCCON=data;
return m_acccon;
}
logerror("ACCCON write %d %d \n",offset,data);
WRITE8_MEMBER(bbc_state::bbcm_acccon_w)
{
m_acccon = data;
tempIRR=m_ACCCON_IRR;
m_acccon_irr = BIT(data,7);
m_acccon_tst = BIT(data,6);
m_acccon_ifj = BIT(data,5);
m_acccon_itu = BIT(data,4);
m_acccon_y = BIT(data,3);
m_acccon_x = BIT(data,2);
m_acccon_e = BIT(data,1);
m_acccon_d = BIT(data,0);
m_ACCCON_IRR = BIT(data,7);
m_ACCCON_TST = BIT(data,6);
m_ACCCON_IFJ = BIT(data,5);
m_ACCCON_ITU = BIT(data,4);
m_ACCCON_Y = BIT(data,3);
m_ACCCON_X = BIT(data,2);
m_ACCCON_E = BIT(data,1);
m_ACCCON_D = BIT(data,0);
/* Bit IRR causes Interrupt Request. */
m_irqs->in_w<6>(m_acccon_irr);
if (tempIRR!=m_ACCCON_IRR)
{
m_irqs->in_w<3>(m_ACCCON_IRR);
}
if (m_ACCCON_Y)
/* Bit Y causes 8K of RAM (HAZEL) to be overlayed on the MOS VDU drivers. */
if (m_acccon_y)
{
m_bank7->set_base(m_region_maincpu->base() + 0x9000);
}
@ -306,10 +278,11 @@ WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
m_bank7->set_base(m_region_os->base());
}
bbc_setvideoshadow(m_ACCCON_D);
/* Bit D causes the CRT controller to display the contents of LYNNE. */
setvideoshadow(m_acccon_d);
if (m_ACCCON_X)
/* Bit X causes all accesses to 0x3000-0x7fff to be re-directed to LYNNE.*/
if (m_acccon_x)
{
m_bank2->set_base(m_region_maincpu->base() + 0xb000);
}
@ -318,10 +291,10 @@ WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
m_bank2->set_base(m_region_maincpu->base() + 0x3000);
}
/* ACCCON_TST controls paging of rom reads in the 0xFC00-0xFEFF region */
/* Bit TST controls paging of ROM reads in the 0xfc00-0xfeff region */
/* if 0 the I/O is paged for both reads and writes */
/* if 1 the ROM is paged in for reads but writes still go to I/O */
if (m_ACCCON_TST)
if (m_acccon_tst)
{
m_bank8->set_base(m_region_os->base() + 0x3c00);
space.install_read_bank(0xfc00, 0xfeff, "bank8");
@ -332,98 +305,76 @@ WRITE8_MEMBER(bbc_state::bbcm_ACCCON_write)
}
}
int bbc_state::bbcm_vdudriverset()
{
int PC;
PC = machine().device("maincpu")->safe_pc();
return ((PC >= 0xc000) && (PC <= 0xdfff));
}
WRITE8_MEMBER(bbc_state::page_selectbm_w)
{
m_pagedRAM = (data & 0x80) >> 7;
m_rombank = data & 0x0f;
m_paged_ram = (data & 0x80) >> 7;
m_swrbank = data & 0x0f;
if (m_lk19_ic37_paged_rom && (m_rombank == 4 || m_rombank == 5)) m_pagedRAM = 0;
if (m_lk18_ic41_paged_rom && (m_rombank == 6 || m_rombank == 7)) m_pagedRAM = 0;
if (m_pagedRAM)
if ((!m_lk19_ic37_paged_rom && (m_swrbank == 4 || m_swrbank == 5)) || (!m_lk18_ic41_paged_rom && (m_swrbank == 6 || m_swrbank == 7)))
{
m_bank4->set_entry(0x10);
m_bank5->set_entry(m_rombank);
/* links are set for RAM so make read/write */
m_swrbank_ram = true;
}
else
{
m_bank4->set_entry(m_rombank);
m_bank5->set_entry(m_rombank);
/* links are set for ROM so make read-only */
m_swrbank_ram = false;
}
if (m_paged_ram)
{
m_bank4->set_entry(0x10);
m_bank5->set_entry(m_swrbank);
}
else
{
m_bank4->set_entry(m_swrbank);
m_bank5->set_entry(m_swrbank);
}
}
WRITE8_MEMBER(bbc_state::bbc_memorybm1_w)
{
m_region_maincpu->base()[offset] = data;
}
WRITE8_MEMBER(bbc_state::bbc_memorybm2_w)
{
uint8_t *RAM = m_region_maincpu->base();
if (m_ACCCON_X)
if (m_acccon_x || (m_acccon_e && m_vdusel))
{
RAM[offset + 0xb000] = data;
m_region_maincpu->base()[offset + 0xb000] = data;
}
else
{
if (m_ACCCON_E && bbcm_vdudriverset())
{
RAM[offset + 0xb000] = data;
}
else
{
RAM[offset + 0x3000] = data;
}
m_region_maincpu->base()[offset + 0x3000] = data;
}
}
WRITE8_MEMBER(bbc_state::bbc_memorybm4_w)
{
if (m_pagedRAM)
if (m_paged_ram)
{
m_region_maincpu->base()[offset+0x8000] = data;
m_region_maincpu->base()[offset + 0x8000] = data;
}
else
else if (m_swrbank_ram)
{
if ((!m_lk18_ic41_paged_rom && (m_rombank == 6 || m_rombank == 7)) || (!m_lk19_ic37_paged_rom && (m_rombank == 4 || m_rombank == 5)))
{
m_region_opt->base()[offset+(m_rombank<<14)] = data;
}
m_region_opt->base()[offset + (m_swrbank << 14)] = data;
}
}
WRITE8_MEMBER(bbc_state::bbc_memorybm5_w)
{
if ((!m_lk18_ic41_paged_rom && (m_rombank == 6 || m_rombank == 7)) || (!m_lk19_ic37_paged_rom && (m_rombank == 4 || m_rombank == 5)))
if (m_swrbank_ram)
{
m_region_opt->base()[offset+(m_rombank<<14) + 0x1000] = data;
m_region_opt->base()[offset + (m_swrbank << 14) + 0x1000] = data;
}
}
WRITE8_MEMBER(bbc_state::bbc_memorybm7_w)
{
if (m_ACCCON_Y)
if (m_acccon_y)
{
m_region_maincpu->base()[offset+0x9000] = data;
m_region_maincpu->base()[offset + 0x9000] = data;
}
}
/******************************************************************************
&FC00-&FCFF FRED
&FC00-&FC03 Byte-Wide Expansion RAM
@ -493,7 +444,7 @@ READ8_MEMBER(bbc_state::bbcm_r)
if ((myo>=0x28) && (myo<=0x2f) && (m_wd1772)) return m_wd1772->read(space, myo-0x28); /* 1772 Controller */
if ((myo>=0x28) && (myo<=0x2f)) return 0xfe; /* No Controller */
if ((myo>=0x30) && (myo<=0x33)) return 0xfe;
if ((myo>=0x34) && (myo<=0x37)) return bbcm_ACCCON_read(space, myo-0x34); /* ACCCON */
if ((myo>=0x34) && (myo<=0x37)) return bbcm_acccon_r(space, myo-0x34); /* ACCCON */
if ((myo>=0x38) && (myo<=0x3f)) return 0xfe; /* NC ?? */
if ((myo>=0x40) && (myo<=0x5f)) return m_via6522_0->read(space, myo-0x40);
if ((myo>=0x60) && (myo<=0x7f)) return m_via6522_1 ? m_via6522_1->read(space, myo-0x60) : 0xfe;
@ -502,8 +453,8 @@ READ8_MEMBER(bbc_state::bbcm_r)
if ((myo>=0xc0) && (myo<=0xdf)) return 0xff;
if ((myo>=0xe0) && (myo<=0xff))
{
if (m_intube && m_ACCCON_ITU) return m_intube->host_r(space, myo-0xe0); /* Internal TUBE */
if (m_extube && !m_ACCCON_ITU) return m_extube->host_r(space, myo-0xe0); /* External TUBE */
if (m_intube && m_acccon_itu) return m_intube->host_r(space, myo-0xe0); /* Internal TUBE */
if (m_extube && !m_acccon_itu) return m_extube->host_r(space, myo-0xe0); /* External TUBE */
}
}
return 0xfe;
@ -527,7 +478,7 @@ WRITE8_MEMBER(bbc_state::bbcm_w)
if ((myo>=0x24) && (myo<=0x27) && (m_wd1772)) bbcm_wd1772l_write(space, myo-0x24, data); /* disc control latch */
if ((myo>=0x28) && (myo<=0x2f) && (m_wd1772)) m_wd1772->write(space, myo-0x28, data); /* 1772 Controller */
if ((myo>=0x30) && (myo<=0x33)) page_selectbm_w(space, myo-0x30, data); /* ROMSEL */
if ((myo>=0x34) && (myo<=0x37)) bbcm_ACCCON_write(space, myo-0x34, data); /* ACCCON */
if ((myo>=0x34) && (myo<=0x37)) bbcm_acccon_w(space, myo-0x34, data); /* ACCCON */
//if ((myo>=0x38) && (myo<=0x3f)) /* NC ?? */
if ((myo>=0x40) && (myo<=0x5f)) m_via6522_0->write(space, myo-0x40, data);
if ((myo>=0x60) && (myo<=0x7f) && (m_via6522_1)) m_via6522_1->write(space, myo-0x60, data);
@ -536,8 +487,8 @@ WRITE8_MEMBER(bbc_state::bbcm_w)
//if ((myo>=0xc0) && (myo<=0xdf))
if ((myo>=0xe0) && (myo<=0xff))
{
if (m_intube && m_ACCCON_ITU) m_intube->host_w(space, myo-0xe0, data); /* Internal TUBE */
if (m_extube && !m_ACCCON_ITU) m_extube->host_w(space, myo-0xe0, data); /* External TUBE */
if (m_intube && m_acccon_itu) m_intube->host_w(space, myo-0xe0, data); /* Internal TUBE */
if (m_extube && !m_acccon_itu) m_extube->host_w(space, myo-0xe0, data); /* External TUBE */
}
}
}
@ -1018,7 +969,7 @@ READ8_MEMBER(bbc_state::bbcb_via_system_read_portb)
/**************************************
BBC Joystick Support
BBC Joystick Support
**************************************/
UPD7002_GET_ANALOGUE(bbc_state::BBC_get_analogue_input)
@ -1649,23 +1600,18 @@ MACHINE_START_MEMBER(bbc_state, bbca)
MACHINE_RESET_MEMBER(bbc_state, bbca)
{
m_monitortype = m_bbcconfig.read_safe(0) & 0x03;
m_Speech = m_bbcconfig.read_safe(0) & 0x04;
m_SWRAMtype = m_bbcconfig.read_safe(0) & 0x18;
m_swramtype = (m_bbcconfig.read_safe(0) & 0x0c) >> 2;
uint8_t *RAM = m_region_maincpu->base();
m_bank1->set_base(RAM);
m_bank1->set_base(m_region_maincpu->base());
if (m_ram->size() == 32*1024)
{
/* 32K Model A */
m_bank3->set_base(RAM + 0x4000);
m_memorySize=32;
m_bank3->set_base(m_region_maincpu->base() + 0x4000);
}
else
{
/* 16K just repeat the lower 16K*/
m_bank3->set_base(RAM);
m_memorySize=16;
m_bank3->set_base(m_region_maincpu->base());
}
m_bank4->set_entry(0);
@ -1684,14 +1630,10 @@ MACHINE_START_MEMBER(bbc_state, bbcb)
MACHINE_RESET_MEMBER(bbc_state, bbcb)
{
m_monitortype = m_bbcconfig.read_safe(0) & 0x03;
m_Speech = m_bbcconfig.read_safe(1) & 0x04;
m_SWRAMtype = m_bbcconfig.read_safe(0) & 0x18;
m_swramtype = (m_bbcconfig.read_safe(0) & 0x0c) >> 2;
uint8_t *RAM = m_region_maincpu->base();
m_bank1->set_base(RAM);
m_bank3->set_base(RAM + 0x4000);
m_memorySize=32;
m_bank1->set_base(m_region_maincpu->base());
m_bank3->set_base(m_region_maincpu->base() + 0x4000);
m_bank4->set_entry(0);
m_bank7->set_base(m_region_os->base()); /* bank 7 points at the OS rom from c000 to ffff */
@ -1705,8 +1647,7 @@ MACHINE_RESET_MEMBER(bbc_state, torch)
MACHINE_RESET_CALL_MEMBER(bbcb);
m_monitortype = monitor_type_t::COLOUR;
m_Speech = 1;
m_SWRAMtype = 0;
m_swramtype = 0;
}
@ -1723,8 +1664,7 @@ MACHINE_START_MEMBER(bbc_state, bbcbp)
MACHINE_RESET_MEMBER(bbc_state, bbcbp)
{
m_monitortype = m_bbcconfig.read_safe(0) & 0x03;
m_Speech = m_bbcconfig.read_safe(1) & 0x04;
m_SWRAMtype = 0;
m_swramtype = 0;
m_bank1->set_base(m_region_maincpu->base());
m_bank2->set_base(m_region_maincpu->base() + 0x3000); /* bank 2 screen/shadow ram from 3000 to 7fff */
@ -1758,11 +1698,10 @@ MACHINE_START_MEMBER(bbc_state, bbcm)
MACHINE_RESET_MEMBER(bbc_state, bbcm)
{
m_monitortype = m_bbcconfig.read_safe(0) & 0x03;
m_Speech = 0;
m_SWRAMtype = 0;
m_swramtype = 0;
m_bank1->set_base(m_region_maincpu->base()); /* bank 1 regular lower ram from 0000 to 2fff */
m_bank2->set_base(m_region_maincpu->base() + 0x3000); /* bank 2 screen/shadow ram from 3000 to 7fff */
m_bank1->set_base(m_region_maincpu->base()); /* bank 1 regular lower RAM from 0000 to 2fff */
m_bank2->set_base(m_region_maincpu->base() + 0x3000); /* bank 2 screen/shadow RAM from 3000 to 7fff */
m_bank4->set_entry(0);
m_bank5->set_entry(0);
m_bank7->set_base(m_region_os->base()); /* bank 6 OS rom of RAM from c000 to dfff */
@ -1789,8 +1728,7 @@ MACHINE_RESET_MEMBER(bbc_state, ltmpbp)
MACHINE_RESET_CALL_MEMBER(bbcbp);
m_monitortype = monitor_type_t::GREEN;
m_Speech = 1;
m_SWRAMtype = 0;
m_swramtype = 0;
}
MACHINE_RESET_MEMBER(bbc_state, ltmpm)
@ -1798,8 +1736,7 @@ MACHINE_RESET_MEMBER(bbc_state, ltmpm)
MACHINE_RESET_CALL_MEMBER(bbcm);
m_monitortype = monitor_type_t::GREEN;
m_Speech = 0;
m_SWRAMtype = 0;
m_swramtype = 0;
}

7
src/mame/video/bbc.cpp
View File

@ -77,7 +77,7 @@ uint16_t bbc_state::calculate_video_address(uint16_t ma, uint8_t ra)
else
m = ((ma & 0xff)<<3) | (s<<11) | (ra & 0x7);
if (m_memorySize == 16) m &= 0x3fff;
if (m_ram->size() == 16 * 1024) m &= 0x3fff;
return m;
}
@ -281,13 +281,13 @@ WRITE_LINE_MEMBER(bbc_state::bbc_de_changed)
/**** BBC B+/Master Shadow Ram change ****/
void bbc_state::bbc_setvideoshadow(int vdusel)
void bbc_state::setvideoshadow(int vdusel)
{
// LYNNE lives at 0xb000 in our map, but the offset we use here is 0x8000
// as the video circuitry will already be looking at 0x3000 or so above
// the offset.
if (vdusel)
m_video_ram = m_region_maincpu->base()+0x8000;
m_video_ram = m_region_maincpu->base() + 0x8000;
else
m_video_ram = m_region_maincpu->base();
}
@ -304,5 +304,4 @@ VIDEO_START_MEMBER(bbc_state, bbc)
set_pixel_lookup();
m_video_ram = m_region_maincpu->base();
m_memorySize = m_ram->size() / 1024;
}