diff --git a/src/emu/bus/isa/s3virge.c b/src/emu/bus/isa/s3virge.c index fda0f63111c..0a279c2c8e3 100644 --- a/src/emu/bus/isa/s3virge.c +++ b/src/emu/bus/isa/s3virge.c @@ -50,7 +50,7 @@ void s3virge_vga_device::device_start() vga.svga_intf.seq_regcount = 0x1c; vga.svga_intf.crtc_regcount = 0x19; vga.svga_intf.vram_size = 0x400000; - vga.memory.resize(vga.svga_intf.vram_size); + vga.memory.resize_and_clear(vga.svga_intf.vram_size); save_item(vga.memory,"Video RAM"); save_pointer(vga.crtc.data,"CRTC Registers",0x100); save_pointer(vga.sequencer.data,"Sequencer Registers",0x100); @@ -83,6 +83,22 @@ void s3virgedx_vga_device::device_start() s3.id_cr30 = 0xe1; // CR30 } +void s3virge_vga_device::device_reset() +{ + vga_device::device_reset(); + // Power-on strapping bits. Sampled at reset, but can be modified later. + // These are just assumed defaults. + s3.strapping = 0x000f0912; +} + +void s3virgedx_vga_device::device_reset() +{ + vga_device::device_reset(); + // Power-on strapping bits. Sampled at reset, but can be modified later. + // These are just assumed defaults. + s3.strapping = 0x000f0912; +} + UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index) { UINT8 res; @@ -112,7 +128,7 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index) res = s3.crt_reg_lock; break; case 0x36: // Configuration register 1 - res = 0x12; // PCI (not really), 1-cycle EDO + res = s3.strapping & 0x000000ff; // PCI (not really), Fast Page Mode DRAM if(vga.svga_intf.vram_size == 0x200000) res |= 0x80; else if(vga.svga_intf.vram_size == 0x400000) @@ -121,7 +137,7 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index) res |= 0x80; // shouldn't get here... break; case 0x37: // Configuration register 2 - res = 0x09; // enable chipset, 64k BIOS size, internal DCLK/MCLK + res = (s3.strapping & 0x0000ff00) >> 8; // enable chipset, 64k BIOS size, internal DCLK/MCLK break; case 0x38: res = s3.reg_lock1; @@ -188,7 +204,7 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index) res = s3.ext_misc_ctrl_2; break; case 0x68: // Configuration register 3 - res = 0x03; // no /CAS,/OE stretch time + res = (s3.strapping & 0x00ff0000) >> 16; // no /CAS,/OE stretch time, 32-bit data bus size break; case 0x69: res = vga.crtc.start_addr_latch >> 16; @@ -197,7 +213,7 @@ UINT8 s3virge_vga_device::s3_crtc_reg_read(UINT8 index) res = svga.bank_r & 0x7f; break; case 0x6f: // Configuration register 4 - res = 0x18; // Serial port I/O at port 0xe8, Serial port I/O disabled (MMIO only), no /WE delay + res = (s3.strapping & 0xff000000) >> 24; // LPB(?) mode, Serial port I/O at port 0xe8, Serial port I/O disabled (MMIO only), no WE delay break; default: res = vga.crtc.data[index]; @@ -276,6 +292,20 @@ void s3virge_vga_device::s3_crtc_reg_write(UINT8 index, UINT8 data) svga.bank_w = data & 0xf; svga.bank_r = svga.bank_w; break; + case 0x36: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0xffffff00) | data; + logerror("CR36: Strapping data = %08x\n",s3.strapping); + } + break; + case 0x37: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0xffff00ff) | (data << 8); + logerror("CR37: Strapping data = %08x\n",s3.strapping); + } + break; case 0x38: s3.reg_lock1 = data; break; @@ -518,6 +548,13 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h s3_define_video_mode(); //printf("%02x X\n",data); break; + case 0x68: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0xff00ffff) | (data << 16); + logerror("CR68: Strapping data = %08x\n",s3.strapping); + } + break; case 0x69: vga.crtc.start_addr_latch &= ~0x1f0000; vga.crtc.start_addr_latch |= ((data & 0x1f) << 16); @@ -527,6 +564,13 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h svga.bank_w = data & 0x3f; svga.bank_r = svga.bank_w; break; + case 0x6f: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0x00ffffff) | (data << 24); + logerror("CR6F: Strapping data = %08x\n",s3.strapping); + } + break; default: if(LOG_REG) logerror("S3: CR%02X write %02x\n",index,data); break; diff --git a/src/emu/bus/isa/s3virge.h b/src/emu/bus/isa/s3virge.h index 22f8311144e..105b493cd14 100644 --- a/src/emu/bus/isa/s3virge.h +++ b/src/emu/bus/isa/s3virge.h @@ -33,6 +33,7 @@ public: protected: // device-level overrides virtual void device_start(); + virtual void device_reset(); private: virtual UINT8 s3_crtc_reg_read(UINT8 index); @@ -53,6 +54,7 @@ public: protected: // device-level overrides virtual void device_start(); + virtual void device_reset(); }; // device type definition diff --git a/src/emu/video/pc_vga.c b/src/emu/video/pc_vga.c index 4aaa4648e37..53a10dbc107 100644 --- a/src/emu/video/pc_vga.c +++ b/src/emu/video/pc_vga.c @@ -1996,6 +1996,14 @@ void vga_device::device_reset() vga.dac.mask = 0xff; } +void s3_vga_device::device_reset() +{ + vga_device::device_reset(); + // Power-on strapping bits. Sampled at reset, but can be modified later. + // These are just assumed defaults. + s3.strapping = 0x000f0b1e; +} + READ8_MEMBER(vga_device::mem_r) { /* TODO: check me */ @@ -2759,7 +2767,7 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index) res = s3.crt_reg_lock; break; case 0x36: // Configuration register 1 - res = 0x1e; // PCI (not really), Fast Page Mode DRAM + res = s3.strapping & 0x000000ff; // PCI (not really), Fast Page Mode DRAM if(vga.svga_intf.vram_size == 0x80000) res |= 0xe0; else if(vga.svga_intf.vram_size == 0x100000) @@ -2772,7 +2780,7 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index) res |= 0xe0; // shouldn't get here... break; case 0x37: // Configuration register 2 - res = 0x09; // enable chipset, 64k BIOS size, internal DCLK/MCLK + res = (s3.strapping & 0x0000ff00) >> 8; // enable chipset, 64k BIOS size, internal DCLK/MCLK break; case 0x38: res = s3.reg_lock1; @@ -2840,7 +2848,7 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index) res = s3.ext_misc_ctrl_2; break; case 0x68: // Configuration register 3 - res = 0x03; // no /CAS,/OE stretch time, 32-bit data bus size + res = (s3.strapping & 0x00ff0000) >> 16; // no /CAS,/OE stretch time, 32-bit data bus size break; case 0x69: res = vga.crtc.start_addr_latch >> 16; @@ -2848,8 +2856,8 @@ UINT8 s3_vga_device::s3_crtc_reg_read(UINT8 index) case 0x6a: res = svga.bank_r & 0x7f; break; - case 0x6f: // Configuration register 4 - res = 0x18; // LPB(?) mode, Serial port I/O at port 0xe8, Serial port I/O disabled (MMIO only), no WE delay + case 0x6f: // Configuration register 4 (Trio64V+) + res = (s3.strapping & 0xff000000) >> 24; // LPB(?) mode, Serial port I/O at port 0xe8, Serial port I/O disabled (MMIO only), no WE delay break; default: res = vga.crtc.data[index]; @@ -2921,6 +2929,20 @@ void s3_vga_device::s3_crtc_reg_write(UINT8 index, UINT8 data) svga.bank_w = data & 0xf; svga.bank_r = svga.bank_w; break; + case 0x36: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0xffffff00) | data; + logerror("CR36: Strapping data = %08x\n",s3.strapping); + } + break; + case 0x37: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0xffff00ff) | (data << 8); + logerror("CR37: Strapping data = %08x\n",s3.strapping); + } + break; case 0x38: s3.reg_lock1 = data; break; @@ -3159,6 +3181,13 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h s3.ext_misc_ctrl_2 = data; s3_define_video_mode(); break; + case 0x68: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0xff00ffff) | (data << 16); + logerror("CR68: Strapping data = %08x\n",s3.strapping); + } + break; case 0x69: vga.crtc.start_addr_latch &= ~0x1f0000; vga.crtc.start_addr_latch |= ((data & 0x1f) << 16); @@ -3170,6 +3199,13 @@ bit 0 Vertical Total bit 10. Bit 10 of the Vertical Total register (3d4h if(data & 0x60) popmessage("TODO: s3 bank selects above 1M\n"); break; + case 0x6f: + if(s3.reg_lock2 == 0xa5) + { + s3.strapping = (s3.strapping & 0x00ffffff) | (data << 24); + logerror("CR6F: Strapping data = %08x\n",s3.strapping); + } + break; default: if(LOG_8514) logerror("S3: 3D4 index %02x write %02x\n",index,data); break; diff --git a/src/emu/video/pc_vga.h b/src/emu/video/pc_vga.h index 72f54a5035b..7782f3b5b02 100644 --- a/src/emu/video/pc_vga.h +++ b/src/emu/video/pc_vga.h @@ -556,6 +556,7 @@ public: protected: // device-level overrides virtual void device_start(); + virtual void device_reset(); struct { UINT8 memory_config; @@ -573,6 +574,7 @@ protected: UINT8 id_low; UINT8 revision; UINT8 id_cr30; + UINT32 strapping; // power-on strapping bits UINT8 sr10; // MCLK PLL UINT8 sr11; // MCLK PLL UINT8 sr12; // DCLK PLL