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(MESS) cbm2: Address decoding WIP. (nw)
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@ -39,13 +39,10 @@
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//**************************************************************************
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//-------------------------------------------------
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// bankswitch -
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// read_pla -
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//-------------------------------------------------
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void cbm2_state::bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
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int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *buframcs, int *extbufcs, int *vidramcs,
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int *diskromcs, int *csbank1, int *csbank2, int *csbank3, int *basiccs, int *knbcs, int *kernalcs,
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int *crtccs, int *cs1, int *sidcs, int *extprtcs, int *ciacs, int *aciacs, int *tript1cs, int *tript2cs)
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void cbm2_state::read_pla(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *casseg1, int *casseg2, int *casseg3, int *casseg4)
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{
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UINT32 input = P0 << 15 | P1 << 14 | P2 << 13 | P3 << 12 | busy2 << 11 | eras << 10 | ecas << 9 | refen << 8 | cas << 7 | ras << 6;
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UINT32 data = m_pla1->read(input);
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@ -58,6 +55,42 @@ void cbm2_state::bankswitch(offs_t offset, int busy2, int eras, int ecas, int re
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*casseg4 = BIT(data, 5);
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*casseg3 = BIT(data, 6);
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//*rasseg3 = BIT(data, 7);
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}
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void cbm2hp_state::read_pla(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *casseg1, int *casseg2, int *casseg3, int *casseg4)
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{
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UINT32 input = ras << 13 | cas << 12 | refen << 11 | eras << 10 | ecas << 9 | busy2 << 8 | P3 << 3 | P2 << 2 | P1 << 1 | P0;
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UINT32 data = m_pla1->read(input);
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*casseg1 = BIT(data, 0);
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*casseg2 = BIT(data, 1);
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*casseg3 = BIT(data, 2);
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*casseg4 = BIT(data, 3);
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//*rasseg1 = BIT(data, 4);
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//*rasseg2 = BIT(data, 5);
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//*rasseg3 = BIT(data, 6);
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//*rasseg4 = BIT(data, 7);
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}
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//-------------------------------------------------
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// bankswitch -
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//-------------------------------------------------
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void cbm2_state::bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
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int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *buframcs, int *extbufcs, int *vidramcs,
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int *diskromcs, int *csbank1, int *csbank2, int *csbank3, int *basiccs, int *knbcs, int *kernalcs,
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int *crtccs, int *cs1, int *sidcs, int *extprtcs, int *ciacs, int *aciacs, int *tript1cs, int *tript2cs)
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{
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//this->read_pla(offset, busy2, eras, ecas, refen, cas, ras, casseg1, casseg2, casseg3, casseg4);
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switch (offset >> 16)
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{
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case 1: *casseg1 = 0; break;
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case 2: *casseg2 = 0; break;
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case 3: *casseg3 = 0; break;
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case 4: *casseg4 = 0; break;
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}
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int busen1 = m_dramon;
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int decoden = 0; // TODO
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@ -415,11 +448,6 @@ UINT8 p500_state::read_memory(address_space &space, offs_t offset, offs_t va, in
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*/
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UINT8 data = 0xff;
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if (ae)
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{
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data = m_vic->bus_r();
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}
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if (aec && !datxen && !_64kcasen)
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{
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data = m_ram->pointer()[offset & 0xffff];
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@ -1257,7 +1285,7 @@ WRITE8_MEMBER( cbm2_state::tpi2_pb_w )
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m_tpi2_pb = data;
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}
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READ8_MEMBER( cbm2lp_state::tpi2_pc_r )
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READ8_MEMBER( cbm2_state::tpi2_pc_r )
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{
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/*
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@ -1344,7 +1372,7 @@ static const tpi6525_interface tpi2_intf =
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DEVCB_DRIVER_MEMBER(cbm2_state, tpi2_pa_w),
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DEVCB_NULL,
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DEVCB_DRIVER_MEMBER(cbm2_state, tpi2_pb_w),
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DEVCB_DRIVER_MEMBER(cbm2lp_state, tpi2_pc_r),
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DEVCB_DRIVER_MEMBER(cbm2_state, tpi2_pc_r),
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DEVCB_NULL,
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DEVCB_NULL,
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DEVCB_NULL
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@ -1729,7 +1757,7 @@ MACHINE_CONFIG_END
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// MACHINE_CONFIG( cbm2lp_ntsc )
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//-------------------------------------------------
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static MACHINE_CONFIG_START( cbm2lp_ntsc, cbm2lp_state )
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static MACHINE_CONFIG_START( cbm2lp_ntsc, cbm2_state )
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MCFG_MACHINE_START_OVERRIDE(cbm2_state, cbm2_ntsc)
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MCFG_MACHINE_RESET_OVERRIDE(cbm2_state, cbm2)
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@ -1780,7 +1808,7 @@ MACHINE_CONFIG_END
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// MACHINE_CONFIG( b128 )
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//-------------------------------------------------
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static MACHINE_CONFIG_START( b128, cbm2lp_state )
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static MACHINE_CONFIG_START( b128, cbm2_state )
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MCFG_FRAGMENT_ADD(cbm2lp_ntsc)
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MCFG_FRAGMENT_ADD(128k)
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MACHINE_CONFIG_END
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@ -1790,7 +1818,7 @@ MACHINE_CONFIG_END
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// MACHINE_CONFIG( b256 )
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//-------------------------------------------------
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static MACHINE_CONFIG_START( b256, cbm2lp_state )
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static MACHINE_CONFIG_START( b256, cbm2_state )
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MCFG_FRAGMENT_ADD(cbm2lp_ntsc)
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MCFG_FRAGMENT_ADD(256k)
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MACHINE_CONFIG_END
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@ -1800,7 +1828,7 @@ MACHINE_CONFIG_END
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// MACHINE_CONFIG( cbm2lp_pal )
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//-------------------------------------------------
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static MACHINE_CONFIG_START( cbm2lp_pal, cbm2lp_state )
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static MACHINE_CONFIG_START( cbm2lp_pal, cbm2_state )
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MCFG_FRAGMENT_ADD(cbm2lp_ntsc)
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MCFG_MACHINE_START_OVERRIDE(cbm2_state, cbm2_pal)
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@ -1814,7 +1842,7 @@ MACHINE_CONFIG_END
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// MACHINE_CONFIG( cbm610 )
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//-------------------------------------------------
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static MACHINE_CONFIG_START( cbm610, cbm2lp_state )
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static MACHINE_CONFIG_START( cbm610, cbm2_state )
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MCFG_FRAGMENT_ADD(cbm2lp_pal)
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MCFG_FRAGMENT_ADD(128k)
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MACHINE_CONFIG_END
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@ -1824,7 +1852,7 @@ MACHINE_CONFIG_END
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// MACHINE_CONFIG( cbm620 )
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//-------------------------------------------------
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static MACHINE_CONFIG_START( cbm620, cbm2lp_state )
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static MACHINE_CONFIG_START( cbm620, cbm2_state )
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MCFG_FRAGMENT_ADD(cbm2lp_pal)
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MCFG_FRAGMENT_ADD(256k)
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MACHINE_CONFIG_END
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@ -90,6 +90,8 @@ public:
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DECLARE_MACHINE_START( cbm2_pal );
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DECLARE_MACHINE_RESET( cbm2 );
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virtual void read_pla(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *casseg1, int *casseg2, int *casseg3, int *casseg4);
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void bankswitch(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *sysioen, int *dramen,
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int *casseg1, int *casseg2, int *casseg3, int *casseg4, int *buframcs, int *extbufcs, int *vidramcs,
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int *diskromcs, int *csbank1, int *csbank2, int *csbank3, int *basiccs, int *knbcs, int *kernalcs,
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@ -113,6 +115,7 @@ public:
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DECLARE_WRITE8_MEMBER( tpi2_pa_w );
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DECLARE_WRITE8_MEMBER( tpi2_pb_w );
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DECLARE_READ8_MEMBER( tpi2_pc_r );
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DECLARE_READ8_MEMBER( cia_pa_r );
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DECLARE_WRITE8_MEMBER( cia_pa_w );
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@ -151,6 +154,19 @@ public:
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};
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class cbm2hp_state : public cbm2_state
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{
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public:
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cbm2hp_state(const machine_config &mconfig, device_type type, const char *tag)
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: cbm2_state(mconfig, type, tag)
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{ }
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virtual void read_pla(offs_t offset, int busy2, int eras, int ecas, int refen, int cas, int ras, int *casseg1, int *casseg2, int *casseg3, int *casseg4);
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DECLARE_READ8_MEMBER( tpi2_pc_r );
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};
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class p500_state : public cbm2_state
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{
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public:
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@ -203,27 +219,5 @@ public:
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};
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class cbm2lp_state : public cbm2_state
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{
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public:
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cbm2lp_state(const machine_config &mconfig, device_type type, const char *tag)
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: cbm2_state(mconfig, type, tag)
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{ }
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DECLARE_READ8_MEMBER( tpi2_pc_r );
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};
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class cbm2hp_state : public cbm2_state
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{
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public:
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cbm2hp_state(const machine_config &mconfig, device_type type, const char *tag)
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: cbm2_state(mconfig, type, tag)
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{ }
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DECLARE_READ8_MEMBER( tpi2_pc_r );
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};
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#endif
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