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Hooks up sound CPU comms in Power Instinct 2. This enables synchronized dancing for the background characters.

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Credit Shimapong.
This commit is contained in:
Andrew Gardner 2008-08-21 03:35:05 +00:00
parent 73cbd67b13
commit e6a2212387
1 changed files with 112 additions and 112 deletions
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224
src/mame/drivers/cave.c
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@ -493,24 +493,24 @@ static ADDRESS_MAP_START( dfeveron_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x800000, 0x800007) AM_READ(cave_irq_cause_r ) // IRQ Cause
/**/AM_RANGE(0x900000, 0x900005) AM_READ(SMH_RAM ) // Layer 0 Control
/**/AM_RANGE(0xa00000, 0xa00005) AM_READ(SMH_RAM ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xb00002, 0xb00003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xb00000, 0xb00001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xb00002, 0xb00003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( dfeveron_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x300000, 0x300003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x607fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x708000, 0x708fff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0x710c00, 0x710fff) AM_WRITE(SMH_RAM ) // ?
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x710c00, 0x710fff) AM_WRITE(SMH_RAM ) // ?
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x900000, 0x900005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xc00000, 0xc00001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
AM_RANGE(0xc00000, 0xc00001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
ADDRESS_MAP_END
@ -532,25 +532,25 @@ static ADDRESS_MAP_START( ddonpach_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xa00000, 0xa00005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xb00000, 0xb00005) AM_READ(SMH_RAM ) // Layer 2 Control
/**/AM_RANGE(0xc00000, 0xc0ffff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0xd00000, 0xd00001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xd00002, 0xd00003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xd00000, 0xd00001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xd00002, 0xd00003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( ddonpach_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x300000, 0x300003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x607fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2 )
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x607fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x700000, 0x70ffff) AM_WRITE(cave_vram_2_8x8_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x900000, 0x900005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xc00000, 0xc0ffff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0xe00000, 0xe00001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
AM_RANGE(0xe00000, 0xe00001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
ADDRESS_MAP_END
@ -598,22 +598,22 @@ static ADDRESS_MAP_START( donpachi_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xa08000, 0xa08fff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0xb00000, 0xb00001) AM_READ(okim6295_status_0_lsb_r ) // M6295
AM_RANGE(0xb00010, 0xb00011) AM_READ(okim6295_status_1_lsb_r ) //
AM_RANGE(0xc00000, 0xc00001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xc00002, 0xc00003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xc00000, 0xc00001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xc00002, 0xc00003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( donpachi_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x07ffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x200000, 0x207fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x300000, 0x307fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x200000, 0x207fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x300000, 0x307fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x400000, 0x407fff) AM_WRITE(cave_vram_2_8x8_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x500000, 0x507fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x508000, 0x50ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x508000, 0x50ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2 )
AM_RANGE(0x600000, 0x600005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0x700000, 0x700005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0x800000, 0x800005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0x900000, 0x90007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x900000, 0x90007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0xa08000, 0xa08fff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0xb00000, 0xb00003) AM_WRITE(okim6295_data_0_lsb_w ) // M6295
AM_RANGE(0xb00010, 0xb00013) AM_WRITE(okim6295_data_1_lsb_w ) //
@ -640,20 +640,20 @@ static ADDRESS_MAP_START( esprade_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xa00000, 0xa00005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xb00000, 0xb00005) AM_READ(SMH_RAM ) // Layer 2 Control
/**/AM_RANGE(0xc00000, 0xc0ffff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0xd00000, 0xd00001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xd00002, 0xd00003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xd00000, 0xd00001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xd00002, 0xd00003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( esprade_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x300000, 0x300003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2) // Sprites?
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x607fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x700000, 0x707fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x900000, 0x900005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
@ -683,9 +683,9 @@ static ADDRESS_MAP_START( gaia_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xa00000, 0xa00005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xb00000, 0xb00005) AM_READ(SMH_RAM ) // Layer 2 Control
AM_RANGE(0xc00000, 0xc0ffff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0xd00010, 0xd00011) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xd00012, 0xd00013) AM_READ_PORT("IN1") // Inputs
AM_RANGE(0xd00014, 0xd00015) AM_READ_PORT("DSW") // Dips
AM_RANGE(0xd00010, 0xd00011) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xd00012, 0xd00013) AM_READ_PORT("IN1" ) // Inputs
AM_RANGE(0xd00014, 0xd00015) AM_READ_PORT("DSW" ) // Dips
ADDRESS_MAP_END
static ADDRESS_MAP_START( gaia_writemem, ADDRESS_SPACE_PROGRAM, 16 )
@ -693,14 +693,14 @@ static ADDRESS_MAP_START( gaia_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x300000, 0x300003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprite bank 1
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2) // Sprite bank 2
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2 ) // Sprite bank 2
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x508000, 0x50ffff) AM_WRITE(SMH_RAM ) // More Layer 0, Tested but not used?
AM_RANGE(0x508000, 0x50ffff) AM_WRITE(SMH_RAM ) // More Layer 0, Tested but not used?
AM_RANGE(0x600000, 0x607fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x608000, 0x60ffff) AM_WRITE(SMH_RAM ) // More Layer 1, Tested but not used?
AM_RANGE(0x608000, 0x60ffff) AM_WRITE(SMH_RAM ) // More Layer 1, Tested but not used?
AM_RANGE(0x700000, 0x707fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x708000, 0x70ffff) AM_WRITE(SMH_RAM ) // More Layer 2, Tested but not used?
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x708000, 0x70ffff) AM_WRITE(SMH_RAM ) // More Layer 2, Tested but not used?
AM_RANGE(0x800000, 0x80007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x900000, 0x900005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
@ -728,27 +728,27 @@ static ADDRESS_MAP_START( guwange_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xa00000, 0xa00005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xb00000, 0xb00005) AM_READ(SMH_RAM ) // Layer 2 Control
/**/AM_RANGE(0xc00000, 0xc0ffff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0xd00010, 0xd00011) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xd00012, 0xd00013) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xd00010, 0xd00011) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xd00012, 0xd00013) AM_READ_PORT("IN1" ) // Inputs + EEPROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( guwange_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x200000, 0x20ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x300000, 0x30007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x300000, 0x30007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2 )
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x607fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x700000, 0x707fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x800000, 0x800003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x800000, 0x800003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x900000, 0x900005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xc00000, 0xc0ffff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0xd00010, 0xd00011) AM_WRITE(cave_eeprom_lsb_w ) // EEPROM
// AM_RANGE(0xd00012, 0xd00013) AM_WRITE(SMH_NOP ) // ?
// AM_RANGE(0xd00014, 0xd00015) AM_WRITE(SMH_NOP ) // ? $800068 in dfeveron ? probably Watchdog
// AM_RANGE(0xd00012, 0xd00013) AM_WRITE(SMH_NOP ) // ?
// AM_RANGE(0xd00014, 0xd00015) AM_WRITE(SMH_NOP ) // ? $800068 in dfeveron ? probably Watchdog
ADDRESS_MAP_END
@ -768,8 +768,8 @@ static ADDRESS_MAP_START( hotdogst_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xb00000, 0xb00005) AM_READ(SMH_RAM ) // Layer 0 Control
/**/AM_RANGE(0xb80000, 0xb80005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xc00000, 0xc00005) AM_READ(SMH_RAM ) // Layer 2 Control
AM_RANGE(0xc80000, 0xc80001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xc80002, 0xc80003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xc80000, 0xc80001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xc80002, 0xc80003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
/**/AM_RANGE(0xf00000, 0xf07fff) AM_READ(SMH_RAM ) // Sprites
/**/AM_RANGE(0xf08000, 0xf0ffff) AM_READ(SMH_RAM ) // Sprites?
ADDRESS_MAP_END
@ -781,14 +781,14 @@ static ADDRESS_MAP_START( hotdogst_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x880000, 0x887fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x900000, 0x907fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x980000, 0x987fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0xa8006e, 0xa8006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xa80000, 0xa8007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0xa8006e, 0xa8006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xa80000, 0xa8007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xb80000, 0xb80005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xc00000, 0xc00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xd00000, 0xd00001) AM_WRITE(hotdogst_eeprom_msb_w ) // EEPROM
AM_RANGE(0xd00002, 0xd00003) AM_WRITE(SMH_NOP ) // ???
AM_RANGE(0xf00000, 0xf07fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0xd00000, 0xd00001) AM_WRITE(hotdogst_eeprom_msb_w ) // EEPROM
AM_RANGE(0xd00002, 0xd00003) AM_WRITE(SMH_NOP ) // ???
AM_RANGE(0xf00000, 0xf07fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0xf08000, 0xf0ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
ADDRESS_MAP_END
@ -868,14 +868,14 @@ static ADDRESS_MAP_START( korokoro_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x1c0000, 0x1c0007) AM_READ( cave_irq_cause_r ) // IRQ Cause
// AM_RANGE(0x200000, 0x207fff) AM_READ( SMH_RAM ) // Palette
// AM_RANGE(0x240000, 0x240003) AM_READ( cave_sound_r ) // YMZ280
AM_RANGE(0x280000, 0x280001) AM_READ_PORT("IN0") // Inputs + ???
AM_RANGE(0x280002, 0x280003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0x280000, 0x280001) AM_READ_PORT("IN0" ) // Inputs + ???
AM_RANGE(0x280002, 0x280003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
AM_RANGE(0x300000, 0x30ffff) AM_READ( SMH_RAM ) // RAM
ADDRESS_MAP_END
static ADDRESS_MAP_START( korokoro_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x07ffff) AM_WRITE( SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x107fff) AM_WRITE( cave_vram_0_w ) AM_BASE( &cave_vram_0 ) // Layer 0
AM_RANGE(0x100000, 0x107fff) AM_WRITE( cave_vram_0_w ) AM_BASE( &cave_vram_0 ) // Layer 0
AM_RANGE(0x140000, 0x140005) AM_WRITE( SMH_RAM ) AM_BASE( &cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0x180000, 0x187fff) AM_WRITE( SMH_RAM ) AM_BASE( &spriteram16 ) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x1c0000, 0x1c007f) AM_WRITE( SMH_RAM ) AM_BASE( &cave_videoregs ) // Video Regs
@ -883,8 +883,8 @@ static ADDRESS_MAP_START( korokoro_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x240000, 0x240003) AM_WRITE( cave_sound_w ) // YMZ280
AM_RANGE(0x280008, 0x280009) AM_WRITE( korokoro_leds_w )
AM_RANGE(0x28000a, 0x28000b) AM_WRITE( korokoro_eeprom_msb_w ) // EEPROM
AM_RANGE(0x28000c, 0x28000d) AM_WRITE( SMH_NOP ) // 0 (watchdog?)
AM_RANGE(0x300000, 0x30ffff) AM_WRITE( SMH_RAM ) // RAM
AM_RANGE(0x28000c, 0x28000d) AM_WRITE( SMH_NOP ) // 0 (watchdog?)
AM_RANGE(0x300000, 0x30ffff) AM_WRITE( SMH_RAM ) // RAM
ADDRESS_MAP_END
@ -903,8 +903,8 @@ static ADDRESS_MAP_START( mazinger_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0x504000, 0x507fff) AM_READ(SMH_RAM ) // Layer 0
/**/AM_RANGE(0x600000, 0x600005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0x700000, 0x700005) AM_READ(SMH_RAM ) // Layer 0 Control
AM_RANGE(0x800000, 0x800001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0x800002, 0x800003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0x800000, 0x800001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0x800002, 0x800003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
/**/AM_RANGE(0xc08000, 0xc0ffff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0xd00000, 0xd7ffff) AM_READ(SMH_BANK1 ) // ROM
ADDRESS_MAP_END
@ -912,11 +912,11 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mazinger_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x07ffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x200000, 0x207fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x200000, 0x207fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x208000, 0x20ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x300068, 0x300069) AM_WRITE(watchdog_reset16_w ) // Watchdog
AM_RANGE(0x30006e, 0x30006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0x300000, 0x30007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x300000, 0x30007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x400000, 0x407fff) AM_WRITE(cave_vram_1_8x8_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_8x8_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x600005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
@ -949,8 +949,8 @@ static ADDRESS_MAP_START( metmqstr_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xb00000, 0xb00005) AM_READ(SMH_RAM ) // Layer 0 Control
/**/AM_RANGE(0xb80000, 0xb80005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xc00000, 0xc00005) AM_READ(SMH_RAM ) // Layer 2 Control
AM_RANGE(0xc80000, 0xc80001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0xc80002, 0xc80003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0xc80000, 0xc80001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0xc80002, 0xc80003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
AM_RANGE(0xf00000, 0xf07fff) AM_READ(SMH_RAM ) // Sprites
AM_RANGE(0xf08000, 0xf0ffff) AM_READ(SMH_RAM ) // RAM
ADDRESS_MAP_END
@ -961,20 +961,20 @@ static ADDRESS_MAP_START( metmqstr_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x200000, 0x27ffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x408000, 0x408fff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0x880000, 0x887fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x888000, 0x88ffff) AM_WRITE(SMH_RAM ) //
AM_RANGE(0x888000, 0x88ffff) AM_WRITE(SMH_RAM ) //
AM_RANGE(0x900000, 0x907fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x908000, 0x90ffff) AM_WRITE(SMH_RAM ) //
AM_RANGE(0x908000, 0x90ffff) AM_WRITE(SMH_RAM ) //
AM_RANGE(0x980000, 0x987fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x988000, 0x98ffff) AM_WRITE(SMH_RAM ) //
AM_RANGE(0xa80068, 0xa80069) AM_WRITE(watchdog_reset16_w ) // Watchdog?
AM_RANGE(0xa8006c, 0xa8006d) AM_WRITE(SMH_NOP ) // ?
AM_RANGE(0xa8006e, 0xa8006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xa80000, 0xa8007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x988000, 0x98ffff) AM_WRITE(SMH_RAM ) //
AM_RANGE(0xa80068, 0xa80069) AM_WRITE(watchdog_reset16_w ) // Watchdog?
AM_RANGE(0xa8006c, 0xa8006d) AM_WRITE(SMH_NOP ) // ?
AM_RANGE(0xa8006e, 0xa8006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xa80000, 0xa8007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xb80000, 0xb80005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xc00000, 0xc00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xd00000, 0xd00001) AM_WRITE(metmqstr_eeprom_msb_w ) // EEPROM
AM_RANGE(0xf00000, 0xf07fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0xd00000, 0xd00001) AM_WRITE(metmqstr_eeprom_msb_w ) // EEPROM
AM_RANGE(0xf00000, 0xf07fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0xf08000, 0xf0ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
ADDRESS_MAP_END
@ -1011,8 +1011,8 @@ static WRITE16_HANDLER( pwrinst2_vctrl_3_w ) { vctrl_w(cave_vctrl_3, offset, dat
static ADDRESS_MAP_START( pwrinst2_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x1fffff) AM_READ(SMH_ROM ) // ROM
AM_RANGE(0x400000, 0x40ffff) AM_READ(SMH_RAM ) // RAM
AM_RANGE(0x500000, 0x500001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0x500002, 0x500003) AM_READ_PORT("IN1") //
AM_RANGE(0x500000, 0x500001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0x500002, 0x500003) AM_READ_PORT("IN1" ) //
AM_RANGE(0x600000, 0x6fffff) AM_READ(SMH_ROM) AM_REGION("user1", 0) // extra data ROM space
AM_RANGE(0x800000, 0x807fff) AM_READ(SMH_RAM ) // Layer 2
AM_RANGE(0x880000, 0x887fff) AM_READ(SMH_RAM ) // Layer 0
@ -1026,28 +1026,28 @@ static ADDRESS_MAP_START( pwrinst2_readmem, ADDRESS_SPACE_PROGRAM, 16 )
/**/AM_RANGE(0xc00000, 0xc00005) AM_READ(SMH_RAM ) // Layer 1 Control
/**/AM_RANGE(0xc80000, 0xc80005) AM_READ(SMH_RAM ) // Layer 3 Control
AM_RANGE(0xa80000, 0xa8007f) AM_READ(donpachi_videoregs_r ) // Video Regs
AM_RANGE(0xd80000, 0xd80001) AM_READ(SMH_NOP ) // ? From Sound CPU
AM_RANGE(0xd80000, 0xd80001) AM_READ(soundlatch_ack_r ) // ? From Sound CPU
AM_RANGE(0xe80000, 0xe80001) AM_READ(pwrinst2_eeprom_r ) // EEPROM
AM_RANGE(0xf00000, 0xf04fff) AM_READ(SMH_RAM ) // Palette
ADDRESS_MAP_END
static ADDRESS_MAP_START( pwrinst2_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x1fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x400000, 0x40ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x700000, 0x700001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
AM_RANGE(0x000000, 0x1fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x400000, 0x40ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x700000, 0x700001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
AM_RANGE(0x800000, 0x807fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x880000, 0x887fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x900000, 0x907fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x980000, 0x987fff) AM_WRITE(cave_vram_3_8x8_w) AM_BASE(&cave_vram_3 ) // Layer 3
AM_RANGE(0x980000, 0x987fff) AM_WRITE(cave_vram_3_8x8_w) AM_BASE(&cave_vram_3) // Layer 3
AM_RANGE(0xa00000, 0xa07fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0xa08000, 0xa0ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0xa10000, 0xa1ffff) AM_WRITE(SMH_RAM ) // Sprites?
AM_RANGE(0xa10000, 0xa1ffff) AM_WRITE(SMH_RAM ) // Sprites?
AM_RANGE(0xa80000, 0xa8007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(pwrinst2_vctrl_2_w) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xb80000, 0xb80005) AM_WRITE(pwrinst2_vctrl_0_w) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xc00000, 0xc00005) AM_WRITE(pwrinst2_vctrl_1_w) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xc80000, 0xc80005) AM_WRITE(pwrinst2_vctrl_3_w) AM_BASE(&cave_vctrl_3 ) // Layer 3 Control
AM_RANGE(0xe00000, 0xe00001) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xe00000, 0xe00001) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xf00000, 0xf04fff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
ADDRESS_MAP_END
@ -1089,7 +1089,7 @@ static ADDRESS_MAP_START( sailormn_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x508000, 0x50ffff) AM_READ(SMH_RAM ) // Sprites?
AM_RANGE(0x510000, 0x510001) AM_READ(SMH_RAM ) // (agallet)
AM_RANGE(0x600000, 0x600001) AM_READ(sailormn_input0_r ) // Inputs + Watchdog!
AM_RANGE(0x600002, 0x600003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0x600002, 0x600003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
AM_RANGE(0x800000, 0x887fff) AM_READ(SMH_RAM ) // Layer 0
AM_RANGE(0x880000, 0x887fff) AM_READ(SMH_RAM ) // Layer 1
AM_RANGE(0x900000, 0x907fff) AM_READ(SMH_RAM ) // Layer 2
@ -1103,26 +1103,26 @@ static ADDRESS_MAP_START( sailormn_readmem, ADDRESS_SPACE_PROGRAM, 16 )
ADDRESS_MAP_END
static ADDRESS_MAP_START( sailormn_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x07ffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x110000, 0x110001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x200000, 0x3fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x000000, 0x07ffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x110000, 0x110001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x200000, 0x3fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x408000, 0x40bfff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0x40c000, 0x40ffff) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x410000, 0x410001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x500000, 0x507fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x40c000, 0x40ffff) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x410000, 0x410001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x500000, 0x507fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x508000, 0x50ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x510000, 0x510001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x700000, 0x700001) AM_WRITE(sailormn_eeprom_msb_w ) // EEPROM
AM_RANGE(0x800000, 0x807fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x880000, 0x887fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x900000, 0x907fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x908000, 0x908001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa80000, 0xa80005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xb8006e, 0xb8006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0x510000, 0x510001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0x700000, 0x700001) AM_WRITE(sailormn_eeprom_msb_w ) // EEPROM
AM_RANGE(0x800000, 0x807fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x880000, 0x887fff) AM_WRITE(cave_vram_1_w) AM_BASE(&cave_vram_1 ) // Layer 1
AM_RANGE(0x900000, 0x907fff) AM_WRITE(cave_vram_2_w) AM_BASE(&cave_vram_2 ) // Layer 2
AM_RANGE(0x908000, 0x908001) AM_WRITE(SMH_RAM ) // (agallet)
AM_RANGE(0xa00000, 0xa00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0xa80000, 0xa80005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_1 ) // Layer 1 Control
AM_RANGE(0xb00000, 0xb00005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_2 ) // Layer 2 Control
AM_RANGE(0xb8006e, 0xb8006f) AM_WRITE(sound_cmd_w ) // To Sound CPU
AM_RANGE(0xb80000, 0xb8007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
ADDRESS_MAP_END
@ -1141,18 +1141,18 @@ static ADDRESS_MAP_START( uopoko_readmem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x600000, 0x600007) AM_READ(cave_irq_cause_r ) // IRQ Cause
/**/AM_RANGE(0x700000, 0x700005) AM_READ(SMH_RAM ) // Layer 0 Control
/**/AM_RANGE(0x800000, 0x80ffff) AM_READ(SMH_RAM ) // Palette
AM_RANGE(0x900000, 0x900001) AM_READ_PORT("IN0") // Inputs
AM_RANGE(0x900002, 0x900003) AM_READ_PORT("IN1") // Inputs + EEPROM
AM_RANGE(0x900000, 0x900001) AM_READ_PORT("IN0" ) // Inputs
AM_RANGE(0x900002, 0x900003) AM_READ_PORT("IN1" ) // Inputs + EEPROM
ADDRESS_MAP_END
static ADDRESS_MAP_START( uopoko_writemem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x000000, 0x0fffff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x100000, 0x10ffff) AM_WRITE(SMH_RAM ) // RAM
AM_RANGE(0x300000, 0x300003) AM_WRITE(cave_sound_w ) // YMZ280
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size ) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2)
AM_RANGE(0x400000, 0x407fff) AM_WRITE(SMH_RAM) AM_BASE(&spriteram16) AM_SIZE(&spriteram_size) // Sprites
AM_RANGE(0x408000, 0x40ffff) AM_WRITE(SMH_RAM) AM_BASE(&cave_spriteram16_2 )
AM_RANGE(0x500000, 0x507fff) AM_WRITE(cave_vram_0_w) AM_BASE(&cave_vram_0 ) // Layer 0
AM_RANGE(0x600000, 0x60007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x600000, 0x60007f) AM_WRITE(SMH_RAM) AM_BASE(&cave_videoregs ) // Video Regs
AM_RANGE(0x700000, 0x700005) AM_WRITE(SMH_RAM) AM_BASE(&cave_vctrl_0 ) // Layer 0 Control
AM_RANGE(0x800000, 0x80ffff) AM_WRITE(SMH_RAM) AM_BASE(&paletteram16) AM_SIZE(&cave_paletteram_size) // Palette
AM_RANGE(0xa00000, 0xa00001) AM_WRITE(cave_eeprom_msb_w ) // EEPROM
@ -1206,7 +1206,7 @@ static ADDRESS_MAP_START( hotdogst_sound_readport, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x30, 0x30) AM_READ(soundlatch_lo_r ) // From Main CPU
AM_RANGE(0x40, 0x40) AM_READ(soundlatch_hi_r ) //
AM_RANGE(0x50, 0x50) AM_READ(ym2203_status_port_0_r ) // YM2203
AM_RANGE(0x50, 0x50) AM_READ(ym2203_status_port_0_r ) // YM2203
AM_RANGE(0x51, 0x51) AM_READ(ym2203_read_port_0_r ) //
AM_RANGE(0x60, 0x60) AM_READ(okim6295_status_0_r ) // M6295
ADDRESS_MAP_END
@ -1251,7 +1251,7 @@ ADDRESS_MAP_END
static ADDRESS_MAP_START( mazinger_sound_readport, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x30, 0x30) AM_READ(soundlatch_lo_r ) // From Main CPU
AM_RANGE(0x52, 0x52) AM_READ(ym2203_status_port_0_r ) // YM2203
AM_RANGE(0x52, 0x52) AM_READ(ym2203_status_port_0_r ) // YM2203
ADDRESS_MAP_END
static ADDRESS_MAP_START( mazinger_sound_writeport, ADDRESS_SPACE_IO, 8 )
@ -1313,7 +1313,7 @@ static ADDRESS_MAP_START( metmqstr_sound_readport, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x20, 0x20) AM_READ(soundflags_r ) // Communication
AM_RANGE(0x30, 0x30) AM_READ(soundlatch_lo_r ) // From Main CPU
AM_RANGE(0x40, 0x40) AM_READ(soundlatch_hi_r ) //
AM_RANGE(0x51, 0x51) AM_READ(ym2151_status_port_0_r ) // YM2151
AM_RANGE(0x51, 0x51) AM_READ(ym2151_status_port_0_r ) // YM2151
ADDRESS_MAP_END
static ADDRESS_MAP_START( metmqstr_sound_writeport, ADDRESS_SPACE_IO, 8 )
@ -1357,7 +1357,7 @@ static ADDRESS_MAP_START( pwrinst2_sound_readport, ADDRESS_SPACE_IO, 8 )
ADDRESS_MAP_GLOBAL_MASK(0xff)
AM_RANGE(0x00, 0x00) AM_READ(okim6295_status_0_r ) // M6295
AM_RANGE(0x08, 0x08) AM_READ(okim6295_status_1_r ) //
AM_RANGE(0x40, 0x40) AM_READ(ym2203_status_port_0_r ) // YM2203
AM_RANGE(0x40, 0x40) AM_READ(ym2203_status_port_0_r ) // YM2203
AM_RANGE(0x41, 0x41) AM_READ(ym2203_read_port_0_r ) //
AM_RANGE(0x60, 0x60) AM_READ(soundlatch_hi_r ) // From Main CPU
AM_RANGE(0x70, 0x70) AM_READ(soundlatch_lo_r ) //
@ -1370,8 +1370,8 @@ static ADDRESS_MAP_START( pwrinst2_sound_writeport, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x10, 0x17) AM_WRITE(NMK112_okibank_w ) // Samples bank
AM_RANGE(0x40, 0x40) AM_WRITE(ym2203_control_port_0_w ) // YM2203
AM_RANGE(0x41, 0x41) AM_WRITE(ym2203_write_port_0_w ) //
// AM_RANGE(0x50, 0x50) AM_WRITE(SMH_NOP ) // ?? volume
// AM_RANGE(0x51, 0x51) AM_WRITE(SMH_NOP ) // ?? volume
AM_RANGE(0x50, 0x50) AM_WRITE(soundlatch_ack_w ) // To Main CPU
// AM_RANGE(0x51, 0x51) AM_WRITE(SMH_NOP ) // ?? volume
AM_RANGE(0x80, 0x80) AM_WRITE(pwrinst2_rombank_w ) // ROM bank
ADDRESS_MAP_END
@ -1418,16 +1418,16 @@ static WRITE8_HANDLER( sailormn_okibank1_w )
}
static ADDRESS_MAP_START( sailormn_sound_readmem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x3fff) AM_READ(SMH_ROM ) // ROM
AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1 ) // ROM (Banked)
AM_RANGE(0xc000, 0xdfff) AM_READ(mirror_ram_r ) // RAM
AM_RANGE(0xe000, 0xffff) AM_READ(mirror_ram_r ) // Mirrored RAM (agallet)
AM_RANGE(0x0000, 0x3fff) AM_READ(SMH_ROM ) // ROM
AM_RANGE(0x4000, 0x7fff) AM_READ(SMH_BANK1 ) // ROM (Banked)
AM_RANGE(0xc000, 0xdfff) AM_READ(mirror_ram_r ) // RAM
AM_RANGE(0xe000, 0xffff) AM_READ(mirror_ram_r ) // Mirrored RAM (agallet)
ADDRESS_MAP_END
static ADDRESS_MAP_START( sailormn_sound_writemem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x0000, 0x3fff) AM_WRITE(SMH_ROM ) // ROM
AM_RANGE(0x4000, 0x7fff) AM_WRITE(SMH_ROM ) // ROM (Banked)
AM_RANGE(0xc000, 0xdfff) AM_WRITE(mirror_ram_w) AM_BASE(&mirror_ram ) // RAM
AM_RANGE(0xc000, 0xdfff) AM_WRITE(mirror_ram_w) AM_BASE(&mirror_ram) // RAM
AM_RANGE(0xe000, 0xffff) AM_WRITE(mirror_ram_w ) // Mirrored RAM (agallet)
ADDRESS_MAP_END
@ -1436,7 +1436,7 @@ static ADDRESS_MAP_START( sailormn_sound_readport, ADDRESS_SPACE_IO, 8 )
AM_RANGE(0x20, 0x20) AM_READ(soundflags_r ) // Communication
AM_RANGE(0x30, 0x30) AM_READ(soundlatch_lo_r ) // From Main CPU
AM_RANGE(0x40, 0x40) AM_READ(soundlatch_hi_r ) //
AM_RANGE(0x51, 0x51) AM_READ(ym2151_status_port_0_r ) // YM2151
AM_RANGE(0x51, 0x51) AM_READ(ym2151_status_port_0_r ) // YM2151
AM_RANGE(0x60, 0x60) AM_READ(okim6295_status_0_r ) // M6295 #0
AM_RANGE(0x80, 0x80) AM_READ(okim6295_status_1_r ) // M6295 #1
ADDRESS_MAP_END