mirror of
https://github.com/holub/mame
synced 2025-04-21 07:52:35 +03:00
Made both DRC and Non-DRC compile for MIPS, RSP and SH2 core and added option to enable/disable DRC from command line (-drc -nodrc by default it's on) [Miodrag Milanovic]
This commit is contained in:
Miodrag Milanovic
parent
2d650cda4e
commit
e72ada1fbd
@ -17,8 +17,6 @@
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#define ENABLE_OVERFLOWS 0
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#ifndef MIPS3_USE_DRC
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/***************************************************************************
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HELPER MACROS
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***************************************************************************/
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@ -159,22 +157,6 @@ static mips3_regs mips3;
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#define ROPCODE(pc) mips3.core.direct->read_decrypted_dword(pc)
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/***************************************************************************
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DRC COMPATIBILITY
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***************************************************************************/
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void mips3drc_set_options(device_t *device, UINT32 options)
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{
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}
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void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base)
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{
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}
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void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles)
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{
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}
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/***************************************************************************
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EXECEPTION HANDLING
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***************************************************************************/
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@ -2343,7 +2325,7 @@ static CPU_INIT( vr4300le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( vr4300be )
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CPU_GET_INFO( vr4300be_int )
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{
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switch (state)
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{
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@ -2362,7 +2344,7 @@ CPU_GET_INFO( vr4300be )
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}
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}
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CPU_GET_INFO( vr4300le )
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CPU_GET_INFO( vr4300le_int )
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{
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switch (state)
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{
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@ -2382,7 +2364,7 @@ CPU_GET_INFO( vr4300le )
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}
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// VR4310 = VR4300 with different speed bin
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CPU_GET_INFO( vr4310be )
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CPU_GET_INFO( vr4310be_int )
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{
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switch (state)
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{
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@ -2401,7 +2383,7 @@ CPU_GET_INFO( vr4310be )
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}
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}
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CPU_GET_INFO( vr4310le )
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CPU_GET_INFO( vr4310le_int )
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{
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switch (state)
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{
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@ -2437,7 +2419,7 @@ static CPU_INIT( r4600le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( r4600be )
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CPU_GET_INFO( r4600be_int )
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{
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switch (state)
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{
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@ -2456,7 +2438,7 @@ CPU_GET_INFO( r4600be )
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}
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}
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CPU_GET_INFO( r4600le )
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CPU_GET_INFO( r4600le_int )
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{
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switch (state)
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{
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@ -2493,7 +2475,7 @@ static CPU_INIT( r4650le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( r4650be )
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CPU_GET_INFO( r4650be_int )
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{
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switch (state)
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{
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@ -2512,7 +2494,7 @@ CPU_GET_INFO( r4650be )
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}
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}
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CPU_GET_INFO( r4650le )
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CPU_GET_INFO( r4650le_int )
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{
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switch (state)
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{
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@ -2549,7 +2531,7 @@ static CPU_INIT( r4700le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( r4700be )
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CPU_GET_INFO( r4700be_int )
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{
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switch (state)
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{
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@ -2569,7 +2551,7 @@ CPU_GET_INFO( r4700be )
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}
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CPU_GET_INFO( r4700le )
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CPU_GET_INFO( r4700le_int )
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{
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switch (state)
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{
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@ -2606,7 +2588,7 @@ static CPU_INIT( r5000le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( r5000be )
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CPU_GET_INFO( r5000be_int )
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{
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switch (state)
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{
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@ -2625,7 +2607,7 @@ CPU_GET_INFO( r5000be )
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}
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}
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CPU_GET_INFO( r5000le )
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CPU_GET_INFO( r5000le_int )
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{
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switch (state)
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{
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@ -2662,7 +2644,7 @@ static CPU_INIT( qed5271le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( qed5271be )
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CPU_GET_INFO( qed5271be_int )
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{
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switch (state)
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{
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@ -2681,7 +2663,7 @@ CPU_GET_INFO( qed5271be )
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}
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}
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CPU_GET_INFO( qed5271le )
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CPU_GET_INFO( qed5271le_int )
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{
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switch (state)
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{
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@ -2718,7 +2700,7 @@ static CPU_INIT( rm7000le )
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mips3.tlb_table = vtlb_table(mips3.core.vtlb);
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}
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CPU_GET_INFO( rm7000be )
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CPU_GET_INFO( rm7000be_int )
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{
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switch (state)
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{
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@ -2737,7 +2719,7 @@ CPU_GET_INFO( rm7000be )
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}
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}
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CPU_GET_INFO( rm7000le )
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CPU_GET_INFO( rm7000le_int )
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{
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switch (state)
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{
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@ -2756,27 +2738,42 @@ CPU_GET_INFO( rm7000le )
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}
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}
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DEFINE_LEGACY_CPU_DEVICE(VR4300BE, vr4300be);
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DEFINE_LEGACY_CPU_DEVICE(VR4300LE, vr4300le);
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DEFINE_LEGACY_CPU_DEVICE(VR4310BE, vr4310be);
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DEFINE_LEGACY_CPU_DEVICE(VR4310LE, vr4310le);
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DEFINE_LEGACY_CPU_DEVICE(VR4300BE_INT, vr4300be_int);
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DEFINE_LEGACY_CPU_DEVICE(VR4300LE_INT, vr4300le_int);
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DEFINE_LEGACY_CPU_DEVICE(VR4310BE_INT, vr4310be_int);
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DEFINE_LEGACY_CPU_DEVICE(VR4310LE_INT, vr4310le_int);
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DEFINE_LEGACY_CPU_DEVICE(R4600BE, r4600be);
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DEFINE_LEGACY_CPU_DEVICE(R4600LE, r4600le);
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DEFINE_LEGACY_CPU_DEVICE(R4600BE_INT, r4600be_int);
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DEFINE_LEGACY_CPU_DEVICE(R4600LE_INT, r4600le_int);
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DEFINE_LEGACY_CPU_DEVICE(R4650BE, r4650be);
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DEFINE_LEGACY_CPU_DEVICE(R4650LE, r4650le);
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DEFINE_LEGACY_CPU_DEVICE(R4650BE_INT, r4650be_int);
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DEFINE_LEGACY_CPU_DEVICE(R4650LE_INT, r4650le_int);
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DEFINE_LEGACY_CPU_DEVICE(R4700BE, r4700be);
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DEFINE_LEGACY_CPU_DEVICE(R4700LE, r4700le);
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DEFINE_LEGACY_CPU_DEVICE(R4700BE_INT, r4700be_int);
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DEFINE_LEGACY_CPU_DEVICE(R4700LE_INT, r4700le_int);
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DEFINE_LEGACY_CPU_DEVICE(R5000BE, r5000be);
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DEFINE_LEGACY_CPU_DEVICE(R5000LE, r5000le);
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DEFINE_LEGACY_CPU_DEVICE(R5000BE_INT, r5000be_int);
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DEFINE_LEGACY_CPU_DEVICE(R5000LE_INT, r5000le_int);
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DEFINE_LEGACY_CPU_DEVICE(QED5271BE, qed5271be);
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DEFINE_LEGACY_CPU_DEVICE(QED5271LE, qed5271le);
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DEFINE_LEGACY_CPU_DEVICE(QED5271BE_INT, qed5271be_int);
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DEFINE_LEGACY_CPU_DEVICE(QED5271LE_INT, qed5271le_int);
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DEFINE_LEGACY_CPU_DEVICE(RM7000BE, rm7000be);
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DEFINE_LEGACY_CPU_DEVICE(RM7000LE, rm7000le);
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DEFINE_LEGACY_CPU_DEVICE(RM7000BE_INT, rm7000be_int);
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DEFINE_LEGACY_CPU_DEVICE(RM7000LE_INT, rm7000le_int);
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#endif
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const device_type VR4300BE = &legacy_device_creator_drc<vr4300be_int_device, vr4300be_drc_device>;
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const device_type VR4300LE = &legacy_device_creator_drc<vr4300le_int_device, vr4300le_drc_device>;
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const device_type VR4310BE = &legacy_device_creator_drc<vr4310be_int_device, vr4310be_drc_device>;
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const device_type VR4310LE = &legacy_device_creator_drc<vr4310le_int_device, vr4310le_drc_device>;
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const device_type R4600BE = &legacy_device_creator_drc<r4600be_int_device, r4600be_drc_device>;
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const device_type R4600LE = &legacy_device_creator_drc<r4600le_int_device, r4600le_drc_device>;
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const device_type R4650BE = &legacy_device_creator_drc<r4650be_int_device, r4650be_drc_device>;
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const device_type R4650LE = &legacy_device_creator_drc<r4650le_int_device, r4650le_drc_device>;
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const device_type R4700BE = &legacy_device_creator_drc<r4700be_int_device, r4700be_drc_device>;
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const device_type R4700LE = &legacy_device_creator_drc<r4700le_int_device, r4700le_drc_device>;
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const device_type R5000BE = &legacy_device_creator_drc<r5000be_int_device, r5000be_drc_device>;
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const device_type R5000LE = &legacy_device_creator_drc<r5000le_int_device, r5000le_drc_device>;
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const device_type QED5271BE = &legacy_device_creator_drc<qed5271be_int_device, qed5271be_drc_device>;
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const device_type QED5271LE = &legacy_device_creator_drc<qed5271le_int_device, qed5271le_drc_device>;
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const device_type RM7000BE = &legacy_device_creator_drc<rm7000be_int_device, rm7000be_drc_device>;
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const device_type RM7000LE = &legacy_device_creator_drc<rm7000le_int_device, rm7000le_drc_device>;
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@ -227,29 +227,68 @@ void mips3drc_set_options(device_t *device, UINT32 options);
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void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base);
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void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles);
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DECLARE_LEGACY_CPU_DEVICE(VR4300BE, vr4300be);
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DECLARE_LEGACY_CPU_DEVICE(VR4300LE, vr4300le);
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DECLARE_LEGACY_CPU_DEVICE(VR4310BE, vr4310be);
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DECLARE_LEGACY_CPU_DEVICE(VR4310LE, vr4310le);
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DECLARE_LEGACY_CPU_DEVICE(VR4300BE_INT, vr4300be_int);
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DECLARE_LEGACY_CPU_DEVICE(VR4300LE_INT, vr4300le_int);
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DECLARE_LEGACY_CPU_DEVICE(VR4310BE_INT, vr4310be_int);
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DECLARE_LEGACY_CPU_DEVICE(VR4310LE_INT, vr4310le_int);
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DECLARE_LEGACY_CPU_DEVICE(R4600BE, r4600be);
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DECLARE_LEGACY_CPU_DEVICE(R4600LE, r4600le);
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DECLARE_LEGACY_CPU_DEVICE(R4600BE_INT, r4600be_int);
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DECLARE_LEGACY_CPU_DEVICE(R4600LE_INT, r4600le_int);
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DECLARE_LEGACY_CPU_DEVICE(R4650BE, r4650be);
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DECLARE_LEGACY_CPU_DEVICE(R4650LE, r4650le);
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DECLARE_LEGACY_CPU_DEVICE(R4650BE_INT, r4650be_int);
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DECLARE_LEGACY_CPU_DEVICE(R4650LE_INT, r4650le_int);
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DECLARE_LEGACY_CPU_DEVICE(R4700BE, r4700be);
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DECLARE_LEGACY_CPU_DEVICE(R4700LE, r4700le);
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DECLARE_LEGACY_CPU_DEVICE(R4700BE_INT, r4700be_int);
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DECLARE_LEGACY_CPU_DEVICE(R4700LE_INT, r4700le_int);
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DECLARE_LEGACY_CPU_DEVICE(R5000BE, r5000be);
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DECLARE_LEGACY_CPU_DEVICE(R5000LE, r5000le);
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DECLARE_LEGACY_CPU_DEVICE(R5000BE_INT, r5000be_int);
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DECLARE_LEGACY_CPU_DEVICE(R5000LE_INT, r5000le_int);
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DECLARE_LEGACY_CPU_DEVICE(QED5271BE, qed5271be);
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DECLARE_LEGACY_CPU_DEVICE(QED5271LE, qed5271le);
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DECLARE_LEGACY_CPU_DEVICE(QED5271BE_INT, qed5271be_int);
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DECLARE_LEGACY_CPU_DEVICE(QED5271LE_INT, qed5271le_int);
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DECLARE_LEGACY_CPU_DEVICE(RM7000BE, rm7000be);
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DECLARE_LEGACY_CPU_DEVICE(RM7000LE, rm7000le);
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DECLARE_LEGACY_CPU_DEVICE(RM7000BE_INT, rm7000be_int);
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DECLARE_LEGACY_CPU_DEVICE(RM7000LE_INT, rm7000le_int);
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DECLARE_LEGACY_CPU_DEVICE(VR4300BE_DRC, vr4300be_drc);
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DECLARE_LEGACY_CPU_DEVICE(VR4300LE_DRC, vr4300le_drc);
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DECLARE_LEGACY_CPU_DEVICE(VR4310BE_DRC, vr4310be_drc);
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DECLARE_LEGACY_CPU_DEVICE(VR4310LE_DRC, vr4310le_drc);
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DECLARE_LEGACY_CPU_DEVICE(R4600BE_DRC, r4600be_drc);
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DECLARE_LEGACY_CPU_DEVICE(R4600LE_DRC, r4600le_drc);
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DECLARE_LEGACY_CPU_DEVICE(R4650BE_DRC, r4650be_drc);
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DECLARE_LEGACY_CPU_DEVICE(R4650LE_DRC, r4650le_drc);
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DECLARE_LEGACY_CPU_DEVICE(R4700BE_DRC, r4700be_drc);
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DECLARE_LEGACY_CPU_DEVICE(R4700LE_DRC, r4700le_drc);
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DECLARE_LEGACY_CPU_DEVICE(R5000BE_DRC, r5000be_drc);
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DECLARE_LEGACY_CPU_DEVICE(R5000LE_DRC, r5000le_drc);
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DECLARE_LEGACY_CPU_DEVICE(QED5271BE_DRC, qed5271be_drc);
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DECLARE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc);
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DECLARE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc);
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DECLARE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc);
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extern const device_type VR4300BE;
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extern const device_type VR4300LE;
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extern const device_type VR4310BE;
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extern const device_type VR4310LE;
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extern const device_type R4600BE;
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extern const device_type R4600LE;
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extern const device_type R4650BE;
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extern const device_type R4650LE;
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extern const device_type R4700BE;
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extern const device_type R4700LE;
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extern const device_type R5000BE;
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extern const device_type R5000LE;
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extern const device_type QED5271BE;
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extern const device_type QED5271LE;
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extern const device_type RM7000BE;
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extern const device_type RM7000LE;
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/***************************************************************************
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@ -19,8 +19,6 @@
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CONSTANTS
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***************************************************************************/
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#define MIPS3_USE_DRC
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/* core parameters */
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#define MIPS3_MIN_PAGE_SHIFT 12
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#define MIPS3_MIN_PAGE_SIZE (1 << MIPS3_MIN_PAGE_SHIFT)
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@ -62,8 +62,6 @@
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extern unsigned dasmmips3(char *buffer, unsigned pc, UINT32 op);
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#ifdef MIPS3_USE_DRC
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using namespace uml;
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/***************************************************************************
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@ -301,22 +299,22 @@ static const UINT8 fpmode_source[4] =
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INLINE mips3_state *get_safe_token(device_t *device)
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{
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assert(device != NULL);
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assert(device->type() == VR4300BE ||
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device->type() == VR4300LE ||
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device->type() == VR4310BE ||
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device->type() == VR4310LE ||
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device->type() == R4600BE ||
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device->type() == R4600LE ||
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device->type() == R4650BE ||
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device->type() == R4650LE ||
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device->type() == R4700BE ||
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device->type() == R4700LE ||
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device->type() == R5000BE ||
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device->type() == R5000LE ||
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device->type() == QED5271BE ||
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device->type() == QED5271LE ||
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device->type() == RM7000BE ||
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device->type() == RM7000LE);
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assert(device->type() == VR4300BE_DRC ||
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device->type() == VR4300LE_DRC ||
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device->type() == VR4310BE_DRC ||
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device->type() == VR4310LE_DRC ||
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device->type() == R4600BE_DRC ||
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device->type() == R4600LE_DRC ||
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device->type() == R4650BE_DRC ||
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device->type() == R4650LE_DRC ||
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device->type() == R4700BE_DRC ||
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device->type() == R4700LE_DRC ||
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device->type() == R5000BE_DRC ||
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device->type() == R5000LE_DRC ||
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device->type() == QED5271BE_DRC ||
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device->type() == QED5271LE_DRC ||
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device->type() == RM7000BE_DRC ||
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device->type() == RM7000LE_DRC);
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return *(mips3_state **)downcast<legacy_cpu_device *>(device)->token();
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}
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@ -639,6 +637,7 @@ static CPU_GET_INFO( mips3 )
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void mips3drc_set_options(device_t *device, UINT32 options)
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{
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if (!device->machine().options().drc()) return;
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mips3_state *mips3 = get_safe_token(device);
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mips3->impstate->drcoptions = options;
|
||||
}
|
||||
@ -651,6 +650,7 @@ void mips3drc_set_options(device_t *device, UINT32 options)
|
||||
|
||||
void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 readonly, void *base)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
mips3_state *mips3 = get_safe_token(device);
|
||||
if (mips3->impstate->fastram_select < ARRAY_LENGTH(mips3->impstate->fastram))
|
||||
{
|
||||
@ -669,6 +669,7 @@ void mips3drc_add_fastram(device_t *device, offs_t start, offs_t end, UINT8 read
|
||||
|
||||
void mips3drc_add_hotspot(device_t *device, offs_t pc, UINT32 opcode, UINT32 cycles)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
mips3_state *mips3 = get_safe_token(device);
|
||||
if (mips3->impstate->hotspot_select < ARRAY_LENGTH(mips3->impstate->hotspot))
|
||||
{
|
||||
@ -3705,7 +3706,7 @@ static CPU_INIT( vr4300le )
|
||||
mips3_init(MIPS3_TYPE_VR4300, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( vr4300be )
|
||||
CPU_GET_INFO( vr4300be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3724,7 +3725,7 @@ CPU_GET_INFO( vr4300be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( vr4300le )
|
||||
CPU_GET_INFO( vr4300le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3744,7 +3745,7 @@ CPU_GET_INFO( vr4300le )
|
||||
}
|
||||
|
||||
// VR4310 = VR4300 with different speed bin
|
||||
CPU_GET_INFO( vr4310be )
|
||||
CPU_GET_INFO( vr4310be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3763,7 +3764,7 @@ CPU_GET_INFO( vr4310be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( vr4310le )
|
||||
CPU_GET_INFO( vr4310le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3797,7 +3798,7 @@ static CPU_INIT( r4600le )
|
||||
mips3_init(MIPS3_TYPE_R4600, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r4600be )
|
||||
CPU_GET_INFO( r4600be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3816,7 +3817,7 @@ CPU_GET_INFO( r4600be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r4600le )
|
||||
CPU_GET_INFO( r4600le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3850,7 +3851,7 @@ static CPU_INIT( r4650le )
|
||||
mips3_init(MIPS3_TYPE_R4650, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r4650be )
|
||||
CPU_GET_INFO( r4650be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3869,7 +3870,7 @@ CPU_GET_INFO( r4650be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r4650le )
|
||||
CPU_GET_INFO( r4650le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3904,7 +3905,7 @@ static CPU_INIT( r4700le )
|
||||
mips3_init(MIPS3_TYPE_R4700, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r4700be )
|
||||
CPU_GET_INFO( r4700be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3923,7 +3924,7 @@ CPU_GET_INFO( r4700be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r4700le )
|
||||
CPU_GET_INFO( r4700le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3958,7 +3959,7 @@ static CPU_INIT( r5000le )
|
||||
mips3_init(MIPS3_TYPE_R5000, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r5000be )
|
||||
CPU_GET_INFO( r5000be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3977,7 +3978,7 @@ CPU_GET_INFO( r5000be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( r5000le )
|
||||
CPU_GET_INFO( r5000le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -4012,7 +4013,7 @@ static CPU_INIT( qed5271le )
|
||||
mips3_init(MIPS3_TYPE_QED5271, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( qed5271be )
|
||||
CPU_GET_INFO( qed5271be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -4031,7 +4032,7 @@ CPU_GET_INFO( qed5271be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( qed5271le )
|
||||
CPU_GET_INFO( qed5271le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -4066,7 +4067,7 @@ static CPU_INIT( rm7000le )
|
||||
mips3_init(MIPS3_TYPE_RM7000, FALSE, device, irqcallback);
|
||||
}
|
||||
|
||||
CPU_GET_INFO( rm7000be )
|
||||
CPU_GET_INFO( rm7000be_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -4085,7 +4086,7 @@ CPU_GET_INFO( rm7000be )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( rm7000le )
|
||||
CPU_GET_INFO( rm7000le_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -4104,27 +4105,26 @@ CPU_GET_INFO( rm7000le )
|
||||
}
|
||||
}
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4300BE, vr4300be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4300LE, vr4300le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4310BE, vr4310be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4310LE, vr4310le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4300BE_DRC, vr4300be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4300LE_DRC, vr4300le_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4310BE_DRC, vr4310be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(VR4310LE_DRC, vr4310le_drc);
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4600BE, r4600be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4600LE, r4600le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4600BE_DRC, r4600be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4600LE_DRC, r4600le_drc);
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4650BE, r4650be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4650LE, r4650le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4650BE_DRC, r4650be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4650LE_DRC, r4650le_drc);
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4700BE, r4700be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4700LE, r4700le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4700BE_DRC, r4700be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R4700LE_DRC, r4700le_drc);
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(R5000BE, r5000be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R5000LE, r5000le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R5000BE_DRC, r5000be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(R5000LE_DRC, r5000le_drc);
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(QED5271BE, qed5271be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(QED5271LE, qed5271le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(QED5271BE_DRC, qed5271be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(QED5271LE_DRC, qed5271le_drc);
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(RM7000BE, rm7000be);
|
||||
DEFINE_LEGACY_CPU_DEVICE(RM7000LE, rm7000le);
|
||||
DEFINE_LEGACY_CPU_DEVICE(RM7000BE_DRC, rm7000be_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(RM7000LE_DRC, rm7000le_drc);
|
||||
|
||||
#endif // MIPS3_USE_DRC
|
||||
|
||||
@ -11,8 +11,6 @@
|
||||
|
||||
CPU_DISASSEMBLE( rsp );
|
||||
|
||||
#ifndef USE_RSPDRC
|
||||
|
||||
#define LOG_INSTRUCTION_EXECUTION 0
|
||||
#define SAVE_DISASM 0
|
||||
#define SAVE_DMEM 0
|
||||
@ -33,7 +31,7 @@ extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
|
||||
INLINE rsp_state *get_safe_token(device_t *device)
|
||||
{
|
||||
assert(device != NULL);
|
||||
assert(device->type() == RSP);
|
||||
assert(device->type() == RSP_INT);
|
||||
return (rsp_state *)downcast<legacy_cpu_device *>(device)->token();
|
||||
}
|
||||
|
||||
@ -302,8 +300,8 @@ static CPU_INIT( rsp )
|
||||
rsp->flag[1] = 0;
|
||||
rsp->flag[2] = 0;
|
||||
rsp->flag[3] = 0;
|
||||
rsp->square_root_res = 0;
|
||||
rsp->square_root_high = 0;
|
||||
//rsp->square_root_res = 0;
|
||||
//rsp->square_root_high = 0;
|
||||
rsp->reciprocal_res = 0;
|
||||
rsp->reciprocal_high = 0;
|
||||
#endif
|
||||
@ -2991,7 +2989,7 @@ static CPU_SET_INFO( rsp )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( rsp )
|
||||
CPU_GET_INFO( rsp_int )
|
||||
{
|
||||
rsp_state *rsp = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
|
||||
@ -3123,22 +3121,6 @@ CPU_GET_INFO( rsp )
|
||||
}
|
||||
}
|
||||
|
||||
void rspdrc_flush_drc_cache(device_t *device)
|
||||
{
|
||||
}
|
||||
DEFINE_LEGACY_CPU_DEVICE(RSP_INT, rsp_int);
|
||||
|
||||
void rspdrc_set_options(device_t *device, UINT32 options)
|
||||
{
|
||||
}
|
||||
|
||||
void rspdrc_add_imem(device_t *device, UINT32 *base)
|
||||
{
|
||||
}
|
||||
|
||||
void rspdrc_add_dmem(device_t *device, UINT32 *base)
|
||||
{
|
||||
}
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(RSP, rsp);
|
||||
|
||||
#endif // USE_RSPDRC
|
||||
const device_type RSP = &legacy_device_creator_drc<rsp_int_device, rsp_drc_device>;
|
||||
|
||||
@ -22,8 +22,6 @@
|
||||
#include <tmmintrin.h>
|
||||
#endif
|
||||
|
||||
#define USE_RSPDRC
|
||||
|
||||
/***************************************************************************
|
||||
REGISTER ENUMERATION
|
||||
***************************************************************************/
|
||||
@ -214,7 +212,10 @@ struct rsp_state
|
||||
devcb_resolved_write32 sp_set_status_func;
|
||||
};
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(RSP, rsp);
|
||||
DECLARE_LEGACY_CPU_DEVICE(RSP_INT, rsp_int);
|
||||
DECLARE_LEGACY_CPU_DEVICE(RSP_DRC, rsp_drc);
|
||||
|
||||
extern const device_type RSP;
|
||||
|
||||
extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
|
||||
|
||||
|
||||
@ -33,8 +33,6 @@ CPU_DISASSEMBLE( rsp );
|
||||
|
||||
extern offs_t rsp_dasm_one(char *buffer, offs_t pc, UINT32 op);
|
||||
|
||||
#ifdef USE_RSPDRC
|
||||
|
||||
/***************************************************************************
|
||||
DEBUGGING
|
||||
***************************************************************************/
|
||||
@ -267,7 +265,7 @@ static void log_add_disasm_comment(rsp_state *rsp, drcuml_block *block, UINT32 p
|
||||
INLINE rsp_state *get_safe_token(device_t *device)
|
||||
{
|
||||
assert(device != NULL);
|
||||
assert(device->type() == RSP);
|
||||
assert(device->type() == RSP_DRC);
|
||||
return *(rsp_state **)downcast<legacy_cpu_device *>(device)->token();
|
||||
}
|
||||
|
||||
@ -333,6 +331,7 @@ INLINE void save_fast_iregs(rsp_state *rsp, drcuml_block *block)
|
||||
|
||||
void rspdrc_add_imem(device_t *device, UINT32 *base)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
rsp_state *rsp = get_safe_token(device);
|
||||
rsp->imem32 = base;
|
||||
rsp->imem16 = (UINT16*)base;
|
||||
@ -341,6 +340,7 @@ void rspdrc_add_imem(device_t *device, UINT32 *base)
|
||||
|
||||
void rspdrc_add_dmem(device_t *device, UINT32 *base)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
rsp_state *rsp = get_safe_token(device);
|
||||
rsp->dmem32 = base;
|
||||
rsp->dmem16 = (UINT16*)base;
|
||||
@ -445,6 +445,7 @@ static void cfunc_write32(void *param)
|
||||
|
||||
void rspdrc_set_options(device_t *device, UINT32 options)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
rsp_state *rsp = get_safe_token(device);
|
||||
rsp->impstate->drcoptions = options;
|
||||
}
|
||||
@ -4634,6 +4635,7 @@ static CPU_EXECUTE( rsp )
|
||||
|
||||
void rspdrc_flush_drc_cache(device_t *device)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
rsp_state *rsp = get_safe_token(device);
|
||||
rsp->impstate->cache_dirty = TRUE;
|
||||
}
|
||||
@ -5969,7 +5971,7 @@ static CPU_SET_INFO( rsp )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( rsp )
|
||||
CPU_GET_INFO( rsp_drc )
|
||||
{
|
||||
rsp_state *rsp = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
|
||||
@ -6169,6 +6171,5 @@ CPU_GET_INFO( rsp )
|
||||
}
|
||||
}
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(RSP, rsp);
|
||||
DEFINE_LEGACY_CPU_DEVICE(RSP_DRC, rsp_drc);
|
||||
|
||||
#endif // USE_RSPDRC
|
||||
|
||||
@ -112,7 +112,6 @@
|
||||
|
||||
CPU_DISASSEMBLE( sh2 );
|
||||
|
||||
#ifndef USE_SH2DRC
|
||||
|
||||
/* speed up delay loops, bail out of tight loops */
|
||||
#define BUSY_LOOP_HACKS 1
|
||||
@ -124,8 +123,8 @@ CPU_DISASSEMBLE( sh2 );
|
||||
INLINE sh2_state *get_safe_token(device_t *device)
|
||||
{
|
||||
assert(device != NULL);
|
||||
assert(device->type() == SH1 ||
|
||||
device->type() == SH2);
|
||||
assert(device->type() == SH1_INT ||
|
||||
device->type() == SH2_INT);
|
||||
return (sh2_state *)downcast<legacy_cpu_device *>(device)->token();
|
||||
}
|
||||
|
||||
@ -2311,7 +2310,7 @@ static CPU_INIT( sh2 )
|
||||
sh2_state *sh2 = get_safe_token(device);
|
||||
|
||||
/* initialize the common core parts */
|
||||
sh2_common_init(sh2, device, irqcallback);
|
||||
sh2_common_init(sh2, device, irqcallback,false);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
@ -2378,7 +2377,7 @@ static CPU_SET_INFO( sh2 )
|
||||
* Generic get_info
|
||||
**************************************************************************/
|
||||
|
||||
CPU_GET_INFO( sh2 )
|
||||
CPU_GET_INFO( sh2_int )
|
||||
{
|
||||
sh2_state *sh2 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
switch (state)
|
||||
@ -2507,7 +2506,7 @@ CPU_GET_INFO( sh2 )
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( sh1 )
|
||||
CPU_GET_INFO( sh1_int )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -2518,21 +2517,13 @@ CPU_GET_INFO( sh1 )
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "SH-1"); break;
|
||||
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh1"); break;
|
||||
|
||||
default: CPU_GET_INFO_CALL(sh2); break;
|
||||
default: CPU_GET_INFO_CALL(sh2_int); break;
|
||||
}
|
||||
}
|
||||
|
||||
void sh2drc_set_options(device_t *device, UINT32 options)
|
||||
{
|
||||
/* doesn't apply here */
|
||||
}
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH1_INT, sh1_int);
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH2_INT, sh2_int);
|
||||
|
||||
void sh2drc_add_pcflush(device_t *device, offs_t address)
|
||||
{
|
||||
/* doesn't apply here */
|
||||
}
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH1, sh1);
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH2, sh2);
|
||||
|
||||
#endif
|
||||
const device_type SH1 = &legacy_device_creator_drc<sh1_int_device, sh1_drc_device>;
|
||||
const device_type SH2 = &legacy_device_creator_drc<sh2_int_device, sh2_drc_device>;
|
||||
|
||||
@ -64,8 +64,13 @@ struct sh2_cpu_core
|
||||
int (*dma_callback_fifo_data_available)(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
|
||||
};
|
||||
|
||||
DECLARE_LEGACY_CPU_DEVICE(SH1, sh1);
|
||||
DECLARE_LEGACY_CPU_DEVICE(SH2, sh2);
|
||||
DECLARE_LEGACY_CPU_DEVICE(SH1_INT, sh1_int);
|
||||
DECLARE_LEGACY_CPU_DEVICE(SH2_INT, sh2_int);
|
||||
DECLARE_LEGACY_CPU_DEVICE(SH1_DRC, sh1_drc);
|
||||
DECLARE_LEGACY_CPU_DEVICE(SH2_DRC, sh2_drc);
|
||||
|
||||
extern const device_type SH1;
|
||||
extern const device_type SH2;
|
||||
|
||||
DECLARE_WRITE32_HANDLER( sh2_internal_w );
|
||||
DECLARE_READ32_HANDLER( sh2_internal_r );
|
||||
|
||||
@ -15,12 +15,14 @@
|
||||
|
||||
#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
#define GET_SH2(dev) *(sh2_state **)downcast<legacy_cpu_device *>(dev)->token()
|
||||
#else
|
||||
#define GET_SH2(dev) (sh2_state *)downcast<legacy_cpu_device *>(dev)->token()
|
||||
#endif
|
||||
|
||||
INLINE sh2_state *GET_SH2(device_t *dev)
|
||||
{
|
||||
if (dev->machine().options().drc()) {
|
||||
return *(sh2_state **)downcast<legacy_cpu_device *>(dev)->token();
|
||||
} else {
|
||||
return (sh2_state *)downcast<legacy_cpu_device *>(dev)->token();
|
||||
}
|
||||
}
|
||||
|
||||
static const int div_tab[4] = { 3, 5, 7, 0 };
|
||||
|
||||
@ -517,9 +519,9 @@ WRITE32_HANDLER( sh2_internal_w )
|
||||
sh2_state *sh2 = GET_SH2(&space.device());
|
||||
UINT32 old;
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
offset &= 0x7f;
|
||||
#endif
|
||||
if (sh2->isdrc)
|
||||
offset &= 0x7f;
|
||||
|
||||
|
||||
old = sh2->m[offset];
|
||||
COMBINE_DATA(sh2->m+offset);
|
||||
@ -737,9 +739,9 @@ READ32_HANDLER( sh2_internal_r )
|
||||
{
|
||||
sh2_state *sh2 = GET_SH2(&space.device());
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
if (sh2->isdrc)
|
||||
offset &= 0x7f;
|
||||
#endif
|
||||
|
||||
// logerror("sh2_internal_r: Read %08x (%x) @ %08x\n", 0xfffffe00+offset*4, offset, mem_mask);
|
||||
switch( offset )
|
||||
{
|
||||
@ -841,9 +843,8 @@ void sh2_set_irq_line(sh2_state *sh2, int irqline, int state)
|
||||
|
||||
sh2_exception(sh2, "Set IRQ line", 16);
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
sh2->pending_nmi = 1;
|
||||
#endif
|
||||
if (sh2->isdrc)
|
||||
sh2->pending_nmi = 1;
|
||||
}
|
||||
}
|
||||
else
|
||||
@ -861,14 +862,15 @@ void sh2_set_irq_line(sh2_state *sh2, int irqline, int state)
|
||||
{
|
||||
LOG(("SH-2 '%s' assert irq #%d\n", sh2->device->tag(), irqline));
|
||||
sh2->pending_irq |= 1 << irqline;
|
||||
#ifdef USE_SH2DRC
|
||||
if (sh2->isdrc)
|
||||
{
|
||||
sh2->test_irq = 1;
|
||||
#else
|
||||
} else {
|
||||
if(sh2->delay)
|
||||
sh2->test_irq = 1;
|
||||
else
|
||||
CHECK_PENDING_IRQ("sh2_set_irq_line");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -956,7 +958,8 @@ void sh2_exception(sh2_state *sh2, const char *message, int irqline)
|
||||
LOG(("SH-2 '%s' nmi exception (autovector: $%x) after [%s]\n", sh2->device->tag(), vector, message));
|
||||
}
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
if (sh2->isdrc)
|
||||
{
|
||||
sh2->evec = RL( sh2, sh2->vbr + vector * 4 );
|
||||
sh2->evec &= AM;
|
||||
sh2->irqsr = sh2->sr;
|
||||
@ -968,7 +971,7 @@ void sh2_exception(sh2_state *sh2, const char *message, int irqline)
|
||||
sh2->sr = (sh2->sr & ~I) | (irqline << 4);
|
||||
|
||||
// printf("sh2_exception [%s] irqline %x evec %x save SR %x new SR %x\n", message, irqline, sh2->evec, sh2->irqsr, sh2->sr);
|
||||
#else
|
||||
} else {
|
||||
sh2->r[15] -= 4;
|
||||
WL( sh2, sh2->r[15], sh2->sr ); /* push SR onto stack */
|
||||
sh2->r[15] -= 4;
|
||||
@ -982,16 +985,17 @@ void sh2_exception(sh2_state *sh2, const char *message, int irqline)
|
||||
|
||||
/* fetch PC */
|
||||
sh2->pc = RL( sh2, sh2->vbr + vector * 4 );
|
||||
#endif
|
||||
}
|
||||
|
||||
if(sh2->sleep_mode == 1) { sh2->sleep_mode = 2; }
|
||||
}
|
||||
|
||||
void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback)
|
||||
void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, bool drc)
|
||||
{
|
||||
const sh2_cpu_core *conf = (const sh2_cpu_core *)device->static_config();
|
||||
int i;
|
||||
|
||||
sh2->isdrc = drc;
|
||||
sh2->timer = device->machine().scheduler().timer_alloc(FUNC(sh2_timer_callback), sh2);
|
||||
sh2->timer->adjust(attotime::never);
|
||||
|
||||
|
||||
@ -12,17 +12,14 @@
|
||||
#define __SH2COMN_H__
|
||||
|
||||
|
||||
#define USE_SH2DRC
|
||||
|
||||
// do we use a timer for the DMA, or have it in CPU_EXECUTE
|
||||
#define USE_TIMER_FOR_DMA
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
#include "cpu/drcfe.h"
|
||||
#include "cpu/drcuml.h"
|
||||
#include "cpu/drcumlsh.h"
|
||||
class sh2_frontend;
|
||||
#endif
|
||||
|
||||
#define SH2_CODE_XOR(a) ((a) ^ NATIVE_ENDIAN_VALUE_LE_BE(2,0))
|
||||
|
||||
@ -120,6 +117,8 @@ struct sh2_state
|
||||
UINT32 irqsr; // IRQ-time old SR for DRC
|
||||
UINT32 target; // target for jmp/jsr/etc so the delay slot can't kill it
|
||||
irq_entry irq_queue[16];
|
||||
|
||||
bool isdrc;
|
||||
|
||||
int pcfsel; // last pcflush entry set
|
||||
int maxpcfsel; // highest valid pcflush entry
|
||||
@ -166,7 +165,6 @@ struct sh2_state
|
||||
|
||||
void (*ftcsr_read_callback)(UINT32 data);
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
drc_cache * cache; /* pointer to the DRC code cache */
|
||||
drcuml_state * drcuml; /* DRC UML generator state */
|
||||
sh2_frontend * drcfe; /* pointer to the DRC front-end state */
|
||||
@ -199,10 +197,8 @@ struct sh2_state
|
||||
/* fast RAM */
|
||||
UINT32 fastram_select;
|
||||
fast_ram_info fastram[SH2_MAX_FASTRAM];
|
||||
#endif
|
||||
};
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
class sh2_frontend : public drc_frontend
|
||||
{
|
||||
public:
|
||||
@ -222,9 +218,8 @@ private:
|
||||
|
||||
sh2_state &m_context;
|
||||
};
|
||||
#endif
|
||||
|
||||
void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback);
|
||||
void sh2_common_init(sh2_state *sh2, legacy_cpu_device *device, device_irq_acknowledge_callback irqcallback, bool drc);
|
||||
void sh2_recalc_irq(sh2_state *sh2);
|
||||
void sh2_set_irq_line(sh2_state *sh2, int irqline, int state);
|
||||
void sh2_exception(sh2_state *sh2, const char *message, int irqline);
|
||||
|
||||
@ -17,8 +17,6 @@
|
||||
CPU_DISASSEMBLE( sh2 );
|
||||
extern unsigned DasmSH2(char *buffer, unsigned pc, UINT16 opcode);
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
|
||||
using namespace uml;
|
||||
|
||||
/***************************************************************************
|
||||
@ -134,8 +132,8 @@ static void cfunc_DIV1(void *param);
|
||||
INLINE sh2_state *get_safe_token(device_t *device)
|
||||
{
|
||||
assert(device != NULL);
|
||||
assert(device->type() == SH1 ||
|
||||
device->type() == SH2);
|
||||
assert(device->type() == SH1_DRC ||
|
||||
device->type() == SH2_DRC);
|
||||
return *(sh2_state **)downcast<legacy_cpu_device *>(device)->token();
|
||||
}
|
||||
|
||||
@ -668,7 +666,7 @@ static CPU_INIT( sh2 )
|
||||
memset(sh2, 0, sizeof(sh2_state));
|
||||
|
||||
/* initialize the common core parts */
|
||||
sh2_common_init(sh2, device, irqcallback);
|
||||
sh2_common_init(sh2, device, irqcallback,true);
|
||||
|
||||
/* allocate the implementation-specific state from the full cache */
|
||||
sh2->cache = cache;
|
||||
@ -3182,6 +3180,7 @@ static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state
|
||||
|
||||
void sh2drc_set_options(device_t *device, UINT32 options)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
sh2_state *sh2 = get_safe_token(device);
|
||||
sh2->drcoptions = options;
|
||||
}
|
||||
@ -3194,6 +3193,7 @@ void sh2drc_set_options(device_t *device, UINT32 options)
|
||||
|
||||
void sh2drc_add_pcflush(device_t *device, offs_t address)
|
||||
{
|
||||
if (!device->machine().options().drc()) return;
|
||||
sh2_state *sh2 = get_safe_token(device);
|
||||
|
||||
if (sh2->pcfsel < ARRAY_LENGTH(sh2->pcflushes))
|
||||
@ -3303,7 +3303,7 @@ static CPU_SET_INFO( sh2 )
|
||||
given CPU instance
|
||||
-------------------------------------------------*/
|
||||
|
||||
CPU_GET_INFO( sh2 )
|
||||
CPU_GET_INFO( sh2_drc )
|
||||
{
|
||||
sh2_state *sh2 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
|
||||
switch (state)
|
||||
@ -3442,7 +3442,7 @@ CPU_GET_INFO( sh2 )
|
||||
given CPU instance
|
||||
-------------------------------------------------*/
|
||||
|
||||
CPU_GET_INFO( sh1 )
|
||||
CPU_GET_INFO( sh1_drc )
|
||||
{
|
||||
switch (state)
|
||||
{
|
||||
@ -3453,11 +3453,9 @@ CPU_GET_INFO( sh1 )
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "SH-1 DRC"); break;
|
||||
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh1_drc"); break;
|
||||
|
||||
default: CPU_GET_INFO_CALL(sh2); break;
|
||||
default: CPU_GET_INFO_CALL(sh2_drc); break;
|
||||
}
|
||||
}
|
||||
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH1, sh1);
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH2, sh2);
|
||||
|
||||
#endif // USE_SH2DRC
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH1_DRC, sh1_drc);
|
||||
DEFINE_LEGACY_CPU_DEVICE(SH2_DRC, sh2_drc);
|
||||
|
||||
@ -14,7 +14,6 @@
|
||||
#include "sh2comn.h"
|
||||
#include "cpu/drcfe.h"
|
||||
|
||||
#ifdef USE_SH2DRC
|
||||
/***************************************************************************
|
||||
INSTRUCTION PARSERS
|
||||
***************************************************************************/
|
||||
@ -761,4 +760,4 @@ bool sh2_frontend::describe_group_12(opcode_desc &desc, const opcode_desc *prev,
|
||||
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@ -46,6 +46,8 @@
|
||||
#ifndef __DEVCPU_H__
|
||||
#define __DEVCPU_H__
|
||||
|
||||
#include "emuopts.h"
|
||||
|
||||
//**************************************************************************
|
||||
// CONSTANTS
|
||||
//**************************************************************************
|
||||
@ -298,6 +300,16 @@ device_t *legacy_device_creator(const machine_config &mconfig, const char *tag,
|
||||
return global_alloc(_DeviceClass(mconfig, &legacy_device_creator<_DeviceClass>, tag, owner, clock));
|
||||
}
|
||||
|
||||
// this template function creates a stub which constructs a device
|
||||
template<class _DeviceClass1,class _DeviceClass2>
|
||||
device_t *legacy_device_creator_drc(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
{
|
||||
if (mconfig.options().drc())
|
||||
return global_alloc(_DeviceClass2(mconfig, &legacy_device_creator<_DeviceClass2>, tag, owner, clock));
|
||||
else
|
||||
return global_alloc(_DeviceClass1(mconfig, &legacy_device_creator<_DeviceClass1>, tag, owner, clock));
|
||||
}
|
||||
|
||||
//**************************************************************************
|
||||
// TYPE DEFINITIONS
|
||||
//**************************************************************************
|
||||
|
||||
@ -107,13 +107,13 @@ typedef device_t * (*machine_config_constructor)(machine_config &config, device_
|
||||
#include "timer.h"
|
||||
#include "dinetwork.h"
|
||||
|
||||
// timers, CPU and scheduling
|
||||
#include "devcpu.h"
|
||||
|
||||
// machine and driver configuration
|
||||
#include "mconfig.h"
|
||||
#include "gamedrv.h"
|
||||
|
||||
// timers, CPU and scheduling
|
||||
#include "devcpu.h"
|
||||
|
||||
// image-related
|
||||
#include "softlist.h"
|
||||
#include "image.h"
|
||||
|
||||
@ -189,6 +189,7 @@ const options_entry emu_options::s_option_entries[] =
|
||||
|
||||
// misc options
|
||||
{ NULL, NULL, OPTION_HEADER, "CORE MISC OPTIONS" },
|
||||
{ OPTION_DRC, "1", OPTION_BOOLEAN, "enable DRC cpu core if available" },
|
||||
{ OPTION_BIOS, NULL, OPTION_STRING, "select the system BIOS to use" },
|
||||
{ OPTION_CHEAT ";c", "0", OPTION_BOOLEAN, "enable cheat subsystem" },
|
||||
{ OPTION_SKIP_GAMEINFO, "0", OPTION_BOOLEAN, "skip displaying the information screen at startup" },
|
||||
|
||||
@ -191,6 +191,7 @@ enum
|
||||
#define OPTION_DEBUGSCRIPT "debugscript"
|
||||
|
||||
// core misc options
|
||||
#define OPTION_DRC "drc"
|
||||
#define OPTION_BIOS "bios"
|
||||
#define OPTION_CHEAT "cheat"
|
||||
#define OPTION_SKIP_GAMEINFO "skip_gameinfo"
|
||||
@ -353,6 +354,7 @@ public:
|
||||
bool update_in_pause() const { return bool_value(OPTION_UPDATEINPAUSE); }
|
||||
|
||||
// core misc options
|
||||
bool drc() const { return bool_value(OPTION_DRC); }
|
||||
const char *bios() const { return value(OPTION_BIOS); }
|
||||
bool cheat() const { return bool_value(OPTION_CHEAT); }
|
||||
bool skip_gameinfo() const { return bool_value(OPTION_SKIP_GAMEINFO); }
|
||||
|
||||
Loading…
Reference in New Issue
Block a user