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ppu2c0x & vsnes privatize variables (nw)
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@ -191,6 +191,26 @@ public:
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required_device<cpu_device> m_cpu;
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// some bootleg / clone hardware appears to ignore this
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static void use_sprite_write_limitation_disable(device_t &device)
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{
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ppu2c0x_device &dev = downcast<ppu2c0x_device &>(device);
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dev.m_use_sprite_write_limitation = false;
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}
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protected:
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int m_scanlines_per_frame; /* number of scanlines per frame */
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int m_security_value; /* 2C05 protection */
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int m_vblank_first_scanline; /* the very first scanline where VBLANK occurs */
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private:
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static const device_timer_id TIMER_HBLANK = 0;
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static const device_timer_id TIMER_NMI = 1;
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static const device_timer_id TIMER_SCANLINE = 2;
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inline uint8_t readbyte(offs_t address);
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inline void writebyte(offs_t address, uint8_t data);
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std::unique_ptr<bitmap_ind16> m_bitmap; /* target bitmap */
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std::unique_ptr<uint8_t[]> m_spriteram; /* sprite ram */
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std::unique_ptr<pen_t[]> m_colortable; /* color table modified at run time */
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@ -215,9 +235,6 @@ public:
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int m_color_base;
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uint8_t m_palette_ram[0x20]; /* shouldn't be in main memory! */
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int m_scan_scale; /* scan scale */
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int m_scanlines_per_frame; /* number of scanlines per frame */
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int m_vblank_first_scanline; /* the very first scanline where VBLANK occurs */
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int m_security_value; /* 2C05 protection */
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int m_tilecount; /* MMC5 can change attributes to subsets of the 34 visible tiles */
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int m_draw_phase; /* MMC5 uses different regs for BG and OAM */
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ppu2c0x_latch_delegate m_latch;
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@ -226,23 +243,8 @@ public:
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emu_timer *m_hblank_timer; /* hblank period at end of each scanline */
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emu_timer *m_nmi_timer; /* NMI timer */
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emu_timer *m_scanline_timer; /* scanline timer */
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// some bootleg / clone hardware appears to ignore this
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static void use_sprite_write_limitation_disable(device_t &device)
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{
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ppu2c0x_device &dev = downcast<ppu2c0x_device &>(device);
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dev.m_use_sprite_write_limitation = false;
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}
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bool m_use_sprite_write_limitation;
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private:
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static const device_timer_id TIMER_HBLANK = 0;
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static const device_timer_id TIMER_NMI = 1;
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static const device_timer_id TIMER_SCANLINE = 2;
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inline uint8_t readbyte(offs_t address);
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inline void writebyte(offs_t address, uint8_t data);
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};
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class ppu2c02_device : public ppu2c0x_device {
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@ -29,35 +29,6 @@ public:
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optional_memory_region m_gfx1_rom;
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int m_coin;
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int m_do_vrom_bank;
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int m_input_latch[4];
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int m_sound_fix;
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uint8_t m_last_bank;
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std::unique_ptr<uint8_t[]> m_vram;
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uint8_t* m_vrom[2];
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std::unique_ptr<uint8_t[]> m_nt_ram[2];
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uint8_t* m_nt_page[2][4];
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uint32_t m_vrom_size[2];
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int m_vrom_banks;
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int m_zapstore;
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int m_old_bank;
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int m_drmario_shiftreg;
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int m_drmario_shiftcount;
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int m_size16k;
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int m_switchlow;
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int m_vrom4k;
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int m_MMC3_cmd;
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int m_MMC3_prg_bank[4];
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int m_MMC3_chr_bank[6];
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int m_MMC3_prg_mask;
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int m_IRQ_enable;
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int m_IRQ_count;
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int m_IRQ_count_latch;
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int m_VSindex;
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int m_supxevs_prot_index;
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int m_security_counter;
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int m_ret;
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DECLARE_WRITE8_MEMBER(sprite_dma_0_w);
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DECLARE_WRITE8_MEMBER(sprite_dma_1_w);
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DECLARE_WRITE8_MEMBER(vsnes_coin_counter_w);
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@ -129,7 +100,38 @@ public:
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DECLARE_WRITE8_MEMBER(bootleg_sound_write);
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DECLARE_READ8_MEMBER(vsnes_bootleg_z80_data_r);
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DECLARE_READ8_MEMBER(vsnes_bootleg_z80_address_r);
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private:
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int m_coin;
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int m_do_vrom_bank;
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int m_input_latch[4];
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int m_sound_fix;
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uint8_t m_last_bank;
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std::unique_ptr<uint8_t[]> m_vram;
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uint8_t* m_vrom[2];
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std::unique_ptr<uint8_t[]> m_nt_ram[2];
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uint8_t* m_nt_page[2][4];
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uint32_t m_vrom_size[2];
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int m_vrom_banks;
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int m_zapstore;
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int m_old_bank;
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int m_drmario_shiftreg;
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int m_drmario_shiftcount;
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int m_size16k;
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int m_switchlow;
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int m_vrom4k;
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int m_MMC3_cmd;
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int m_MMC3_prg_bank[4];
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int m_MMC3_chr_bank[6];
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int m_MMC3_prg_mask;
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int m_IRQ_enable;
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int m_IRQ_count;
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int m_IRQ_count_latch;
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int m_VSindex;
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int m_supxevs_prot_index;
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int m_security_counter;
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int m_ret;
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uint8_t m_bootleg_sound_offset;
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uint8_t m_bootleg_sound_data;
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};
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