mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
Splitted out FGA-002 as its own device, Added CPU-33 roms, Added CPU-30 board layout
This commit is contained in:
Joakim Larsson Edstrom
parent
d9b44f4936
commit
e7fc2fe0db
@ -19,52 +19,52 @@
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* ||||--||_____________________________________________________________
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* ||||--|| |
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* || || _ |__
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | |VME|
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* || | | |
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* || | |P1 |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || |_| |
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* || |___|
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* || |
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* || |
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* || |
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* || |
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* || |
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* || |
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* || |
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* || |
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* || |___
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* || _| |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | |VME|
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* || | | |
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* || | |P2 |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || | | |
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* || |_| |
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* || |___|
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* || || +
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* ||||--|| |
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* || +----------------+ | | |
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* RST O=== | | | | |
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* || | | | | |
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* ABT O=== | FGA-002 | | | |
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RUN/HLT C| GREEN/RED +------------+ | | | | |
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BUS MST C| GREEN/unlit |System flash| | | | | |
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* || +------------+ | | | |VME|
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* rot [O SW4 +------------+ +----------------+ | | |
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* swtshs|| |System Flash| | |P1 |
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* [O SW3 +------------+ +----------+ | | |
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* || +------------+ | | | | |
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* || |System Flash| | 68030 | | | |
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* | || +------------+ | | | | |
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* |--| +------------+ | | | | |
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* AUI | | |System Flash| +----------+ | | |
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* eth| | +------------+ |_| |
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* | | +----------+ |___|
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* | | +-----+ | | |
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* |--| |SIA | | 68882 | |
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* | || |7992 | | | |
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* || +-----+ J28 | | |
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* || +------+ +----------+ |
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* || | Opt | |
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* ||| | Boot | |
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* +---+ | PROM | |
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* Ser | = +----------+ +------+ +--------+ |___
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* #3 | = | LANCE | +------+ | SCSI | _ _| |
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* | = | 7970 | | Def | | 87034 | | | |
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* +---+ | | | Boot | | | | | |
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* ||| | | | PROM | +--------+ | | |
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* || +----------+ +------+ | | |
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* ||| +----+ J36 +------+ | |VME|
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* +---+ |NV- | | FDC | | | |
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* Ser | = | RAM| |37C65C| | |P2 |
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* #2 | = | | +------+ | | |
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* | = +----+ | 5 row |
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* +---+ +--------+ +--------+ | conn- |
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* ||| +-----+ | DUSCC1 | | PIT1 | | ector|
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* || | OPT | | 68562 | | 68230 | | | |
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* ||| |NVRAM| | | | | | | |
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* +---+ | | +--------+ +--------+ | | |
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* Ser | = | | ____ +--------+ +--------+ | | |
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* #1 | = | | / \ | DUSCC2 | | PIT2 | |_ _| |
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* | = | | BATTERY | 68562 | | 68230 | |___|
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* || +---+ +-----+ \____/ | | | | +
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* ||||--|| +--------+ +--------+ |
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* ||||--||--------------------------------------------------------------+
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* ||
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*
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@ -160,6 +160,7 @@
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#include "cpu/m68000/m68000.h"
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#include "machine/scnxx562.h"
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#include "machine/68230pit.h"
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#include "machine/fga002.h"
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#include "machine/nvram.h"
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#include "bus/rs232/rs232.h"
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#include "machine/clock.h"
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@ -189,14 +190,12 @@ fccpu30_state(const machine_config &mconfig, device_type type, const char *tag)
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, m_dusccterm(*this, "duscc")
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, m_pit1 (*this, "pit1")
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, m_pit2 (*this, "pit2")
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, m_fga002 (*this, "fga002")
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{
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}
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DECLARE_READ32_MEMBER (bootvect_r);
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DECLARE_WRITE32_MEMBER (bootvect_w);
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/* FGA-002 - Force Gate Array */
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DECLARE_READ8_MEMBER (fga8_r);
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DECLARE_WRITE8_MEMBER (fga8_w);
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/* Rotary switch PIT input */
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DECLARE_READ8_MEMBER (rotary_rd);
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@ -218,12 +217,11 @@ private:
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required_device<pit68230_device> m_pit1;
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required_device<pit68230_device> m_pit2;
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required_device<fga002_device> m_fga002;
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// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
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UINT32 *m_sysrom;
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UINT32 m_sysram[2];
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// FGA-002
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UINT8 m_fga002[0x500];
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};
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static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
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@ -236,7 +234,7 @@ static ADDRESS_MAP_START (fccpu30_mem, AS_PROGRAM, 32, fccpu30_state)
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AM_RANGE (0xff800c00, 0xff800dff) AM_DEVREADWRITE8("pit1", pit68230_device, read, write, 0xffffffff)
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AM_RANGE (0xff800e00, 0xff800fff) AM_DEVREADWRITE8("pit2", pit68230_device, read, write, 0xffffffff)
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AM_RANGE (0xffc00000, 0xffcfffff) AM_RAM AM_SHARE ("nvram") /* On-board SRAM with battery backup (nvram) */
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AM_RANGE (0xffd00000, 0xffd004ff) AM_READWRITE8(fga8_r, fga8_w, 0xffffffff) /* FGA-002 Force Gate Array */
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AM_RANGE (0xffd00000, 0xffdfffff) AM_DEVREADWRITE8("fga002", fga002_device, read, write, 0xffffffff) /* FGA-002 Force Gate Array */
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AM_RANGE (0xffe00000, 0xffefffff) AM_ROM AM_REGION("roms", 0x800000)
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//AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
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@ -247,100 +245,6 @@ ADDRESS_MAP_END
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static INPUT_PORTS_START (fccpu30)
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INPUT_PORTS_END
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#define FGA_ICRMBOX0 0x0000
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#define FGA_ICRMBOX1 0x0004
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#define FGA_ICRMBOX2 0x0008
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#define FGA_ICRMBOX3 0x000c
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#define FGA_ICRMBOX4 0x0010
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#define FGA_ICRMBOX5 0x0014
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#define FGA_ICRMBOX6 0x0018
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#define FGA_ICRMBOX7 0x001C
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#define FGA_VMEPAGE 0x0200
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#define FGA_ICRVME1 0x0204
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#define FGA_ICRVME2 0x0208
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#define FGA_ICRVME3 0x020c
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#define FGA_ICRVME4 0x0210
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#define FGA_ICRVME5 0x0214
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#define FGA_ICRVME6 0x0218
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#define FGA_ICRVME7 0x021c
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#define FGA_ICRTIM0 0x0220
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#define FGA_ICRDMANORM 0x0230
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#define FGA_ICRDMAERR 0x0234
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#define FGA_CTL1 0x0238
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#define FGA_CTL2 0x023c
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#define FGA_ICRFMB0REF 0x0240
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#define FGA_ICRFMB1REF 0x0244
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#define FGA_ICRFMB0MES 0x0248
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#define FGA_ICRFMB1MES 0x024c
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#define FGA_CTL3 0x0250
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#define FGA_CTL4 0x0254
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#define FGA_ICRPARITY 0x0258
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#define FGA_AUXPINCTL 0x0260
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#define FGA_CTL5 0x0264
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#define FGA_AUXFIFWEX 0x0268
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#define FGA_AUXFIFREX 0x026c
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#define FGA_CTL6 0x0270
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#define FGA_CTL7 0x0274
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#define FGA_CTL8 0x0278
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#define FGA_CTL9 0x027c
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#define FGA_ICRABORT 0x0280
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#define FGA_ICRACFAIL 0x0284
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#define FGA_ICRSYSFAIL 0x0288
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#define FGA_ICRLOCAL0 0x028c
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#define FGA_ICRLOCAL1 0x0290
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#define FGA_ICRLOCAL2 0x0294
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#define FGA_ICRLOCAL3 0x0298
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#define FGA_ICRLOCAL4 0x029c
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#define FGA_ICRLOCAL5 0x02a0
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#define FGA_ICRLOCAL6 0x02a4
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#define FGA_ICRLOCAL7 0x02a8
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#define FGA_ENAMCODE 0x02b4
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#define FGA_CTL10 0x02c0
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#define FGA_CTL11 0x02c4
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#define FGA_MAINUM 0x02c8
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#define FGA_MAINUU 0x02cc
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#define FGA_BOTTOMPAGEU 0x02d0
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#define FGA_BOTTOMPAGEL 0x02d4
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#define FGA_TOPPAGEU 0x02d8
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#define FGA_TOPPAGEL 0x02dc
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#define FGA_MYVMEPAGE 0x02fc
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#define FGA_TIM0PRELOAD 0x0300
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#define FGA_TIM0CTL 0x0310
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#define FGA_DMASRCATT 0x0320
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#define FGA_DMADSTATT 0x0324
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#define FGA_DMA_GENERAL 0x0328
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#define FGA_CTL12 0x032c
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#define FGA_LIOTIMING 0x0330
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#define FGA_LOCALIACK 0x0334
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#define FGA_FMBCTL 0x0338
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#define FGA_FMBAREA 0x033c
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#define FGA_AUXSRCSTART 0x0340
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#define FGA_AUXDSTSTART 0x0344
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#define FGA_AUXSRCTERM 0x0348
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#define FGA_AUXDSTTERM 0x034c
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#define FGA_CTL13 0x0350
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#define FGA_CTL14 0x0354
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#define FGA_CTL15 0x0358
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#define FGA_CTL16 0x035c
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#define FGA_SPECIALENA 0x0424
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#define FGA_ISTIM0 0x04a0
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#define FGA_ISDMANORM 0x04b0
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#define FGA_ISDMAERR 0x04b4
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#define FGA_ISFMB0REF 0x04b8
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#define FGA_ISFMB1REF 0x04bc
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#define FGA_ISPARITY 0x04c0
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#define FGA_DMARUNCTL 0x04c4
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#define FGA_ISABORT 0x04c8
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#define FGA_ISACFAIL 0x04cc
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#define FGA_ISFMB0MES 0x04e0
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#define FGA_ISFMB1MES 0x04e4
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#define FGA_ISSYSFAIL 0x04d0
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#define FGA_ABORTPIN 0x04d4
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#define FGA_RSVMECALL 0x04f0
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#define FGA_RSKEYRES 0x04f4
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#define FGA_RSCPUCALL 0x04f8
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#define FGA_RSLOCSW 0x04fc
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/* Start it up */
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void fccpu30_state::machine_start ()
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{
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@ -348,7 +252,6 @@ void fccpu30_state::machine_start ()
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save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
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save_pointer (NAME (m_sysram), sizeof(m_sysram));
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save_pointer (NAME (m_fga002), sizeof(m_fga002));
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/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
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m_sysrom = (UINT32*)(memregion ("roms")->base () + 0x800000);
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@ -361,24 +264,6 @@ void fccpu30_state::machine_reset ()
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/* Reset pointer to bootvector in ROM for bootvector handler bootvect_r */
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if (m_sysrom == &m_sysram[0]) /* Condition needed because memory map is not setup first time */
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m_sysrom = (UINT32*)(memregion ("roms")->base () + 0x800000);
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/* Reset values for the FGA-002 */
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memset(&m_fga002[0], 0, sizeof(m_fga002));
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m_fga002[FGA_RSVMECALL] = 0x80;
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m_fga002[FGA_RSKEYRES] = 0x80;
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m_fga002[FGA_RSCPUCALL] = 0x80;
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m_fga002[FGA_RSLOCSW] = 0x80;
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m_fga002[FGA_ISTIM0] = 0x80;
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m_fga002[FGA_ISDMANORM] = 0x80;
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m_fga002[FGA_ISDMAERR] = 0x80;
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m_fga002[FGA_ISFMB0REF] = 0x80;
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m_fga002[FGA_ISFMB1REF] = 0x80;
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m_fga002[FGA_ISPARITY] = 0x80;
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m_fga002[FGA_ISABORT] = 0x80;
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m_fga002[FGA_ISACFAIL] = 0x80;
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m_fga002[FGA_ISSYSFAIL] = 0x80;
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m_fga002[FGA_ISFMB0MES] = 0x80;
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m_fga002[FGA_ISFMB1MES] = 0x80;
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}
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/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset*/
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@ -392,229 +277,6 @@ WRITE32_MEMBER (fccpu30_state::bootvect_w){
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m_sysrom = &m_sysram[0]; // redirect all upcomming accesses to masking RAM until reset.
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}
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/*
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* FGA-002 driver, might deserve its own driver but will rest here until another board wants it
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*
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The FGA-002 gate array is a high speed CMOS device manufactured in 1.2 micron technology and
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containing 24,000 gates in a 281 pin PGA package. It provides interfaces to the 68020/30 microprocessor
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as well as a VMEbus compatible interface. The auxilary interface of the gate array is a high speed data
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channel used by the internal 32 bit DMA controller. The interface allows data transfer rates of up to
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6 MByte/second. The timing of the local I/O interface is programmable and provides easy interfacing of
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local I/O devices. All control, address and data lines of the CPU and the VMEbus are either directly
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connected or connected via buffers to the gate array allowing easy implementation and usage.
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The gate array registers are programmed by the local CPU.
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FEATURES:
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- Programmable decoding for CPU and VME access to the local main memory
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- Interrupt management for internal and external interrupt sources
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- 32 bit multi-port DMA Controller
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- FORCE Message Broadcast slave interface with 2 message channels
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- 8 interrupt capable MAILBOXES
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- 8 bit TIMER with 16 selectable internal source clocks
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*/
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WRITE8_MEMBER (fccpu30_state::fga8_w){
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LOG(("%s[%04x] <- %02x - ", FUNCNAME, offset, data));
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switch(offset)
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{
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case FGA_SPECIALENA : LOG(("FGA_SPECIALENA - not implemented\n")); m_fga002[FGA_SPECIALENA] = data; break;
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case FGA_RSVMECALL : LOG(("FGA_RSVMECALL - not implemented\n")); m_fga002[FGA_RSVMECALL] = data; break;
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case FGA_RSKEYRES : LOG(("FGA_RSKEYRES - not implemented\n")); m_fga002[FGA_RSKEYRES] = data; break;
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case FGA_RSCPUCALL : LOG(("FGA_RSCPUCALL - not implemented\n")); m_fga002[FGA_RSCPUCALL] = data; break;
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case FGA_RSLOCSW : LOG(("FGA_RSLOCSW - not implemented\n")); m_fga002[FGA_RSLOCSW] = data; break;
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case FGA_ICRMBOX0 : LOG(("FGA_ICRMBOX0 - not implemented\n")); m_fga002[FGA_ICRMBOX0] = data; break;
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case FGA_ICRMBOX1 : LOG(("FGA_ICRMBOX1 - not implemented\n")); m_fga002[FGA_ICRMBOX1] = data; break;
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case FGA_ICRMBOX2 : LOG(("FGA_ICRMBOX2 - not implemented\n")); m_fga002[FGA_ICRMBOX2] = data; break;
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case FGA_ICRMBOX3 : LOG(("FGA_ICRMBOX3 - not implemented\n")); m_fga002[FGA_ICRMBOX3] = data; break;
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case FGA_ICRMBOX4 : LOG(("FGA_ICRMBOX4 - not implemented\n")); m_fga002[FGA_ICRMBOX4] = data; break;
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case FGA_ICRMBOX5 : LOG(("FGA_ICRMBOX5 - not implemented\n")); m_fga002[FGA_ICRMBOX5] = data; break;
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case FGA_ICRMBOX6 : LOG(("FGA_ICRMBOX6 - not implemented\n")); m_fga002[FGA_ICRMBOX6] = data; break;
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case FGA_ICRMBOX7 : LOG(("FGA_ICRMBOX7 - not implemented\n")); m_fga002[FGA_ICRMBOX7] = data; break;
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case FGA_VMEPAGE : LOG(("FGA_VMEPAGE - not implemented\n")); m_fga002[FGA_VMEPAGE ] = data; break;
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case FGA_ICRVME1 : LOG(("FGA_ICRVME1 - not implemented\n")); m_fga002[FGA_ICRVME1] = data; break;
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case FGA_ICRVME2 : LOG(("FGA_ICRVME2 - not implemented\n")); m_fga002[FGA_ICRVME2] = data; break;
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case FGA_ICRVME3 : LOG(("FGA_ICRVME3 - not implemented\n")); m_fga002[FGA_ICRVME3] = data; break;
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case FGA_ICRVME4 : LOG(("FGA_ICRVME4 - not implemented\n")); m_fga002[FGA_ICRVME4] = data; break;
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case FGA_ICRVME5 : LOG(("FGA_ICRVME5 - not implemented\n")); m_fga002[FGA_ICRVME5] = data; break;
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case FGA_ICRVME6 : LOG(("FGA_ICRVME6 - not implemented\n")); m_fga002[FGA_ICRVME6] = data; break;
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case FGA_ICRVME7 : LOG(("FGA_ICRVME7 - not implemented\n")); m_fga002[FGA_ICRVME7] = data; break;
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case FGA_ICRTIM0 : LOG(("FGA_ICRTIM0 - not implemented\n")); m_fga002[FGA_ICRTIM0] = data; break;
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case FGA_ICRDMANORM : LOG(("FGA_ICRDMANORM - not implemented\n")); m_fga002[FGA_ICRDMANORM] = data; break;
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case FGA_ICRDMAERR : LOG(("FGA_ICRDMAERR - not implemented\n")); m_fga002[FGA_ICRDMAERR] = data; break;
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case FGA_CTL1 : LOG(("FGA_CTL1 - not implemented\n")); m_fga002[FGA_CTL1] = data; break;
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case FGA_CTL2 : LOG(("FGA_CTL2 - not implemented\n")); m_fga002[FGA_CTL2] = data; break;
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case FGA_ICRFMB0REF : LOG(("FGA_ICRFMB0REF - not implemented\n")); m_fga002[FGA_ICRFMB0REF] = data; break;
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case FGA_ICRFMB1REF : LOG(("FGA_ICRFMB1REF - not implemented\n")); m_fga002[FGA_ICRFMB1REF] = data; break;
|
||||
case FGA_ICRFMB0MES : LOG(("FGA_ICRFMB0MES - not implemented\n")); m_fga002[FGA_ICRFMB0MES] = data; break;
|
||||
case FGA_ICRFMB1MES : LOG(("FGA_ICRFMB1MES - not implemented\n")); m_fga002[FGA_ICRFMB1MES] = data; break;
|
||||
case FGA_CTL3 : LOG(("FGA_CTL3 - not implemented\n")); m_fga002[FGA_CTL3] = data; break;
|
||||
case FGA_CTL4 : LOG(("FGA_CTL4 - not implemented\n")); m_fga002[FGA_CTL4] = data; break;
|
||||
case FGA_ICRPARITY : LOG(("FGA_ICRPARITY - not implemented\n")); m_fga002[FGA_ICRPARITY] = data; break;
|
||||
case FGA_AUXPINCTL : LOG(("FGA_AUXPINCTL - not implemented\n")); m_fga002[FGA_AUXPINCTL] = data; break;
|
||||
case FGA_CTL5 : LOG(("FGA_CTL5 - not implemented\n")); m_fga002[FGA_CTL5] = data; break;
|
||||
case FGA_AUXFIFWEX : LOG(("FGA_AUXFIFWEX - not implemented\n")); m_fga002[FGA_AUXFIFWEX] = data; break;
|
||||
case FGA_AUXFIFREX : LOG(("FGA_AUXFIFREX - not implemented\n")); m_fga002[FGA_AUXFIFREX] = data; break;
|
||||
case FGA_CTL6 : LOG(("FGA_CTL6 - not implemented\n")); m_fga002[FGA_CTL6] = data; break;
|
||||
case FGA_CTL7 : LOG(("FGA_CTL7 - not implemented\n")); m_fga002[FGA_CTL7] = data; break;
|
||||
case FGA_CTL8 : LOG(("FGA_CTL8 - not implemented\n")); m_fga002[FGA_CTL8] = data; break;
|
||||
case FGA_CTL9 : LOG(("FGA_CTL9 - not implemented\n")); m_fga002[FGA_CTL9] = data; break;
|
||||
case FGA_ICRABORT : LOG(("FGA_ICRABORT - not implemented\n")); m_fga002[FGA_ICRABORT] = data; break;
|
||||
case FGA_ICRACFAIL : LOG(("FGA_ICRACFAIL - not implemented\n")); m_fga002[FGA_ICRACFAIL] = data; break;
|
||||
case FGA_ICRSYSFAIL : LOG(("FGA_ICRSYSFAIL - not implemented\n")); m_fga002[FGA_ICRSYSFAIL] = data; break;
|
||||
case FGA_ICRLOCAL0 : LOG(("FGA_ICRLOCAL0 - not implemented\n")); m_fga002[FGA_ICRLOCAL0] = data; break;
|
||||
case FGA_ICRLOCAL1 : LOG(("FGA_ICRLOCAL1 - not implemented\n")); m_fga002[FGA_ICRLOCAL1] = data; break;
|
||||
case FGA_ICRLOCAL2 : LOG(("FGA_ICRLOCAL2 - not implemented\n")); m_fga002[FGA_ICRLOCAL2] = data; break;
|
||||
case FGA_ICRLOCAL3 : LOG(("FGA_ICRLOCAL3 - not implemented\n")); m_fga002[FGA_ICRLOCAL3] = data; break;
|
||||
case FGA_ICRLOCAL4 : LOG(("FGA_ICRLOCAL4 - not implemented\n")); m_fga002[FGA_ICRLOCAL4] = data; break;
|
||||
case FGA_ICRLOCAL5 : LOG(("FGA_ICRLOCAL5 - not implemented\n")); m_fga002[FGA_ICRLOCAL5] = data; break;
|
||||
case FGA_ICRLOCAL6 : LOG(("FGA_ICRLOCAL6 - not implemented\n")); m_fga002[FGA_ICRLOCAL6] = data; break;
|
||||
case FGA_ICRLOCAL7 : LOG(("FGA_ICRLOCAL7 - not implemented\n")); m_fga002[FGA_ICRLOCAL7] = data; break;
|
||||
case FGA_ENAMCODE : LOG(("FGA_ENAMCODE - not implemented\n")); m_fga002[FGA_ENAMCODE] = data; break;
|
||||
case FGA_CTL10 : LOG(("FGA_CTL10 - not implemented\n")); m_fga002[FGA_CTL10] = data; break;
|
||||
case FGA_CTL11 : LOG(("FGA_CTL11 - not implemented\n")); m_fga002[FGA_CTL11] = data; break;
|
||||
case FGA_MAINUM : LOG(("FGA_MAINUM - not implemented\n")); m_fga002[FGA_MAINUM] = data; break;
|
||||
case FGA_MAINUU : LOG(("FGA_MAINUU - not implemented\n")); m_fga002[FGA_MAINUU] = data; break;
|
||||
case FGA_BOTTOMPAGEU : LOG(("FGA_BOTTOMPAGEU - not implemented\n")); m_fga002[FGA_BOTTOMPAGEU] = data; break;
|
||||
case FGA_BOTTOMPAGEL : LOG(("FGA_BOTTOMPAGEL - not implemented\n")); m_fga002[FGA_BOTTOMPAGEL] = data; break;
|
||||
case FGA_TOPPAGEU : LOG(("FGA_TOPPAGEU - not implemented\n")); m_fga002[FGA_TOPPAGEU] = data; break;
|
||||
case FGA_TOPPAGEL : LOG(("FGA_TOPPAGEL - not implemented\n")); m_fga002[FGA_TOPPAGEL] = data; break;
|
||||
case FGA_MYVMEPAGE : LOG(("FGA_MYVMEPAGE - not implemented\n")); m_fga002[FGA_MYVMEPAGE] = data; break;
|
||||
case FGA_TIM0PRELOAD : LOG(("FGA_TIM0PRELOAD - not implemented\n")); m_fga002[FGA_TIM0PRELOAD] = data; break;
|
||||
case FGA_TIM0CTL : LOG(("FGA_TIM0CTL - not implemented\n")); m_fga002[FGA_TIM0CTL] = data; break;
|
||||
case FGA_DMASRCATT : LOG(("FGA_DMASRCATT - not implemented\n")); m_fga002[FGA_DMASRCATT] = data; break;
|
||||
case FGA_DMADSTATT : LOG(("FGA_DMADSTATT - not implemented\n")); m_fga002[FGA_DMADSTATT] = data; break;
|
||||
case FGA_DMA_GENERAL : LOG(("FGA_DMA_GENERAL - not implemented\n")); m_fga002[FGA_DMA_GENERAL] = data; break;
|
||||
case FGA_CTL12 : LOG(("FGA_CTL12 - not implemented\n")); m_fga002[FGA_CTL12] = data; break;
|
||||
case FGA_LIOTIMING : LOG(("FGA_LIOTIMING - not implemented\n")); m_fga002[FGA_LIOTIMING] = data; break;
|
||||
case FGA_LOCALIACK : LOG(("FGA_LOCALIACK - not implemented\n")); m_fga002[FGA_LOCALIACK] = data; break;
|
||||
case FGA_FMBCTL : LOG(("FGA_FMBCTL - not implemented\n")); m_fga002[FGA_FMBCTL] = data; break;
|
||||
case FGA_FMBAREA : LOG(("FGA_FMBAREA - not implemented\n")); m_fga002[FGA_FMBAREA] = data; break;
|
||||
case FGA_AUXSRCSTART : LOG(("FGA_AUXSRCSTART - not implemented\n")); m_fga002[FGA_AUXSRCSTART] = data; break;
|
||||
case FGA_AUXDSTSTART : LOG(("FGA_AUXDSTSTART - not implemented\n")); m_fga002[FGA_AUXDSTSTART] = data; break;
|
||||
case FGA_AUXSRCTERM : LOG(("FGA_AUXSRCTERM - not implemented\n")); m_fga002[FGA_AUXSRCTERM] = data; break;
|
||||
case FGA_AUXDSTTERM : LOG(("FGA_AUXDSTTERM - not implemented\n")); m_fga002[FGA_AUXDSTTERM] = data; break;
|
||||
case FGA_CTL13 : LOG(("FGA_CTL13 - not implemented\n")); m_fga002[FGA_CTL13] = data; break;
|
||||
case FGA_CTL14 : LOG(("FGA_CTL14 - not implemented\n")); m_fga002[FGA_CTL14] = data; break;
|
||||
case FGA_CTL15 : LOG(("FGA_CTL15 - not implemented\n")); m_fga002[FGA_CTL15] = data; break;
|
||||
case FGA_CTL16 : LOG(("FGA_CTL16 - not implemented\n")); m_fga002[FGA_CTL16] = data; break;
|
||||
case FGA_ISTIM0 : LOG(("FGA_ISTIM0 - not implemented\n")); m_fga002[FGA_ISTIM0] = data; break;
|
||||
case FGA_ISDMANORM : LOG(("FGA_ISDMANORM - not implemented\n")); m_fga002[FGA_ISDMANORM] = data; break;
|
||||
case FGA_ISDMAERR : LOG(("FGA_ISDMAERR - not implemented\n")); m_fga002[FGA_ISDMAERR] = data; break;
|
||||
case FGA_ISFMB0REF : LOG(("FGA_ISFMB0REF - not implemented\n")); m_fga002[FGA_ISFMB0REF] = data; break;
|
||||
case FGA_ISFMB1REF : LOG(("FGA_ISFMB1REF - not implemented\n")); m_fga002[FGA_ISFMB1REF] = data; break;
|
||||
case FGA_ISPARITY : LOG(("FGA_ISPARITY - not implemented\n")); m_fga002[FGA_ISPARITY] = data; break;
|
||||
case FGA_DMARUNCTL : LOG(("FGA_DMARUNCTL - not implemented\n")); m_fga002[FGA_DMARUNCTL] = data; break;
|
||||
case FGA_ISABORT : LOG(("FGA_ISABORT - not implemented\n")); m_fga002[FGA_ISABORT] = data; break;
|
||||
case FGA_ISFMB0MES : LOG(("FGA_ISFMB0MES - not implemented\n")); m_fga002[FGA_ISFMB0MES] = data; break;
|
||||
case FGA_ISFMB1MES : LOG(("FGA_ISFMB1MES - not implemented\n")); m_fga002[FGA_ISFMB1MES] = data; break;
|
||||
case FGA_ABORTPIN : LOG(("FGA_ABORTPIN - not implemented\n")); m_fga002[FGA_ABORTPIN] = data; break;
|
||||
default:
|
||||
LOG(("Unsupported register %04x\n", offset));
|
||||
}
|
||||
}
|
||||
|
||||
READ8_MEMBER (fccpu30_state::fga8_r){
|
||||
UINT8 ret = 0;
|
||||
|
||||
LOG(("%s[%04x] ", FUNCNAME, offset));
|
||||
switch(offset)
|
||||
{
|
||||
case FGA_SPECIALENA : ret = m_fga002[FGA_SPECIALENA]; LOG(("FGA_SPECIALENA returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSVMECALL : ret = m_fga002[FGA_RSVMECALL]; LOG(("FGA_RSVMECALL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSKEYRES : ret = m_fga002[FGA_RSKEYRES]; LOG(("FGA_RSKEYRES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSCPUCALL : ret = m_fga002[FGA_RSCPUCALL]; LOG(("FGA_RSCPUCALL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_RSLOCSW : ret = m_fga002[FGA_RSLOCSW]; LOG(("FGA_RSLOCSW returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX0 : ret = m_fga002[FGA_ICRMBOX0]; LOG(("FGA_ICRMBOX0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX1 : ret = m_fga002[FGA_ICRMBOX1]; LOG(("FGA_ICRMBOX1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX2 : ret = m_fga002[FGA_ICRMBOX2]; LOG(("FGA_ICRMBOX2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX3 : ret = m_fga002[FGA_ICRMBOX3]; LOG(("FGA_ICRMBOX3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX4 : ret = m_fga002[FGA_ICRMBOX4]; LOG(("FGA_ICRMBOX4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX5 : ret = m_fga002[FGA_ICRMBOX5]; LOG(("FGA_ICRMBOX5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX6 : ret = m_fga002[FGA_ICRMBOX6]; LOG(("FGA_ICRMBOX6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRMBOX7 : ret = m_fga002[FGA_ICRMBOX7]; LOG(("FGA_ICRMBOX7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_VMEPAGE : ret = m_fga002[FGA_VMEPAGE]; LOG(("FGA_VMEPAGE returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME1 : ret = m_fga002[FGA_ICRVME1]; LOG(("FGA_ICRVME1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME2 : ret = m_fga002[FGA_ICRVME2]; LOG(("FGA_ICRVME2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME3 : ret = m_fga002[FGA_ICRVME3]; LOG(("FGA_ICRVME3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME4 : ret = m_fga002[FGA_ICRVME4]; LOG(("FGA_ICRVME4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME5 : ret = m_fga002[FGA_ICRVME5]; LOG(("FGA_ICRVME5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME6 : ret = m_fga002[FGA_ICRVME6]; LOG(("FGA_ICRVME6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRVME7 : ret = m_fga002[FGA_ICRVME7]; LOG(("FGA_ICRVME7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRTIM0 : ret = m_fga002[FGA_ICRTIM0]; LOG(("FGA_ICRTIM0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRDMANORM : ret = m_fga002[FGA_ICRDMANORM]; LOG(("FGA_ICRDMANORM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRDMAERR : ret = m_fga002[FGA_ICRDMAERR]; LOG(("FGA_ICRDMAERR returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL1 : ret = m_fga002[FGA_CTL1]; LOG(("FGA_CTL1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL2 : ret = m_fga002[FGA_CTL2]; LOG(("FGA_CTL2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB0REF : ret = m_fga002[FGA_ICRFMB0REF]; LOG(("FGA_ICRFMB0REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB1REF : ret = m_fga002[FGA_ICRFMB1REF]; LOG(("FGA_ICRFMB1REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB0MES : ret = m_fga002[FGA_ICRFMB0MES]; LOG(("FGA_ICRFMB0MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRFMB1MES : ret = m_fga002[FGA_ICRFMB1MES]; LOG(("FGA_ICRFMB1MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL3 : ret = m_fga002[FGA_CTL3]; LOG(("FGA_CTL3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL4 : ret = m_fga002[FGA_CTL4]; LOG(("FGA_CTL4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRPARITY : ret = m_fga002[FGA_ICRPARITY]; LOG(("FGA_ICRPARITY returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXPINCTL : ret = m_fga002[FGA_AUXPINCTL]; LOG(("FGA_AUXPINCTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL5 : ret = m_fga002[FGA_CTL5]; LOG(("FGA_CTL5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXFIFWEX : ret = m_fga002[FGA_AUXFIFWEX]; LOG(("FGA_AUXFIFWEX returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXFIFREX : ret = m_fga002[FGA_AUXFIFREX]; LOG(("FGA_AUXFIFREX returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL6 : ret = m_fga002[FGA_CTL6]; LOG(("FGA_CTL6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL7 : ret = m_fga002[FGA_CTL7]; LOG(("FGA_CTL7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL8 : ret = m_fga002[FGA_CTL8]; LOG(("FGA_CTL8 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL9 : ret = m_fga002[FGA_CTL9]; LOG(("FGA_CTL9 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRABORT : ret = m_fga002[FGA_ICRABORT]; LOG(("FGA_ICRABORT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRACFAIL : ret = m_fga002[FGA_ICRACFAIL]; LOG(("FGA_ICRACFAIL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRSYSFAIL : ret = m_fga002[FGA_ICRSYSFAIL]; LOG(("FGA_ICRSYSFAIL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL0 : ret = m_fga002[FGA_ICRLOCAL0]; LOG(("FGA_ICRLOCAL0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL1 : ret = m_fga002[FGA_ICRLOCAL1]; LOG(("FGA_ICRLOCAL1 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL2 : ret = m_fga002[FGA_ICRLOCAL2]; LOG(("FGA_ICRLOCAL2 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL3 : ret = m_fga002[FGA_ICRLOCAL3]; LOG(("FGA_ICRLOCAL3 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL4 : ret = m_fga002[FGA_ICRLOCAL4]; LOG(("FGA_ICRLOCAL4 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL5 : ret = m_fga002[FGA_ICRLOCAL5]; LOG(("FGA_ICRLOCAL5 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL6 : ret = m_fga002[FGA_ICRLOCAL6]; LOG(("FGA_ICRLOCAL6 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ICRLOCAL7 : ret = m_fga002[FGA_ICRLOCAL7]; LOG(("FGA_ICRLOCAL7 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ENAMCODE : ret = m_fga002[FGA_ENAMCODE]; LOG(("FGA_ENAMCODE returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL10 : ret = m_fga002[FGA_CTL10]; LOG(("FGA_CTL10 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL11 : ret = m_fga002[FGA_CTL11]; LOG(("FGA_CTL11 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_MAINUM : ret = m_fga002[FGA_MAINUM]; LOG(("FGA_MAINUM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_MAINUU : ret = m_fga002[FGA_MAINUU]; LOG(("FGA_MAINUU returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_BOTTOMPAGEU : ret = m_fga002[FGA_BOTTOMPAGEU]; LOG(("FGA_BOTTOMPAGEU returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_BOTTOMPAGEL : ret = m_fga002[FGA_BOTTOMPAGEL]; LOG(("FGA_BOTTOMPAGEL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TOPPAGEU : ret = m_fga002[FGA_TOPPAGEU]; LOG(("FGA_TOPPAGEU returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TOPPAGEL : ret = m_fga002[FGA_TOPPAGEL]; LOG(("FGA_TOPPAGEL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_MYVMEPAGE : ret = m_fga002[FGA_MYVMEPAGE]; LOG(("FGA_MYVMEPAGE returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TIM0PRELOAD : ret = m_fga002[FGA_TIM0PRELOAD]; LOG(("FGA_TIM0PRELOAD returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_TIM0CTL : ret = m_fga002[FGA_TIM0CTL]; LOG(("FGA_TIM0CTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMASRCATT : ret = m_fga002[FGA_DMASRCATT]; LOG(("FGA_DMASRCATT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMADSTATT : ret = m_fga002[FGA_DMADSTATT]; LOG(("FGA_DMADSTATT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMA_GENERAL : ret = m_fga002[FGA_DMA_GENERAL]; LOG(("FGA_DMA_GENERAL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL12 : ret = m_fga002[FGA_CTL12]; LOG(("FGA_CTL12 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_LIOTIMING : ret = m_fga002[FGA_LIOTIMING]; LOG(("FGA_LIOTIMING returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_LOCALIACK : ret = m_fga002[FGA_LOCALIACK]; LOG(("FGA_LOCALIACK returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_FMBCTL : ret = m_fga002[FGA_FMBCTL]; LOG(("FGA_FMBCTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_FMBAREA : ret = m_fga002[FGA_FMBAREA]; LOG(("FGA_FMBAREA returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXSRCSTART : ret = m_fga002[FGA_AUXSRCSTART]; LOG(("FGA_AUXSRCSTART returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXDSTSTART : ret = m_fga002[FGA_AUXDSTSTART]; LOG(("FGA_AUXDSTSTART returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXSRCTERM : ret = m_fga002[FGA_AUXSRCTERM]; LOG(("FGA_AUXSRCTERM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_AUXDSTTERM : ret = m_fga002[FGA_AUXDSTTERM]; LOG(("FGA_AUXDSTTERM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL13 : ret = m_fga002[FGA_CTL13]; LOG(("FGA_CTL13 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL14 : ret = m_fga002[FGA_CTL14]; LOG(("FGA_CTL14 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL15 : ret = m_fga002[FGA_CTL15]; LOG(("FGA_CTL15 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_CTL16 : ret = m_fga002[FGA_CTL16]; LOG(("FGA_CTL16 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISTIM0 : ret = m_fga002[FGA_ISTIM0]; LOG(("FGA_ISTIM0 returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISDMANORM : ret = m_fga002[FGA_ISDMANORM]; LOG(("FGA_ISDMANORM returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISDMAERR : ret = m_fga002[FGA_ISDMAERR]; LOG(("FGA_ISDMAERR returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB0REF : ret = m_fga002[FGA_ISFMB0REF]; LOG(("FGA_ISFMB0REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB1REF : ret = m_fga002[FGA_ISFMB1REF]; LOG(("FGA_ISFMB1REF returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISPARITY : ret = m_fga002[FGA_ISPARITY]; LOG(("FGA_ISPARITY returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_DMARUNCTL : ret = m_fga002[FGA_DMARUNCTL]; LOG(("FGA_DMARUNCTL returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISABORT : ret = m_fga002[FGA_ISABORT]; LOG(("FGA_ISABORT returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB0MES : ret = m_fga002[FGA_ISFMB0MES]; LOG(("FGA_ISFMB0MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ISFMB1MES : ret = m_fga002[FGA_ISFMB1MES]; LOG(("FGA_ISFMB1MES returns %02x - not implemented\n", ret)); break;
|
||||
case FGA_ABORTPIN : ret = m_fga002[FGA_ABORTPIN]; LOG(("FGA_ABORTPIN returns %02x - not implemented\n", ret)); break;
|
||||
default:
|
||||
LOG(("Unsupported register %04x\n", offset));
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Rotary Switches - to configure the board
|
||||
*
|
||||
@ -690,7 +352,11 @@ READ8_MEMBER (fccpu30_state::rotary_rd){
|
||||
*/
|
||||
READ8_MEMBER (fccpu30_state::board_mem_id_rd){
|
||||
LOG(("%s\n", FUNCNAME));
|
||||
return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork
|
||||
// return 0x6A; // CPU-30 R4 with 4Mb of shared RAM. TODO: make this configurable from commandline or artwork
|
||||
// return 0x57; // blankt 53 56
|
||||
// return 0x36; // CPU-26 1Mb 36 MHz
|
||||
// return 0x35; // CPU-26 1Mb 36 MHz
|
||||
return 0x36; // CPU-26 1Mb 36 MHz
|
||||
}
|
||||
|
||||
#if 0
|
||||
@ -719,7 +385,7 @@ WRITE16_MEMBER (fccpu30_state::vme_a16_w){
|
||||
*/
|
||||
static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
|
||||
/* basic machine hardware */
|
||||
MCFG_CPU_ADD ("maincpu", M68030, XTAL_16MHz)
|
||||
MCFG_CPU_ADD ("maincpu", M68030, XTAL_25MHz)
|
||||
MCFG_CPU_PROGRAM_MAP (fccpu30_mem)
|
||||
MCFG_NVRAM_ADD_0FILL("nvram")
|
||||
|
||||
@ -733,22 +399,35 @@ static MACHINE_CONFIG_START (fccpu30, fccpu30_state)
|
||||
MCFG_RS232_RXD_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, rxa_w))
|
||||
MCFG_RS232_CTS_HANDLER (DEVWRITELINE ("duscc", duscc68562_device, ctsa_w))
|
||||
|
||||
// MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
|
||||
MCFG_DUSCC68562_ADD("duscc2", DUSCC_CLOCK, 0, 0, 0, 0 )
|
||||
|
||||
/* PIT Parallel Interface and Timer device, assuming strapped for on board clock */
|
||||
MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2)
|
||||
MCFG_DEVICE_ADD ("pit1", PIT68230, XTAL_16MHz / 2) // The PIT clock is not verified on schema but reversed from behaviour
|
||||
MCFG_PIT68230_PA_INPUT_CB(READ8(fccpu30_state, rotary_rd))
|
||||
MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_16MHz / 2)
|
||||
MCFG_DEVICE_ADD ("pit2", PIT68230, XTAL_16MHz / 2) // Th PIT clock is not verified on schema but reversed from behaviour
|
||||
MCFG_PIT68230_PB_INPUT_CB(READ8(fccpu30_state, board_mem_id_rd))
|
||||
|
||||
/* FGA-002, Force Gate Array */
|
||||
MCFG_FGA002_ADD("fga002", 0)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
/* ROM definitions */
|
||||
ROM_START (fccpu30)
|
||||
ROM_REGION32_BE(0x900000, "roms", 0)
|
||||
ROM_LOAD32_BYTE("CPU30UU.bin", 0x000000, 0x20000, CRC(66e95cc2) SHA1(acdb468a3a5974295b81271d617de7f101098891) )
|
||||
ROM_LOAD32_BYTE("CPU30UP.bin", 0x000001, 0x20000, CRC(dfed1f68) SHA1(71478a77d5ab5da0fabcd78e69537919b560e3b8) )
|
||||
ROM_LOAD32_BYTE("CPU30LO.bin", 0x000002, 0x20000, CRC(fefa88ed) SHA1(71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9) )
|
||||
ROM_LOAD32_BYTE("CPU30LL.bin", 0x000003, 0x20000, CRC(a03ebf46) SHA1(48fa0268cb10e20679c093e02574dbd9925f95d1) )
|
||||
|
||||
// Boots with Board ID set to: 0x36
|
||||
ROM_LOAD16_BYTE("CPU33LO.BIN", 0x000001, 0x40000, CRC (49895fdf) SHA1 (733abd144c95225a2faf920490e31df2a27f8e03))
|
||||
ROM_LOAD16_BYTE("CPU33UP.BIN", 0x000000, 0x40000, CRC (cfe75e94) SHA1 (d40e0635a48607be25f7c58c74b53b7e58fe735d))
|
||||
|
||||
// Boots with Board ID set to: 0x36 (no display yet)
|
||||
#if 0
|
||||
ROM_LOAD32_BYTE("CPU30LL.BIN", 0x000003, 0x20000, CRC (a03ebf46) SHA1 (48fa0268cb10e20679c093e02574dbd9925f95d1))
|
||||
ROM_LOAD32_BYTE("CPU30LO.BIN", 0x000002, 0x20000, CRC (fefa88ed) SHA1 (71a9ad807c0c2da5c6f6a6dc68c73ad8b52f3ea9))
|
||||
ROM_LOAD32_BYTE("CPU30UP.BIN", 0x000001, 0x20000, CRC (dfed1f68) SHA1 (71478a77d5ab5da0fabcd78e69537919b560e3b8))
|
||||
ROM_LOAD32_BYTE("CPU30UU.BIN", 0x000000, 0x20000, CRC (66e95cc2) SHA1 (acdb468a3a5974295b81271d617de7f101098891))
|
||||
#endif
|
||||
|
||||
// Same binary for many boards, attempts to detect CPU speed etc, currently failing detection but boots system roms anyway
|
||||
ROM_LOAD ("PGA-002.bin", 0x800000, 0x10000, CRC(faa38972) SHA1(651dfc2f9a865fc6adf49dad90f9e705f2889919) )
|
||||
ROM_END
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user