Changed z80dma to new device interface, updated mario.c and dkong.c to use new interface
* Illustrates how to keep existing memory read/write handlers This is slower than caching the device interface, but does not have an impact on devices accessed at a low frequency like in this case.
This commit is contained in:
Couriersud
parent
75a0723116
commit
e8c24a40d9
@ -86,9 +86,10 @@
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#define READY_ACTIVE_HIGH(_c) ((WR5(_c)>>3) & 0x01)
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struct z80dma
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struct _z80dma_t
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{
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const struct z80dma_interface *intf;
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running_machine *machine;
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const z80dma_interface *intf;
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emu_timer *timer;
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UINT16 regs[REGNUM(6,1)+1];
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@ -109,77 +110,13 @@ struct z80dma
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UINT8 latch;
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};
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static struct z80dma *dma;
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static int dma_count;
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static TIMER_CALLBACK( z80dma_timerproc );
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static void z80dma_update_status(int which);
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static void z80dma_update_status(z80dma_t *z80dma);
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/* ----------------------------------------------------------------------- */
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int z80dma_init(int count)
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static void z80dma_do_read(z80dma_t *cntx)
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{
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int which;
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dma = auto_malloc(count * sizeof(struct z80dma));
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memset(dma, 0, count * sizeof(struct z80dma));
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dma_count = count;
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for (which = 0; which < dma_count; which++)
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{
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dma[which].timer = timer_alloc(z80dma_timerproc, NULL);
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state_save_register_item_array("Z80DMA", which, dma[which].regs);
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state_save_register_item_array("Z80DMA", which, dma[which].regs_follow);
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state_save_register_item("Z80DMA", which, dma[which].num_follow);
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state_save_register_item("Z80DMA", which, dma[which].cur_follow);
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state_save_register_item("Z80DMA", which, dma[which].status);
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state_save_register_item("Z80DMA", which, dma[which].dma_enabled);
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state_save_register_item("Z80DMA", which, dma[which].addressA);
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state_save_register_item("Z80DMA", which, dma[which].addressB);
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state_save_register_item("Z80DMA", which, dma[which].count);
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state_save_register_item("Z80DMA", which, dma[which].rdy);
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state_save_register_item("Z80DMA", which, dma[which].is_read);
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state_save_register_item("Z80DMA", which, dma[which].cur_cycle);
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state_save_register_item("Z80DMA", which, dma[which].latch);
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}
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return 0;
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}
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void z80dma_config(int which, const struct z80dma_interface *intf)
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{
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dma[which].intf = intf;
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}
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void z80dma_reset(void)
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{
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int which;
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for (which = 0; which < dma_count; which++)
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{
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dma[which].status = 0;
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dma[which].rdy = 0;
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dma[which].num_follow = 0;
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dma[which].dma_enabled = 0;
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z80dma_update_status(which);
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}
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}
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/* ----------------------------------------------------------------------- */
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static void z80dma_do_read(int which)
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{
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struct z80dma *cntx = &dma[which];
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UINT8 mode;
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mode = TRANSFER_MODE(cntx);
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@ -188,17 +125,17 @@ static void z80dma_do_read(int which)
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if (PORTA_IS_SOURCE(cntx))
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{
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if (PORTA_MEMORY(cntx))
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cntx->latch = cntx->intf->memory_read_func(cntx->addressA);
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cntx->latch = cntx->intf->memory_read(cntx->machine, cntx, cntx->addressA);
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else
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cntx->latch = cntx->intf->portA_read_func(cntx->addressA);
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cntx->latch = cntx->intf->portA_read(cntx->machine, cntx, cntx->addressA);
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cntx->addressA += PORTA_STEP(cntx);
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}
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else
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{
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if (PORTB_MEMORY(cntx))
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cntx->latch = cntx->intf->memory_read_func(cntx->addressB);
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cntx->latch = cntx->intf->memory_read(cntx->machine, cntx, cntx->addressB);
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else
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cntx->latch = cntx->intf->portB_read_func(cntx->addressB);
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cntx->latch = cntx->intf->portB_read(cntx->machine, cntx, cntx->addressB);
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cntx->addressB += PORTB_STEP(cntx);
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}
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break;
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@ -209,9 +146,8 @@ static void z80dma_do_read(int which)
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}
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}
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static int z80dma_do_write(int which)
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static int z80dma_do_write(z80dma_t *cntx)
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{
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struct z80dma *cntx = &dma[which];
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int done;
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UINT8 mode;
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@ -225,17 +161,17 @@ static int z80dma_do_write(int which)
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if (PORTA_IS_SOURCE(cntx))
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{
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if (PORTB_MEMORY(cntx))
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cntx->intf->memory_write_func(cntx->addressB, cntx->latch);
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cntx->intf->memory_write(cntx->machine, cntx, cntx->addressB, cntx->latch);
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else
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cntx->intf->portB_write_func(cntx->addressB, cntx->latch);
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cntx->intf->portB_write(cntx->machine, cntx, cntx->addressB, cntx->latch);
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cntx->addressB += PORTB_STEP(cntx);
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}
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else
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{
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if (PORTA_MEMORY(cntx))
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cntx->intf->memory_write_func(cntx->addressA, cntx->latch);
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cntx->intf->memory_write(cntx->machine, cntx, cntx->addressA, cntx->latch);
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else
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cntx->intf->portB_write_func(cntx->addressA, cntx->latch);
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cntx->intf->portB_write(cntx->machine, cntx, cntx->addressA, cntx->latch);
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cntx->addressA += PORTA_STEP(cntx);
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}
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cntx->count--;
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@ -255,8 +191,7 @@ static int z80dma_do_write(int which)
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static TIMER_CALLBACK( z80dma_timerproc )
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{
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int which = param;
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struct z80dma *cntx = &dma[which];
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z80dma_t *cntx = ptr;
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int done;
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if (--cntx->cur_cycle)
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@ -265,62 +200,61 @@ static TIMER_CALLBACK( z80dma_timerproc )
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}
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if (cntx->is_read)
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{
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z80dma_do_read(which);
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z80dma_do_read(cntx);
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done = 0;
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cntx->is_read = 0;
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cntx->cur_cycle = (PORTA_IS_SOURCE(cntx) ? PORTA_CYCLE_LEN(cntx) : PORTB_CYCLE_LEN(cntx));
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}
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else
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{
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done = z80dma_do_write(which);
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done = z80dma_do_write(cntx);
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cntx->is_read = 1;
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cntx->cur_cycle = (PORTB_IS_SOURCE(cntx) ? PORTA_CYCLE_LEN(cntx) : PORTB_CYCLE_LEN(cntx));
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}
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if (done)
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{
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cntx->dma_enabled = 0; //FIXME: Correct?
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z80dma_update_status(which);
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z80dma_update_status(cntx);
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}
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}
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static void z80dma_update_status(int which)
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static void z80dma_update_status(z80dma_t *z80dma)
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{
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struct z80dma *cntx = &dma[which];
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UINT16 pending_transfer;
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attotime next;
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/* no transfer is active right now; is there a transfer pending right now? */
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pending_transfer = dma[which].rdy & dma[which].dma_enabled;
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pending_transfer = z80dma->rdy & z80dma->dma_enabled;
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if (pending_transfer)
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{
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dma[which].is_read = 1;
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dma[which].cur_cycle = (PORTA_IS_SOURCE(cntx) ? PORTA_CYCLE_LEN(cntx) : PORTB_CYCLE_LEN(cntx));
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next = ATTOTIME_IN_HZ(dma[which].intf->clockhz);
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timer_adjust_periodic(dma[which].timer,
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z80dma->is_read = 1;
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z80dma->cur_cycle = (PORTA_IS_SOURCE(z80dma) ? PORTA_CYCLE_LEN(z80dma) : PORTB_CYCLE_LEN(z80dma));
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next = ATTOTIME_IN_HZ(z80dma->intf->clockhz);
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timer_adjust_periodic(z80dma->timer,
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attotime_zero,
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which,
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0,
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/* 1 byte transferred in 4 clock cycles */
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next);
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}
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else
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{
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/* no transfers active right now */
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timer_reset(dma[which].timer, attotime_never);
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timer_reset(z80dma->timer, attotime_never);
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}
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/* set the halt line */
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if (dma[which].intf && dma[which].intf->cpunum >= 0)
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if (z80dma->intf && z80dma->intf->cpunum >= 0)
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{
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//FIXME: Synchronization is done by BUSREQ!
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cpunum_set_input_line(Machine, dma[which].intf->cpunum, INPUT_LINE_HALT,
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cpunum_set_input_line(Machine, z80dma->intf->cpunum, INPUT_LINE_HALT,
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pending_transfer ? ASSERT_LINE : CLEAR_LINE);
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}
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}
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/* ----------------------------------------------------------------------- */
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static UINT8 z80dma_read(int which, offs_t offset)
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UINT8 z80dma_read(z80dma_t *z80dma)
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{
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fatalerror("z80dma_read: not implemented");
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return 0;
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@ -328,9 +262,9 @@ static UINT8 z80dma_read(int which, offs_t offset)
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static void z80dma_write(int which, offs_t offset, UINT8 data)
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void z80dma_write(z80dma_t *z80dma, UINT8 data)
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{
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struct z80dma *cntx = &dma[which];
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z80dma_t *cntx = z80dma;
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if (cntx->num_follow == 0)
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{
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@ -406,11 +340,11 @@ static void z80dma_write(int which, offs_t offset, UINT8 data)
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break;
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case 0x83: /* Disable dma */
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cntx->dma_enabled = 0;
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z80dma_rdy_write(which, cntx->rdy);
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z80dma_rdy_write(cntx, cntx->rdy);
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break;
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case 0x87: /* Enable dma */
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cntx->dma_enabled = 1;
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z80dma_rdy_write(which, cntx->rdy);
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z80dma_rdy_write(cntx, cntx->rdy);
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break;
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case 0xBB:
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cntx->regs_follow[cntx->num_follow++] = GET_REGNUM(cntx, READ_MASK(cntx));
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@ -446,50 +380,156 @@ static void z80dma_write(int which, offs_t offset, UINT8 data)
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static TIMER_CALLBACK( z80dma_rdy_write_callback )
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{
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int which = param >> 1;
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int state = param & 0x01;
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struct z80dma *cntx = &dma[which];
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z80dma_t *cntx = ptr;
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/* normalize state */
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cntx->rdy = 1 ^ state ^ READY_ACTIVE_HIGH(cntx);
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cntx->status = (cntx->status & 0xFD) | (cntx->rdy<<1);
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z80dma_update_status(which);
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z80dma_update_status(cntx);
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}
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void z80dma_rdy_write(int which, int state)
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void z80dma_rdy_write(z80dma_t *z80dma, int state)
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{
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int param;
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param = (which << 1) | (state ? 1 : 0);
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LOG(("RDY: %d Active High: %d\n", state, READY_ACTIVE_HIGH(&dma[which])));
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timer_call_after_resynch(NULL, param, z80dma_rdy_write_callback);
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param = (state ? 1 : 0);
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LOG(("RDY: %d Active High: %d\n", state, READY_ACTIVE_HIGH(z80dma)));
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timer_call_after_resynch(z80dma, param, z80dma_rdy_write_callback);
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}
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/* ----------------------------------------------------------------------- */
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/* device interface */
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static DEVICE_START( z80dma )
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{
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z80dma_t *z80dma;
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char unique_tag[30];
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/* validate arguments */
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assert(machine != NULL);
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assert(tag != NULL);
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assert(strlen(tag) < 20);
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/* allocate the object that holds the state */
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z80dma = auto_malloc(sizeof(*z80dma));
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memset(z80dma, 0, sizeof(*z80dma));
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//z80dma->device_type = device_type;
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z80dma->machine = machine;
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z80dma->intf = static_config;
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z80dma->timer = timer_alloc(z80dma_timerproc, z80dma);
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state_save_combine_module_and_tag(unique_tag, "z80dma", tag);
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state_save_register_item_array(unique_tag, 0, z80dma->regs);
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state_save_register_item_array(unique_tag, 0, z80dma->regs_follow);
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state_save_register_item(unique_tag, 0, z80dma->num_follow);
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state_save_register_item(unique_tag, 0, z80dma->cur_follow);
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state_save_register_item(unique_tag, 0, z80dma->status);
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state_save_register_item(unique_tag, 0, z80dma->dma_enabled);
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state_save_register_item(unique_tag, 0, z80dma->addressA);
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state_save_register_item(unique_tag, 0, z80dma->addressB);
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state_save_register_item(unique_tag, 0, z80dma->count);
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state_save_register_item(unique_tag, 0, z80dma->rdy);
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state_save_register_item(unique_tag, 0, z80dma->is_read);
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state_save_register_item(unique_tag, 0, z80dma->cur_cycle);
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state_save_register_item(unique_tag, 0, z80dma->latch);
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return z80dma;
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}
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static DEVICE_RESET( z80dma )
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{
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z80dma_t *z80dma = token;
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z80dma->status = 0;
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z80dma->rdy = 0;
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z80dma->num_follow = 0;
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z80dma->dma_enabled = 0;
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z80dma_update_status(z80dma);
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}
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/******************* Standard 8-bit/32-bit/64-bit CPU interfaces *******************/
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static DEVICE_SET_INFO( z80dma )
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{
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switch (state)
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{
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/* no parameters to set */
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}
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}
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READ8_HANDLER( z80dma_0_r ) { return z80dma_read(0, offset); }
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READ8_HANDLER( z80dma_1_r ) { return z80dma_read(1, offset); }
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WRITE8_HANDLER( z80dma_0_w ) { z80dma_write(0, offset, data); }
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WRITE8_HANDLER( z80dma_1_w ) { z80dma_write(1, offset, data); }
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WRITE8_HANDLER( z80dma_0_rdy_w ) { z80dma_rdy_write(0, data); }
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WRITE8_HANDLER( z80dma_1_rdy_w ) { z80dma_rdy_write(1, data); }
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DEVICE_GET_INFO( z80dma )
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{
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switch (state)
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{
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/* --- the following bits of info are returned as 64-bit signed integers --- */
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case DEVINFO_INT_INLINE_CONFIG_BYTES: info->i = 0; break;
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case DEVINFO_INT_CLASS: info->i = DEVICE_CLASS_PERIPHERAL; break;
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READ16_HANDLER( z80dma_16le_0_r ) { return read16le_with_read8_handler(z80dma_0_r, offset, mem_mask); }
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READ16_HANDLER( z80dma_16le_1_r ) { return read16le_with_read8_handler(z80dma_1_r, offset, mem_mask); }
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WRITE16_HANDLER( z80dma_16le_0_w ) { write16le_with_write8_handler(z80dma_0_w, offset, data, mem_mask); }
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WRITE16_HANDLER( z80dma_16le_1_w ) { write16le_with_write8_handler(z80dma_1_w, offset, data, mem_mask); }
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/* --- the following bits of info are returned as pointers to data or functions --- */
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case DEVINFO_FCT_SET_INFO: info->set_info = DEVICE_SET_INFO_NAME(z80dma); break;
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case DEVINFO_FCT_START: info->start = DEVICE_START_NAME(z80dma);break;
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case DEVINFO_FCT_STOP: /* Nothing */ break;
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case DEVINFO_FCT_RESET: info->reset = DEVICE_RESET_NAME(z80dma);break;
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READ32_HANDLER( z80dma_32le_0_r ) { return read32le_with_read8_handler(z80dma_0_r, offset, mem_mask); }
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READ32_HANDLER( z80dma_32le_1_r ) { return read32le_with_read8_handler(z80dma_1_r, offset, mem_mask); }
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WRITE32_HANDLER( z80dma_32le_0_w ) { write32le_with_write8_handler(z80dma_0_w, offset, data, mem_mask); }
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WRITE32_HANDLER( z80dma_32le_1_w ) { write32le_with_write8_handler(z80dma_1_w, offset, data, mem_mask); }
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/* --- the following bits of info are returned as NULL-terminated strings --- */
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case DEVINFO_STR_NAME: info->s = "Z80DMA"; break;
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case DEVINFO_STR_FAMILY: info->s = "DMA controllers"; break;
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case DEVINFO_STR_VERSION: info->s = "1.0"; break;
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case DEVINFO_STR_SOURCE_FILE: info->s = __FILE__; break;
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case DEVINFO_STR_CREDITS: info->s = "Copyright Nicola Salmoria and the MAME Team"; break;
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}
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}
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READ64_HANDLER( z80dma_64be_0_r ) { return read64be_with_read8_handler(z80dma_0_r, offset, mem_mask); }
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READ64_HANDLER( z80dma_64be_1_r ) { return read64be_with_read8_handler(z80dma_1_r, offset, mem_mask); }
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WRITE64_HANDLER( z80dma_64be_0_w ) { write64be_with_write8_handler(z80dma_0_w, offset, data, mem_mask); }
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WRITE64_HANDLER( z80dma_64be_1_w ) { write64be_with_write8_handler(z80dma_1_w, offset, data, mem_mask); }
|
||||
/******************* Standard 8-bit CPU interfaces *******************/
|
||||
|
||||
READ8_HANDLER( z80dma_0_r )
|
||||
{
|
||||
z80dma_t *z80dma = devtag_get_token(Machine, Z80DMA, Z80DMA_DEV_0_TAG);
|
||||
|
||||
return z80dma_read(z80dma);
|
||||
}
|
||||
|
||||
READ8_HANDLER( z80dma_1_r )
|
||||
{
|
||||
z80dma_t *z80dma = devtag_get_token(Machine, Z80DMA, Z80DMA_DEV_1_TAG);
|
||||
|
||||
return z80dma_read(z80dma);
|
||||
}
|
||||
|
||||
WRITE8_HANDLER( z80dma_0_w )
|
||||
{
|
||||
z80dma_t *z80dma = devtag_get_token(Machine, Z80DMA, Z80DMA_DEV_0_TAG);
|
||||
|
||||
z80dma_write(z80dma, data);
|
||||
}
|
||||
|
||||
WRITE8_HANDLER( z80dma_1_w )
|
||||
{
|
||||
z80dma_t *z80dma = devtag_get_token(Machine, Z80DMA, Z80DMA_DEV_1_TAG);
|
||||
|
||||
z80dma_write(z80dma, data);
|
||||
}
|
||||
|
||||
WRITE8_HANDLER( z80dma_0_rdy_w )
|
||||
{
|
||||
z80dma_t *z80dma = devtag_get_token(Machine, Z80DMA, Z80DMA_DEV_0_TAG);
|
||||
|
||||
z80dma_rdy_write(z80dma, data);
|
||||
}
|
||||
|
||||
WRITE8_HANDLER( z80dma_1_rdy_w )
|
||||
{
|
||||
z80dma_t *z80dma = devtag_get_token(Machine, Z80DMA, Z80DMA_DEV_1_TAG);
|
||||
|
||||
z80dma_rdy_write(z80dma, data);
|
||||
}
|
||||
|
||||
@ -7,7 +7,18 @@
|
||||
#ifndef Z80DMA_H
|
||||
#define Z80DMA_H
|
||||
|
||||
struct z80dma_interface
|
||||
typedef struct _z80dma_t z80dma_t;
|
||||
typedef struct _z80dma_interface z80dma_interface;
|
||||
|
||||
#define Z80DMA DEVICE_GET_INFO_NAME(z80dma)
|
||||
|
||||
typedef UINT8 (*z80dma_read_func)(running_machine *machine, z80dma_t *z80dma, offs_t offset);
|
||||
#define Z80DMA_READ(name) UINT8 name(running_machine *machine, z80dma_t *z80dma, offs_t offset)
|
||||
|
||||
typedef void (*z80dma_write_func)(running_machine *machine, z80dma_t *z80dma, offs_t offset, UINT8 data);
|
||||
#define Z80DMA_WRITE(name) void name(running_machine *machine, z80dma_t *z80dma, offs_t offset, UINT8 data)
|
||||
|
||||
struct _z80dma_interface
|
||||
{
|
||||
/* CPU to halt when DMA is active */
|
||||
int cpunum;
|
||||
@ -16,46 +27,38 @@ struct z80dma_interface
|
||||
int clockhz;
|
||||
|
||||
/* accessors to main memory */
|
||||
UINT8 (*memory_read_func)(offs_t offset);
|
||||
void (*memory_write_func)(offs_t offset, UINT8 data);
|
||||
z80dma_read_func memory_read;
|
||||
z80dma_write_func memory_write;
|
||||
|
||||
/* port accesors */
|
||||
UINT8 (*portA_read_func)(UINT16 addr);
|
||||
void (*portA_write_func)(UINT16 addr, UINT8 data);
|
||||
UINT8 (*portB_read_func)(UINT16 addr);
|
||||
void (*portB_write_func)(UINT16 addr, UINT8 data);
|
||||
z80dma_read_func portA_read;
|
||||
z80dma_write_func portA_write;
|
||||
z80dma_read_func portB_read;
|
||||
z80dma_write_func portB_write;
|
||||
|
||||
/* interrupt callback - not implemented */
|
||||
/* void (*irqcb)(int state); */
|
||||
};
|
||||
|
||||
int z80dma_init(int count);
|
||||
void z80dma_config(int which, const struct z80dma_interface *intf);
|
||||
void z80dma_reset(void);
|
||||
/* device interface */
|
||||
DEVICE_GET_INFO( z80dma );
|
||||
|
||||
void z80dma_rdy_write(int which, int state);
|
||||
void z80dma_rdy_write( z80dma_t *z80dma, int state);
|
||||
UINT8 z80dma_read( z80dma_t *z80dma);
|
||||
void z80dma_write( z80dma_t *z80dma, UINT8 data);
|
||||
|
||||
/******************* Standard 8-bit CPU interfaces *******************/
|
||||
|
||||
#define Z80DMA_DEV_0_TAG "z80dma0"
|
||||
|
||||
READ8_HANDLER(z80dma_0_r);
|
||||
READ8_HANDLER(z80dma_1_r);
|
||||
WRITE8_HANDLER(z80dma_0_w);
|
||||
WRITE8_HANDLER(z80dma_1_w);
|
||||
|
||||
WRITE8_HANDLER(z80dma_0_rdy_w);
|
||||
WRITE8_HANDLER(z80dma_0_w);
|
||||
|
||||
#define Z80DMA_DEV_1_TAG "z80dma1"
|
||||
|
||||
READ8_HANDLER(z80dma_1_r);
|
||||
WRITE8_HANDLER(z80dma_1_w);
|
||||
WRITE8_HANDLER(z80dma_1_rdy_w);
|
||||
|
||||
READ16_HANDLER(z80dma_16le_0_r);
|
||||
READ16_HANDLER(z80dma_16le_1_r);
|
||||
WRITE16_HANDLER(z80dma_16le_0_w);
|
||||
WRITE16_HANDLER(z80dma_16le_1_w);
|
||||
|
||||
READ32_HANDLER(z80dma_32le_0_r);
|
||||
READ32_HANDLER(z80dma_32le_1_r);
|
||||
WRITE32_HANDLER(z80dma_32le_0_w);
|
||||
WRITE32_HANDLER(z80dma_32le_1_w);
|
||||
|
||||
READ64_HANDLER(z80dma_64be_0_r);
|
||||
READ64_HANDLER(z80dma_64be_1_r);
|
||||
WRITE64_HANDLER(z80dma_64be_0_w);
|
||||
WRITE64_HANDLER(z80dma_64be_1_w);
|
||||
|
||||
#endif /* Z80_H */
|
||||
|
||||
@ -278,8 +278,8 @@ static UINT8 hb_dma_read_byte(int channel, offs_t offset);
|
||||
static void hb_dma_write_byte(int channel, offs_t offset, UINT8 data);
|
||||
static UINT8 dk_dma_read_byte(int channel, offs_t offset);
|
||||
static void dk_dma_write_byte(int channel, offs_t offset, UINT8 data);
|
||||
static UINT8 dk3_dma_read_byte(offs_t offset);
|
||||
static void dk3_dma_write_byte(offs_t offset, UINT8 data);
|
||||
static Z80DMA_READ(dk3_dma_read_byte);
|
||||
static Z80DMA_WRITE(dk3_dma_write_byte);
|
||||
static UINT8 p8257_ctl_r(void);
|
||||
static void p8257_ctl_w(UINT8 data);
|
||||
|
||||
@ -289,7 +289,7 @@ static void p8257_ctl_w(UINT8 data);
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static const struct z80dma_interface dk3_dma =
|
||||
static z80dma_interface dk3_dma =
|
||||
{
|
||||
0,
|
||||
CLOCK_1H,
|
||||
@ -395,23 +395,14 @@ static MACHINE_START( radarsc1 )
|
||||
|
||||
static MACHINE_START( dkong3 )
|
||||
{
|
||||
MACHINE_START_CALL(dkong2b);
|
||||
z80dma_init(1);
|
||||
z80dma_config(0, &dk3_dma);
|
||||
dkong_state *state = machine->driver_data;
|
||||
|
||||
state->hardware_type = HARDWARE_TKG04;
|
||||
}
|
||||
|
||||
static MACHINE_RESET( dkong )
|
||||
{
|
||||
|
||||
dma8257_reset();
|
||||
|
||||
}
|
||||
|
||||
static MACHINE_RESET( dkong3 )
|
||||
{
|
||||
|
||||
z80dma_reset();
|
||||
|
||||
}
|
||||
|
||||
static MACHINE_RESET( strtheat )
|
||||
@ -464,7 +455,7 @@ static void dk_dma_write_byte(int channel, offs_t offset, UINT8 data)
|
||||
cpuintrf_pop_context();
|
||||
}
|
||||
|
||||
static UINT8 dk3_dma_read_byte(offs_t offset)
|
||||
static Z80DMA_READ( dk3_dma_read_byte )
|
||||
{
|
||||
UINT8 result;
|
||||
|
||||
@ -475,7 +466,7 @@ static UINT8 dk3_dma_read_byte(offs_t offset)
|
||||
return result;
|
||||
}
|
||||
|
||||
static void dk3_dma_write_byte(offs_t offset, UINT8 data)
|
||||
static Z80DMA_WRITE( dk3_dma_write_byte )
|
||||
{
|
||||
cpuintrf_push_context(0);
|
||||
program_write_byte(offset, data);
|
||||
@ -1643,7 +1634,9 @@ static MACHINE_DRIVER_START( dkong3 )
|
||||
MDRV_CPU_VBLANK_INT("main", nmi_line_pulse)
|
||||
|
||||
MDRV_MACHINE_START(dkong3)
|
||||
MDRV_MACHINE_RESET(dkong3)
|
||||
|
||||
MDRV_DEVICE_ADD(Z80DMA_DEV_0_TAG, Z80DMA)
|
||||
MDRV_DEVICE_CONFIG(dk3_dma)
|
||||
|
||||
/* video hardware */
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
|
||||
@ -95,8 +95,8 @@ write:
|
||||
|
||||
#include "mario.h"
|
||||
|
||||
static UINT8 mario_dma_read_byte(offs_t offset);
|
||||
static void mario_dma_write_byte(offs_t offset, UINT8 data);
|
||||
static Z80DMA_READ(mario_dma_read_byte);
|
||||
static Z80DMA_WRITE(mario_dma_write_byte);
|
||||
|
||||
/*************************************
|
||||
*
|
||||
@ -104,7 +104,7 @@ static void mario_dma_write_byte(offs_t offset, UINT8 data);
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static const struct z80dma_interface mario_dma =
|
||||
static const z80dma_interface mario_dma =
|
||||
{
|
||||
0,
|
||||
Z80_CLOCK,
|
||||
@ -120,24 +120,13 @@ static const struct z80dma_interface mario_dma =
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static MACHINE_START( mario )
|
||||
{
|
||||
z80dma_init(1);
|
||||
z80dma_config(0, &mario_dma);
|
||||
}
|
||||
|
||||
static MACHINE_RESET( mario )
|
||||
{
|
||||
z80dma_reset();
|
||||
}
|
||||
|
||||
/*************************************
|
||||
*
|
||||
* DMA handling
|
||||
*
|
||||
*************************************/
|
||||
|
||||
static UINT8 mario_dma_read_byte(offs_t offset)
|
||||
static Z80DMA_READ(mario_dma_read_byte)
|
||||
{
|
||||
UINT8 result;
|
||||
|
||||
@ -148,7 +137,7 @@ static UINT8 mario_dma_read_byte(offs_t offset)
|
||||
return result;
|
||||
}
|
||||
|
||||
static void mario_dma_write_byte(offs_t offset, UINT8 data)
|
||||
static Z80DMA_WRITE(mario_dma_write_byte)
|
||||
{
|
||||
cpuintrf_push_context(0);
|
||||
program_write_byte(offset, data);
|
||||
@ -363,8 +352,9 @@ static MACHINE_DRIVER_START( mario_base )
|
||||
MDRV_CPU_IO_MAP(0,mario_writeport)
|
||||
MDRV_CPU_VBLANK_INT("main", nmi_line_pulse)
|
||||
|
||||
MDRV_MACHINE_START(mario)
|
||||
MDRV_MACHINE_RESET(mario)
|
||||
/* devices */
|
||||
MDRV_DEVICE_ADD(Z80DMA_DEV_0_TAG, Z80DMA)
|
||||
MDRV_DEVICE_CONFIG(mario_dma)
|
||||
|
||||
/* video hardware */
|
||||
MDRV_SCREEN_ADD("main", RASTER)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user