Basic KRAM hook
This commit is contained in:
Angelo Salese
parent
9b6503ac95
commit
e8f1af1c00
@ -16,6 +16,44 @@
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// device type definition
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const device_type huc6272 = &device_creator<huc6272_device>;
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static ADDRESS_MAP_START( huc6272_vram, AS_0, 16, huc6272_device )
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AM_RANGE(0x000000, 0x0fffff) AM_RAM
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AM_RANGE(0x100000, 0x1fffff) AM_RAM
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ADDRESS_MAP_END
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//-------------------------------------------------
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// memory_space_config - return a description of
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// any address spaces owned by this device
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//-------------------------------------------------
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const address_space_config *huc6272_device::memory_space_config(address_spacenum spacenum) const
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{
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return (spacenum == AS_0) ? &m_space_config : NULL;
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}
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//**************************************************************************
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// INLINE HELPERS
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//**************************************************************************
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//-------------------------------------------------
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// read_dword - read a dword at the given address
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//-------------------------------------------------
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inline UINT32 huc6272_device::read_word(offs_t address)
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{
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return space()->read_word(address << 1);
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}
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//-------------------------------------------------
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// write_dword - write a dword at the given address
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//-------------------------------------------------
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inline void huc6272_device::write_word(offs_t address, UINT32 data)
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{
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space()->write_word(address << 1, data);
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}
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//**************************************************************************
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// LIVE DEVICE
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@ -26,7 +64,9 @@ const device_type huc6272 = &device_creator<huc6272_device>;
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//-------------------------------------------------
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huc6272_device::huc6272_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, huc6272, "huc6272", tag, owner, clock)
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: device_t(mconfig, huc6272, "huc6272", tag, owner, clock),
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device_memory_interface(mconfig, *this),
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m_space_config("videoram", ENDIANNESS_LITTLE, 16, 32, 0, NULL, *ADDRESS_MAP_NAME(huc6272_vram))
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{
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}
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@ -65,11 +105,67 @@ void huc6272_device::device_reset()
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// READ/WRITE HANDLERS
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//**************************************************************************
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READ16_MEMBER( huc6272_device::read )
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READ32_MEMBER( huc6272_device::read )
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{
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return 0;
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UINT32 res = 0;
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if((offset & 1) == 0)
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res = m_register & 0x7f;
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else
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{
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switch(m_register)
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{
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/*
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x--- ---- ---- ---- ----
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*/
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case 0x0c: // KRAM load address
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res = (m_kram_addr_r & 0x3ffff) | ((m_kram_inc_r & 0x1ff) << 18) | ((m_kram_page_r & 1) << 31);
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break;
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case 0x0d: // KRAM write address
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res = (m_kram_addr_w & 0x3ffff) | ((m_kram_inc_w & 0x1ff) << 18) | ((m_kram_page_w & 1) << 31);
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break;
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case 0x0e:
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res = read_word((m_kram_addr_r)|(m_kram_page_r<<18));
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m_kram_addr_r += (m_kram_inc_r & 0x100) ? ((m_kram_inc_r & 0xff) - 0x100) : (m_kram_inc_r & 0xff);
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break;
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//default: printf("%04x\n",m_register);
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}
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}
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return res;
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}
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WRITE16_MEMBER( huc6272_device::write )
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WRITE32_MEMBER( huc6272_device::write )
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{
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if((offset & 1) == 0)
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m_register = data & 0x7f;
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else
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{
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switch(m_register)
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{
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/*
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---- ---- ---- ---- ----
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*/
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case 0x0c: // KRAM load address
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m_kram_addr_r = (data & 0x0003ffff);
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m_kram_inc_r = (data & 0x07fc0000) >> 18;
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m_kram_page_r = (data & 0x80000000) >> 31;
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break;
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case 0x0d: // KRAM write address
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m_kram_addr_w = (data & 0x0003ffff);
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m_kram_inc_w = (data & 0x07fc0000) >> 18;
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m_kram_page_w = (data & 0x80000000) >> 31;
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break;
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case 0x0e: // KRAM write VRAM
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write_word((m_kram_addr_w)|(m_kram_page_w<<18),data & 0xffff); /* TODO: there are some 32-bits accesses during BIOS? */
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m_kram_addr_w += (m_kram_inc_w & 0x100) ? ((m_kram_inc_w & 0xff) - 0x100) : (m_kram_inc_w & 0xff);
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break;
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//default: printf("%04x %04x\n",m_register,data);
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}
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}
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}
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@ -16,7 +16,7 @@ Template for skeleton device
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//**************************************************************************
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#define MCFG_HUC6272_ADD(_tag,_freq) \
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MCFG_DEVICE_ADD(_tag, huc6272, _freq) \
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MCFG_DEVICE_ADD(_tag, huc6272, _freq)
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//**************************************************************************
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@ -25,21 +25,34 @@ Template for skeleton device
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// ======================> huc6272_device
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class huc6272_device : public device_t
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class huc6272_device : public device_t,
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public device_memory_interface
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{
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public:
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// construction/destruction
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huc6272_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// I/O operations
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DECLARE_WRITE16_MEMBER( write );
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DECLARE_READ16_MEMBER( read );
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DECLARE_WRITE32_MEMBER( write );
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DECLARE_READ32_MEMBER( read );
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protected:
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// device-level overrides
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virtual void device_validity_check(validity_checker &valid) const;
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virtual void device_start();
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virtual void device_reset();
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
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private:
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inline UINT32 read_word(offs_t address);
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inline void write_word(offs_t address, UINT32 data);
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UINT8 m_register;
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UINT32 m_kram_addr_r, m_kram_addr_w;
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UINT16 m_kram_inc_r,m_kram_inc_w;
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UINT8 m_kram_page_r,m_kram_page_w;
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const address_space_config m_space_config;
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};
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@ -166,7 +166,7 @@ static ADDRESS_MAP_START( pcfx_io, AS_IO, 32, pcfx_state )
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AM_RANGE( 0x00000300, 0x000003FF ) AM_DEVREADWRITE16( "huc6261", huc6261_device, read, write, 0xffff ) /* HuC6261 */
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AM_RANGE( 0x00000400, 0x000004FF ) AM_DEVREADWRITE8( "huc6270_a", huc6270_device, read, write, 0xffff ) /* HuC6270-A */
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AM_RANGE( 0x00000500, 0x000005FF ) AM_DEVREADWRITE8( "huc6270_b", huc6270_device, read, write, 0xffff ) /* HuC6270-B */
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AM_RANGE( 0x00000600, 0x000006FF ) AM_DEVREADWRITE16( "huc6272", huc6272_device, read, write, 0xffff ) /* HuC6272 */
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AM_RANGE( 0x00000600, 0x000006FF ) AM_DEVREADWRITE( "huc6272", huc6272_device, read, write ) /* HuC6272 */
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AM_RANGE( 0x00000C80, 0x00000C83 ) AM_NOP
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AM_RANGE( 0x00000E00, 0x00000EFF ) AM_READWRITE16( irq_read, irq_write, 0xffff ) /* Interrupt controller */
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AM_RANGE( 0x00000F00, 0x00000FFF ) AM_NOP
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