diff --git a/src/devices/bus/lpci/i82371sb.cpp b/src/devices/bus/lpci/i82371sb.cpp index 4b3744721df..3ea30c60061 100644 --- a/src/devices/bus/lpci/i82371sb.cpp +++ b/src/devices/bus/lpci/i82371sb.cpp @@ -30,6 +30,7 @@ DEFINE_DEVICE_TYPE(I82371SB, i82371sb_device, "i82371sb", "Intel 82371SB") i82371sb_device::i82371sb_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) : southbridge_device(mconfig, I82371SB, tag, owner, clock) , pci_device_interface( mconfig, *this ) + , m_boot_state_hook(*this) { } @@ -147,6 +148,7 @@ void i82371sb_device::pci_write(pci_bus_device *pcibus, int function, int offset void i82371sb_device::device_start() { southbridge_device::device_start(); + m_boot_state_hook.resolve_safe(); /* setup save states */ save_item(NAME(m_regs)); } @@ -179,3 +181,8 @@ void i82371sb_device::device_reset() m_regs[2][0x08] = 0x0c030000; m_regs[2][0x0c] = 0x00000000; } + +void i82371sb_device::port80_debug_write(uint8_t value) +{ + m_boot_state_hook((offs_t)0, value); +} \ No newline at end of file diff --git a/src/devices/bus/lpci/i82371sb.h b/src/devices/bus/lpci/i82371sb.h index c9d71a817b7..e4add02c206 100644 --- a/src/devices/bus/lpci/i82371sb.h +++ b/src/devices/bus/lpci/i82371sb.h @@ -24,6 +24,8 @@ public: // construction/destruction i82371sb_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock); + template static devcb_base &set_boot_state_hook(device_t &device, Object &&cb) { return downcast(device).m_boot_state_hook.set_callback(std::forward(cb)); } + virtual uint32_t pci_read(pci_bus_device *pcibus, int function, int offset, uint32_t mem_mask) override; virtual void pci_write(pci_bus_device *pcibus, int function, int offset, uint32_t data, uint32_t mem_mask) override; @@ -31,6 +33,7 @@ protected: // device-level overrides virtual void device_start() override; virtual void device_reset() override; + virtual void port80_debug_write(uint8_t value) override; uint32_t pci_isa_r(device_t *busdevice, int offset, uint32_t mem_mask); void pci_isa_w(device_t *busdevice, int offset, uint32_t data, uint32_t mem_mask); @@ -42,10 +45,14 @@ protected: void pci_usb_w(device_t *busdevice, int offset, uint32_t data, uint32_t mem_mask); private: uint32_t m_regs[3][0x400/4]; + devcb_write8 m_boot_state_hook; }; // device type definition extern const device_type I82371SB; DECLARE_DEVICE_TYPE(I82371SB, i82371sb_device) +#define MCFG_I82371SB_BOOT_STATE_HOOK(_devcb) \ + devcb = &i82371sb_device::set_boot_state_hook(*device, DEVCB_##_devcb); + #endif // MAME_BUS_LPCI_I82371SB_H diff --git a/src/devices/bus/lpci/i82439tx.cpp b/src/devices/bus/lpci/i82439tx.cpp index b4bebc8e233..39750f7cd7f 100644 --- a/src/devices/bus/lpci/i82439tx.cpp +++ b/src/devices/bus/lpci/i82439tx.cpp @@ -88,6 +88,10 @@ uint32_t i82439tx_device::pci_read(pci_bus_device *pcibus, int function, int off case 0x44: /* reserved */ case 0x48: /* reserved */ case 0x4C: /* reserved */ + logerror("i82439tx_pci_read(): Unemulated PCI read 0x%02X, returning 0\n", offset); + result = 0; + break; + case 0x50: case 0x54: case 0x58: @@ -167,12 +171,47 @@ void i82439tx_device::pci_write(pci_bus_device *pcibus, int function, int offset /* read only */ break; + case 0x58: + if ((mem_mask & 0x0000f000)) + i82439tx_configure_memory(data >> 12, 0xf0000, 0xfffff); + if ((mem_mask & 0x000f0000)) + i82439tx_configure_memory(data >> 16, 0xc0000, 0xc3fff); + if ((mem_mask & 0x00f00000)) + i82439tx_configure_memory(data >> 20, 0xc4000, 0xc7fff); + if ((mem_mask & 0x0f000000)) + i82439tx_configure_memory(data >> 24, 0xc8000, 0xccfff); + if ((mem_mask & 0xf0000000)) + i82439tx_configure_memory(data >> 28, 0xcc000, 0xcffff); + COMBINE_DATA(&m_regs[(offset - 0x50) / 4]); + break; + + case 0x5C: + if ((mem_mask & 0x0000000f)) + i82439tx_configure_memory(data >> 0, 0xd0000, 0xd3fff); + if ((mem_mask & 0x000000f0)) + i82439tx_configure_memory(data >> 4, 0xd4000, 0xd7fff); + if ((mem_mask & 0x00000f00)) + i82439tx_configure_memory(data >> 8, 0xd8000, 0xdbfff); + if ((mem_mask & 0x0000f000)) + i82439tx_configure_memory(data >> 12, 0xdc000, 0xdffff); + if ((mem_mask & 0x000f0000)) + i82439tx_configure_memory(data >> 16, 0xe0000, 0xe3fff); + if ((mem_mask & 0x00f00000)) + i82439tx_configure_memory(data >> 20, 0xe4000, 0xe7fff); + if ((mem_mask & 0x0f000000)) + i82439tx_configure_memory(data >> 24, 0xe8000, 0xecfff); + if ((mem_mask & 0xf0000000)) + i82439tx_configure_memory(data >> 28, 0xec000, 0xeffff); + COMBINE_DATA(&m_regs[(offset - 0x50) / 4]); + break; + case 0x04: /* PCI command register */ case 0x0C: + logerror("i82439tx_pci_write(): Unemulated PCI write 0x%02X = 0x%04X\n", offset, data); + break; + case 0x50: case 0x54: - case 0x58: - case 0x5C: case 0x60: case 0x64: case 0x68: @@ -213,41 +252,6 @@ void i82439tx_device::pci_write(pci_bus_device *pcibus, int function, int offset case 0xF4: case 0xF8: case 0xFC: - switch(offset) - { - case 0x58: - if ((mem_mask & 0x0000f000)) - i82439tx_configure_memory(data >> 12, 0xf0000, 0xfffff); - if ((mem_mask & 0x000f0000)) - i82439tx_configure_memory(data >> 16, 0xc0000, 0xc3fff); - if ((mem_mask & 0x00f00000)) - i82439tx_configure_memory(data >> 20, 0xc4000, 0xc7fff); - if ((mem_mask & 0x0f000000)) - i82439tx_configure_memory(data >> 24, 0xc8000, 0xccfff); - if ((mem_mask & 0xf0000000)) - i82439tx_configure_memory(data >> 28, 0xcc000, 0xcffff); - break; - - case 0x5C: - if ((mem_mask & 0x0000000f)) - i82439tx_configure_memory(data >> 0, 0xd0000, 0xd3fff); - if ((mem_mask & 0x000000f0)) - i82439tx_configure_memory(data >> 4, 0xd4000, 0xd7fff); - if ((mem_mask & 0x00000f00)) - i82439tx_configure_memory(data >> 8, 0xd8000, 0xdbfff); - if ((mem_mask & 0x0000f000)) - i82439tx_configure_memory(data >> 12, 0xdc000, 0xdffff); - if ((mem_mask & 0x000f0000)) - i82439tx_configure_memory(data >> 16, 0xe0000, 0xe3fff); - if ((mem_mask & 0x00f00000)) - i82439tx_configure_memory(data >> 20, 0xe4000, 0xe7fff); - if ((mem_mask & 0x0f000000)) - i82439tx_configure_memory(data >> 24, 0xe8000, 0xecfff); - if ((mem_mask & 0xf0000000)) - i82439tx_configure_memory(data >> 28, 0xec000, 0xeffff); - break; - } - assert(((offset - 0x50) / 4) >= 0 && ((offset - 0x50) / 4) < ARRAY_LENGTH(m_regs)); COMBINE_DATA(&m_regs[(offset - 0x50) / 4]); break; diff --git a/src/devices/bus/lpci/southbridge.cpp b/src/devices/bus/lpci/southbridge.cpp index 969a2b8c71b..70bff510211 100644 --- a/src/devices/bus/lpci/southbridge.cpp +++ b/src/devices/bus/lpci/southbridge.cpp @@ -297,6 +297,8 @@ WRITE8_MEMBER( southbridge_device::at_page8_w ) { m_at_pages[offset % 0x10] = data; + if (offset == 0) + port80_debug_write(data); switch(offset % 8) { case 1: diff --git a/src/devices/bus/lpci/southbridge.h b/src/devices/bus/lpci/southbridge.h index 586a5ae30ca..142fcc0f98b 100644 --- a/src/devices/bus/lpci/southbridge.h +++ b/src/devices/bus/lpci/southbridge.h @@ -50,6 +50,7 @@ protected: // device-level overrides virtual void device_start() override; virtual void device_reset() override; + virtual void port80_debug_write(uint8_t value) {} required_device m_maincpu; required_device m_pic8259_master; diff --git a/src/mame/drivers/atpci.cpp b/src/mame/drivers/atpci.cpp index 7f5f3ea70a7..64311f56053 100644 --- a/src/mame/drivers/atpci.cpp +++ b/src/mame/drivers/atpci.cpp @@ -20,13 +20,23 @@ public: m_maincpu(*this, "maincpu") { } required_device m_maincpu; + DECLARE_WRITE8_MEMBER(boot_state_w); }; +WRITE8_MEMBER(at586_state::boot_state_w) +{ + logerror("Boot state %02x\n", data); +} + static MACHINE_CONFIG_START( tx_config ) MCFG_I82439TX_CPU( "maincpu" ) MCFG_I82439TX_REGION( "isa" ) MACHINE_CONFIG_END +static MACHINE_CONFIG_START(sb_config) + MCFG_I82371SB_BOOT_STATE_HOOK(DEVWRITE8(":", at586_state, boot_state_w)) +MACHINE_CONFIG_END + static SLOT_INTERFACE_START( pci_devices ) SLOT_INTERFACE_INTERNAL("i82439tx", I82439TX) SLOT_INTERFACE_INTERNAL("i82371ab", I82371AB) @@ -85,6 +95,7 @@ static MACHINE_CONFIG_START( at586x3 ) MCFG_SLOT_OPTION_MACHINE_CONFIG("i82439tx", tx_config) MCFG_PCI_BUS_DEVICE("pcibus:1", pci_devices, "i82371sb", true) + MCFG_SLOT_OPTION_MACHINE_CONFIG("i82371sb", sb_config) MCFG_ISA16_SLOT_ADD(":pcibus:1:i82371sb:isabus","isa1", pc_isa16_cards, "svga_et4k", false) MCFG_ISA16_SLOT_ADD(":pcibus:1:i82371sb:isabus","isa2", pc_isa16_cards, nullptr, false) @@ -112,7 +123,11 @@ ROM_END ROM_START( at586x3 ) ROM_REGION32_LE(0x40000, "isa", 0) - ROM_LOAD("5hx29.bin", 0x20000, 0x20000, CRC(07719a55) SHA1(b63993fd5186cdb4f28c117428a507cd069e1f68)) + ROM_SYSTEM_BIOS(0, "5hx29", "5HX29") + ROMX_LOAD("5hx29.bin", 0x20000, 0x20000, CRC(07719a55) SHA1(b63993fd5186cdb4f28c117428a507cd069e1f68), ROM_BIOS(1)) + + ROM_SYSTEM_BIOS(1, "n7ns04", "Version 21/01/98, without integrated sound") // SMSC FDC37C93X I/O + ROMX_LOAD("m7ns04.rom", 0x00000, 0x40000, CRC(9c1f656b) SHA1(f4a0a522d8c47b6ddb6c01fe9a34ddf5b1977f8d), ROM_BIOS(2) ) ROM_END /* FIC VT-503 (Intel TX chipset, ITE 8679 Super I/O) */