mirror of
https://github.com/holub/mame
synced 2025-05-28 08:33:05 +03:00
Added 8/16 bit data bus configuration to TLCS900H. Default is 16bit, neogeo pocket is 8 bit [smf]
This commit is contained in:
smf-
parent
8024829c62
commit
ea27878f48
@ -22,24 +22,32 @@ const device_type TMP95C061 = &device_creator<tmp95c061_device>;
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const device_type TMP95C063 = &device_creator<tmp95c063_device>;
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static ADDRESS_MAP_START( tmp95c061_mem, AS_PROGRAM, 8, tmp95c061_device )
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static ADDRESS_MAP_START( tmp95c061_mem8, AS_PROGRAM, 8, tmp95c061_device )
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AM_RANGE( 0x000000, 0x00007f ) AM_READWRITE( internal_r, internal_w )
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(tmp95c063_mem, AS_PROGRAM, 8, tmp95c063_device )
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AM_RANGE( 0x000000, 0x00009f ) AM_READWRITE( internal_r, internal_w )
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static ADDRESS_MAP_START( tmp95c061_mem16, AS_PROGRAM, 16, tmp95c061_device )
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AM_RANGE( 0x000000, 0x00007f ) AM_READWRITE8( internal_r, internal_w, 0xffff )
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ADDRESS_MAP_END
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tlcs900h_device::tlcs900h_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, address_map_constructor internal_map)
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: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__)
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, m_program_config("program", ENDIANNESS_LITTLE, 8, 24, 0, internal_map)
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static ADDRESS_MAP_START(tmp95c063_mem8, AS_PROGRAM, 8, tmp95c063_device )
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AM_RANGE( 0x000000, 0x00009f ) AM_READWRITE( internal_r, internal_w )
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(tmp95c063_mem16, AS_PROGRAM, 16, tmp95c063_device )
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AM_RANGE( 0x000000, 0x00009f ) AM_READWRITE8( internal_r, internal_w, 0xffff )
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ADDRESS_MAP_END
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tlcs900h_device::tlcs900h_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname)
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: cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__),
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m_am8_16(0)
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{
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}
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tmp95c061_device::tmp95c061_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: tlcs900h_device(mconfig, TMP95C061, "TMP95C061", tag, owner, clock, "tmp95c061", ADDRESS_MAP_NAME(tmp95c061_mem) ),
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: tlcs900h_device(mconfig, TMP95C061, "TMP95C061", tag, owner, clock, "tmp95c061" ),
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m_port1_read(*this),
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m_port1_write(*this),
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m_port2_write(*this),
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@ -59,10 +67,26 @@ tmp95c061_device::tmp95c061_device(const machine_config &mconfig, const char *ta
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{
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}
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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//-------------------------------------------------
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void tmp95c061_device::device_config_complete()
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{
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if (m_am8_16 == 0)
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{
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m_program_config = address_space_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(tmp95c061_mem16));
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}
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else
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{
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m_program_config = address_space_config("program", ENDIANNESS_LITTLE, 8, 24, 0, ADDRESS_MAP_NAME(tmp95c061_mem8));
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}
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}
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tmp95c063_device::tmp95c063_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: tlcs900h_device(mconfig, TMP95C063, "TMP95C063", tag, owner, clock, "tmp95c063", ADDRESS_MAP_NAME(tmp95c063_mem) ),
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: tlcs900h_device(mconfig, TMP95C063, "TMP95C063", tag, owner, clock, "tmp95c063"),
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m_port1_read(*this),
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m_port1_write(*this),
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m_port2_write(*this),
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@ -88,6 +112,24 @@ tmp95c063_device::tmp95c063_device(const machine_config &mconfig, const char *ta
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{
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}
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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//-------------------------------------------------
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void tmp95c063_device::device_config_complete()
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{
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if (m_am8_16 == 0)
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{
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m_program_config = address_space_config("program", ENDIANNESS_LITTLE, 16, 24, 0, ADDRESS_MAP_NAME(tmp95c063_mem16));
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}
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else
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{
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m_program_config = address_space_config("program", ENDIANNESS_LITTLE, 8, 24, 0, ADDRESS_MAP_NAME(tmp95c063_mem8));
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}
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}
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offs_t tlcs900h_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
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{
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@ -215,14 +257,6 @@ offs_t tlcs900h_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8
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#define FLAG_SF 0x80
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#define RDMEM(addr) m_program->read_byte( addr )
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#define WRMEM(addr,data) m_program->write_byte( addr, data )
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#define RDMEMW(addr) ( RDMEM(addr) | ( RDMEM(addr+1) << 8 ) )
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#define RDMEML(addr) ( RDMEMW(addr) | ( RDMEMW(addr+2) << 16 ) )
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#define WRMEMW(addr,data) { UINT16 dw = data; WRMEM(addr,dw & 0xff); WRMEM(addr+1,(dw >> 8 )); }
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#define WRMEML(addr,data) { UINT32 dl = data; WRMEMW(addr,dl); WRMEMW(addr+2,(dl >> 16)); }
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inline UINT8 tlcs900h_device::RDOP()
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{
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UINT8 data;
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@ -1101,7 +1135,7 @@ READ8_MEMBER( tmp95c061_device::internal_r )
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case TMP95C061_P8: m_reg[offset] = m_port8_read(0); break;
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case TMP95C061_P9: m_reg[offset] = m_port9_read(0); break;
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case TMP95C061_PA: m_reg[offset] = m_porta_read(0); break;
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case TMP95C061_PB: m_reg[offset] = m_porta_read(0); break;
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case TMP95C061_PB: m_reg[offset] = m_portb_read(0); break;
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}
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return m_reg[ offset ];
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}
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@ -41,12 +41,17 @@ extern const device_type TMP95C061;
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extern const device_type TMP95C063;
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#define MCFG_TLCS900H_AM8_16( am8_16 ) tlcs900h_device::set_am8_16( *device, am8_16 );
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class tlcs900h_device : public cpu_device
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{
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public:
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// construction/destruction
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tlcs900h_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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tlcs900h_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, address_map_constructor internal_map);
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tlcs900h_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname);
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// static configuration helpers
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static void set_am8_16(device_t &device, int am8_16) { downcast<tlcs900h_device &>(device).m_am8_16 = am8_16; }
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protected:
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// device-level overrides
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@ -73,8 +78,16 @@ protected:
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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protected:
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int m_am8_16;
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address_space_config m_program_config;
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UINT8 RDMEM(offs_t addr) { return m_program->read_byte( addr ); }
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UINT16 RDMEMW(offs_t addr) { return m_program->read_word( addr ); }
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UINT32 RDMEML(offs_t addr) { return m_program->read_dword( addr ); }
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void WRMEM(offs_t addr, UINT8 data) { m_program->write_byte( addr, data ); }
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void WRMEMW(offs_t addr,UINT16 data) { m_program->write_word( addr, data ); }
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void WRMEML(offs_t addr,UINT32 data) { m_program->write_dword( addr, data ); }
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/* registers */
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PAIR m_xwa[4];
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PAIR m_xbc[4];
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@ -645,8 +658,10 @@ public:
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DECLARE_WRITE8_MEMBER( internal_w );
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protected:
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virtual void device_config_complete();
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virtual void device_start();
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virtual void device_reset();
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virtual void execute_set_input(int inputnum, int state);
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virtual void tlcs900_check_hdma();
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virtual void tlcs900_check_irqs();
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@ -762,8 +777,10 @@ public:
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template<class _Object> static devcb2_base &set_porte_write(device_t &device, _Object object) { return downcast<tmp95c063_device &>(device).m_porte_write.set_callback(object); }
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protected:
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virtual void device_config_complete();
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virtual void device_start();
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virtual void device_reset();
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virtual void execute_set_input(int inputnum, int state);
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virtual void tlcs900_check_hdma();
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virtual void tlcs900_check_irqs();
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@ -376,10 +376,10 @@ WRITE8_MEMBER(taitopjc_state::tlcs_sound_w)
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// 0xfc0fb5: INTRX1
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// 0xfc0f41: INTTX1
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static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 8, taitopjc_state )
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static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 16, taitopjc_state )
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AM_RANGE(0x010000, 0x02ffff) AM_RAM // Work RAM
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AM_RANGE(0x040000, 0x0400ff) AM_READWRITE(tlcs_sound_r, tlcs_sound_w)
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AM_RANGE(0x060000, 0x061fff) AM_READWRITE(tlcs_common_r, tlcs_common_w)
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AM_RANGE(0x040000, 0x0400ff) AM_READWRITE8(tlcs_sound_r, tlcs_sound_w, 0xffff)
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AM_RANGE(0x060000, 0x061fff) AM_READWRITE8(tlcs_common_r, tlcs_common_w, 0xffff)
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AM_RANGE(0xfc0000, 0xffffff) AM_ROM AM_REGION("io_cpu", 0)
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ADDRESS_MAP_END
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@ -551,7 +551,7 @@ public:
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required_device<cpu_device> m_maincpu;
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required_device<cpu_device> m_iocpu;
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required_shared_ptr<UINT64> m_work_ram;
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required_shared_ptr<UINT8> m_mbox_ram;
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required_shared_ptr<UINT16> m_mbox_ram;
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required_device<ata_interface_device> m_ata;
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DECLARE_READ64_MEMBER(ppc_common_r);
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@ -608,10 +608,8 @@ public:
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virtual void video_start();
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UINT32 screen_update_taitotz(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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INTERRUPT_GEN_MEMBER(taitotz_vbi);
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DECLARE_READ8_MEMBER(tlcs_ide0_r);
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DECLARE_WRITE8_MEMBER(tlcs_ide0_w);
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DECLARE_READ8_MEMBER(tlcs_ide1_r);
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DECLARE_WRITE8_MEMBER(tlcs_ide1_w);
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DECLARE_READ16_MEMBER(tlcs_ide0_r);
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DECLARE_READ16_MEMBER(tlcs_ide1_r);
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DECLARE_WRITE_LINE_MEMBER(ide_interrupt);
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void taitotz_exit();
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void draw_tile(taitotz_state *state, UINT32 pos, UINT32 tile);
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@ -2304,102 +2302,22 @@ WRITE8_MEMBER(taitotz_state::tlcs_rtc_w)
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}
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}
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READ8_MEMBER(taitotz_state::tlcs_ide0_r)
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READ16_MEMBER(taitotz_state::tlcs_ide0_r)
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{
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int reg = offset >> 1;
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if (reg == 0)
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{
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if ((offset & 1) == 0)
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{
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ide_cs0_latch_r = m_ata->read_cs0(space, reg, 0xffff);
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return (ide_cs0_latch_r & 0xff);
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}
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else
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{
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return (ide_cs0_latch_r >> 8) & 0xff;
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}
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}
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else
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{
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if (offset & 1)
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fatalerror("tlcs_ide0_r: %02X, odd offset\n", offset);
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UINT8 d = m_ata->read_cs0(space, reg, 0xff);
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if (reg == 7)
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d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
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// The status check explicitly checks for 0x50 (drive ready, seek complete).
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return d;
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}
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}
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WRITE8_MEMBER(taitotz_state::tlcs_ide0_w)
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{
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int reg = offset >> 1;
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if (reg == 7 || reg == 0)
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{
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if ((offset & 1) == 0)
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{
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ide_cs0_latch_w &= 0xff00;
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ide_cs0_latch_w |= data;
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}
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else
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{
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ide_cs0_latch_w &= 0x00ff;
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ide_cs0_latch_w |= (UINT16)(data) << 8;
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m_ata->write_cs0(space, reg, ide_cs0_latch_w, 0xffff);
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}
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}
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else
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{
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if (offset & 1)
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fatalerror("tlcs_ide0_w: %02X, %02X, odd offset\n", offset, data);
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m_ata->write_cs0(space, reg, data, 0xff);
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}
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}
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READ8_MEMBER(taitotz_state::tlcs_ide1_r)
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{
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int reg = offset >> 1;
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if (reg != 6)
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fatalerror("tlcs_ide1_r: %02X\n", offset);
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if ((offset & 1) == 0)
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{
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UINT8 d = m_ata->read_cs1(space, reg, 0xff);
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UINT16 d = m_ata->read_cs0(space, offset, mem_mask);
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if (offset == 7)
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d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
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// The status check explicitly checks for 0x50 (drive ready, seek complete).
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return d;
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}
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else
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{
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//fatalerror("tlcs_ide1_r: %02X, odd offset\n", offset);
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UINT8 d = m_ata->read_cs1(space, reg, 0xff);
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d &= ~0x2;
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return d;
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}
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return d;
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}
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WRITE8_MEMBER(taitotz_state::tlcs_ide1_w)
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READ16_MEMBER(taitotz_state::tlcs_ide1_r)
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{
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int reg = offset >> 1;
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if (reg != 6)
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fatalerror("tlcs_ide1_w: %02X, %02X\n", offset, data);
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if ((offset & 1) == 0)
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{
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ide_cs1_latch_w &= 0xff00;
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ide_cs1_latch_w |= data;
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}
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else
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{
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ide_cs1_latch_w &= 0x00ff;
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ide_cs1_latch_w |= (UINT16)(data) << 16;
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m_ata->write_cs1(space, reg, ide_cs1_latch_w, 0xffff);
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}
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UINT16 d = m_ata->read_cs1(space, offset, mem_mask);
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if (offset == 6)
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d &= ~0x2; // Type Zero doesn't like the index bit. It's defined as vendor-specific, so it probably shouldn't be up...
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// The status check explicitly checks for 0x50 (drive ready, seek complete).
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return d;
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}
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// TLCS900 interrupt vectors
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@ -2427,25 +2345,25 @@ WRITE8_MEMBER(taitotz_state::tlcs_ide1_w)
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// 0xfc0d55: INTRX1 Serial 1 receive
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// 0xfc0ce1: INTTX1 Serial 1 transmit
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static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 8, taitotz_state)
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static ADDRESS_MAP_START( tlcs900h_mem, AS_PROGRAM, 16, taitotz_state)
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AM_RANGE(0x010000, 0x02ffff) AM_RAM // Work RAM
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AM_RANGE(0x040000, 0x041fff) AM_RAM AM_SHARE("nvram") // Backup RAM
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AM_RANGE(0x044000, 0x04400f) AM_READWRITE(tlcs_rtc_r, tlcs_rtc_w)
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AM_RANGE(0x060000, 0x061fff) AM_READWRITE(tlcs_common_r, tlcs_common_w)
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AM_RANGE(0x044000, 0x04400f) AM_READWRITE8(tlcs_rtc_r, tlcs_rtc_w, 0xffff)
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AM_RANGE(0x060000, 0x061fff) AM_READWRITE8(tlcs_common_r, tlcs_common_w, 0xffff)
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AM_RANGE(0x064000, 0x064fff) AM_RAM AM_SHARE("mbox_ram") // MBox
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AM_RANGE(0x068000, 0x06800f) AM_READWRITE(tlcs_ide0_r, tlcs_ide0_w)
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AM_RANGE(0x06c000, 0x06c00f) AM_READWRITE(tlcs_ide1_r, tlcs_ide1_w)
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AM_RANGE(0x068000, 0x06800f) AM_DEVWRITE("ata", ata_interface_device, write_cs0) AM_READ(tlcs_ide0_r)
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AM_RANGE(0x06c000, 0x06c00f) AM_DEVWRITE("ata", ata_interface_device, write_cs1) AM_READ(tlcs_ide1_r)
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AM_RANGE(0xfc0000, 0xffffff) AM_ROM AM_REGION("io_cpu", 0)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( landhigh_tlcs900h_mem, AS_PROGRAM, 8, taitotz_state)
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static ADDRESS_MAP_START( landhigh_tlcs900h_mem, AS_PROGRAM, 16, taitotz_state)
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AM_RANGE(0x200000, 0x21ffff) AM_RAM // Work RAM
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AM_RANGE(0x400000, 0x401fff) AM_RAM AM_SHARE("nvram") // Backup RAM
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AM_RANGE(0x404000, 0x40400f) AM_READWRITE(tlcs_rtc_r, tlcs_rtc_w)
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AM_RANGE(0x900000, 0x901fff) AM_READWRITE(tlcs_common_r, tlcs_common_w)
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AM_RANGE(0x404000, 0x40400f) AM_READWRITE8(tlcs_rtc_r, tlcs_rtc_w, 0xffff)
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AM_RANGE(0x900000, 0x901fff) AM_READWRITE8(tlcs_common_r, tlcs_common_w, 0xffff)
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AM_RANGE(0x910000, 0x910fff) AM_RAM AM_SHARE("mbox_ram") // MBox
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AM_RANGE(0x908000, 0x90800f) AM_READWRITE(tlcs_ide0_r, tlcs_ide0_w)
|
||||
AM_RANGE(0x918000, 0x91800f) AM_READWRITE(tlcs_ide1_r, tlcs_ide1_w)
|
||||
AM_RANGE(0x908000, 0x90800f) AM_DEVWRITE("ata", ata_interface_device, write_cs0) AM_READ(tlcs_ide0_r)
|
||||
AM_RANGE(0x918000, 0x91800f) AM_DEVWRITE("ata", ata_interface_device, write_cs1) AM_READ(tlcs_ide1_r)
|
||||
AM_RANGE(0xfc0000, 0xffffff) AM_ROM AM_REGION("io_cpu", 0)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
@ -2758,10 +2676,10 @@ static MACHINE_CONFIG_START( taitotz, taitotz_state )
|
||||
|
||||
/* TMP95C063F I/O CPU */
|
||||
MCFG_CPU_ADD("iocpu", TMP95C063, 25000000)
|
||||
MCFG_TMP95C063_PORT9_READ(IOPORT("INPUTS1"))
|
||||
MCFG_TMP95C063_PORTB_READ(IOPORT("INPUTS2"))
|
||||
MCFG_TMP95C063_PORTD_READ(IOPORT("INPUTS3"))
|
||||
MCFG_TMP95C063_PORTE_READ(IOPORT("INPUTS4"))
|
||||
MCFG_TMP95C063_PORT9_WRITE(IOPORT("INPUTS1"))
|
||||
MCFG_TMP95C063_PORTB_WRITE(IOPORT("INPUTS2"))
|
||||
MCFG_TMP95C063_PORTD_WRITE(IOPORT("INPUTS3"))
|
||||
MCFG_TMP95C063_PORTE_WRITE(IOPORT("INPUTS4"))
|
||||
|
||||
MCFG_CPU_PROGRAM_MAP(tlcs900h_mem)
|
||||
MCFG_CPU_VBLANK_INT_DRIVER("screen", taitotz_state, taitotz_vbi)
|
||||
|
||||
@ -807,6 +807,7 @@ void ngp_state::nvram_write(emu_file &file)
|
||||
static MACHINE_CONFIG_START( ngp_common, ngp_state )
|
||||
|
||||
MCFG_CPU_ADD( "maincpu", TMP95C061, XTAL_6_144MHz )
|
||||
MCFG_TLCS900H_AM8_16(1)
|
||||
MCFG_CPU_PROGRAM_MAP( ngp_mem)
|
||||
MCFG_TMP95C061_PORTA_WRITE(WRITE8(ngp_state,ngp_tlcs900_porta))
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user