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https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
konami cpu dasm: be consistent with uppercase data and reg names, renamed some opcodes
This commit is contained in:
hap
parent
9540dfbff0
commit
ea3118ab93
@ -1150,16 +1150,16 @@ const m6x09_base_disassembler::opcodeinfo konami_disassembler::konami_opcodes[]
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{ 0x2E, 1, "EORA", IND, M6x09_GENERAL },
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{ 0x2F, 1, "EORB", IND, M6x09_GENERAL },
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{ 0x30, 1, "ORA", IMM, M6x09_GENERAL },
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{ 0x31, 1, "ORB", IMM, M6x09_GENERAL },
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{ 0x32, 1, "ORA", IND, M6x09_GENERAL },
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{ 0x33, 1, "ORB", IND, M6x09_GENERAL },
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{ 0x34, 1, "CMPA", IMM, M6x09_GENERAL },
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{ 0x35, 1, "CMPB", IMM, M6x09_GENERAL },
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{ 0x36, 1, "CMPA", IND, M6x09_GENERAL },
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{ 0x37, 1, "CMPB", IND, M6x09_GENERAL },
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{ 0x38, 1, "SETLINES", IMM, M6x09_GENERAL },
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{ 0x39, 1, "SETLINES", IND, M6x09_GENERAL },
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{ 0x30, 1, "ORA", IMM, M6x09_GENERAL },
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{ 0x31, 1, "ORB", IMM, M6x09_GENERAL },
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{ 0x32, 1, "ORA", IND, M6x09_GENERAL },
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{ 0x33, 1, "ORB", IND, M6x09_GENERAL },
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{ 0x34, 1, "CMPA", IMM, M6x09_GENERAL },
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{ 0x35, 1, "CMPB", IMM, M6x09_GENERAL },
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{ 0x36, 1, "CMPA", IND, M6x09_GENERAL },
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{ 0x37, 1, "CMPB", IND, M6x09_GENERAL },
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{ 0x38, 1, "SETLN", IMM, M6x09_GENERAL },
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{ 0x39, 1, "SETLN", IND, M6x09_GENERAL },
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{ 0x3A, 1, "STA", IND, M6x09_GENERAL },
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{ 0x3B, 1, "STB", IND, M6x09_GENERAL },
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{ 0x3C, 1, "ANDCC", IMM, M6x09_GENERAL },
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@ -1266,57 +1266,57 @@ const m6x09_base_disassembler::opcodeinfo konami_disassembler::konami_opcodes[]
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{ 0x9E, 1, "ASL", IND, M6x09_GENERAL },
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{ 0x9F, 0, "RTI", INH, M6x09_GENERAL, STEP_OUT },
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{ 0xA0, 0, "ROLA", INH, M6x09_GENERAL },
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{ 0xA1, 0, "ROLB", INH, M6x09_GENERAL },
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{ 0xA2, 1, "ROL", IND, M6x09_GENERAL },
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{ 0xA3, 1, "LSRW", IND, M6x09_GENERAL },
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{ 0xA4, 1, "RORW", IND, M6x09_GENERAL },
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{ 0xA5, 1, "ASRW", IND, M6x09_GENERAL },
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{ 0xA6, 1, "ASLW", IND, M6x09_GENERAL },
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{ 0xA7, 1, "ROLW", IND, M6x09_GENERAL },
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{ 0xA8, 1, "JMP", IND, M6x09_GENERAL },
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{ 0xA9, 1, "JSR", IND, M6x09_GENERAL, STEP_OVER },
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{ 0xAA, 1, "BSR", REL, M6x09_GENERAL, STEP_OVER },
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{ 0xAB, 2, "LBSR", LREL, M6x09_GENERAL, STEP_OVER },
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{ 0xAC, 1, "DECB,JNZ", REL, M6x09_GENERAL },
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{ 0xAD, 1, "DECX,JNZ", REL, M6x09_GENERAL },
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{ 0xAE, 0, "NOP", INH, M6x09_GENERAL },
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{ 0xA0, 0, "ROLA", INH, M6x09_GENERAL },
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{ 0xA1, 0, "ROLB", INH, M6x09_GENERAL },
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{ 0xA2, 1, "ROL", IND, M6x09_GENERAL },
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{ 0xA3, 1, "LSRW", IND, M6x09_GENERAL },
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{ 0xA4, 1, "RORW", IND, M6x09_GENERAL },
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{ 0xA5, 1, "ASRW", IND, M6x09_GENERAL },
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{ 0xA6, 1, "ASLW", IND, M6x09_GENERAL },
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{ 0xA7, 1, "ROLW", IND, M6x09_GENERAL },
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{ 0xA8, 1, "JMP", IND, M6x09_GENERAL },
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{ 0xA9, 1, "JSR", IND, M6x09_GENERAL, STEP_OVER },
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{ 0xAA, 1, "BSR", REL, M6x09_GENERAL, STEP_OVER },
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{ 0xAB, 2, "LBSR", LREL, M6x09_GENERAL, STEP_OVER },
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{ 0xAC, 1, "DBJNZ", REL, M6x09_GENERAL },
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{ 0xAD, 1, "DXJNZ", REL, M6x09_GENERAL },
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{ 0xAE, 0, "NOP", INH, M6x09_GENERAL },
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{ 0xB0, 0, "ABX", INH, M6x09_GENERAL },
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{ 0xB1, 0, "DAA", INH, M6x09_GENERAL },
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{ 0xB2, 0, "SEX", INH, M6x09_GENERAL },
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{ 0xB3, 0, "MUL", INH, M6x09_GENERAL },
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{ 0xB4, 0, "LMUL", INH, M6x09_GENERAL },
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{ 0xB5, 0, "DIV X,B", INH, M6x09_GENERAL },
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{ 0xB6, 0, "BMOVE Y,X,U", INH, M6x09_GENERAL },
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{ 0xB7, 0, "MOVE Y,X,U", INH, M6x09_GENERAL },
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{ 0xB8, 1, "LSRD", IMM, M6x09_GENERAL },
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{ 0xB9, 1, "LSRD", IND, M6x09_GENERAL },
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{ 0xBA, 1, "RORD", IMM, M6x09_GENERAL },
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{ 0xBB, 1, "RORD", IND, M6x09_GENERAL },
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{ 0xBC, 1, "ASRD", IMM, M6x09_GENERAL },
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{ 0xBD, 1, "ASRD", IND, M6x09_GENERAL },
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{ 0xBE, 1, "ASLD", IMM, M6x09_GENERAL },
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{ 0xBF, 1, "ASLD", IND, M6x09_GENERAL },
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{ 0xB5, 0, "DIV X,B", INH, M6x09_GENERAL },
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{ 0xB6, 0, "BMOVE Y,X,U", INH, M6x09_GENERAL },
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{ 0xB7, 0, "MOVE Y,X,U", INH, M6x09_GENERAL },
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{ 0xB8, 1, "LSRDI", IMM, M6x09_GENERAL },
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{ 0xB9, 1, "LSRWA", IND, M6x09_GENERAL },
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{ 0xBA, 1, "RORDI", IMM, M6x09_GENERAL },
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{ 0xBB, 1, "RORWA", IND, M6x09_GENERAL },
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{ 0xBC, 1, "ASRDI", IMM, M6x09_GENERAL },
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{ 0xBD, 1, "ASRWA", IND, M6x09_GENERAL },
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{ 0xBE, 1, "ASLDI", IMM, M6x09_GENERAL },
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{ 0xBF, 1, "ASLWA", IND, M6x09_GENERAL },
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{ 0xC0, 1, "ROLD", IMM, M6x09_GENERAL },
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{ 0xC1, 1, "ROLD", IND, M6x09_GENERAL },
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{ 0xC2, 0, "CLRD", INH, M6x09_GENERAL },
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{ 0xC3, 1, "CLRW", IND, M6x09_GENERAL },
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{ 0xC4, 0, "NEGD", INH, M6x09_GENERAL },
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{ 0xC5, 1, "NEGW", IND, M6x09_GENERAL },
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{ 0xC6, 0, "INCD", INH, M6x09_GENERAL },
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{ 0xC7, 1, "INCW", IND, M6x09_GENERAL },
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{ 0xC8, 0, "DECD", INH, M6x09_GENERAL },
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{ 0xC9, 1, "DECW", IND, M6x09_GENERAL },
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{ 0xCA, 0, "TSTD", INH, M6x09_GENERAL },
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{ 0xCB, 1, "TSTW", IND, M6x09_GENERAL },
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{ 0xCC, 0, "ABSA", INH, M6x09_GENERAL },
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{ 0xCD, 0, "ABSB", INH, M6x09_GENERAL },
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{ 0xCE, 0, "ABSD", INH, M6x09_GENERAL },
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{ 0xCF, 0, "BSET A,X,U", INH, M6x09_GENERAL },
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{ 0xC0, 1, "ROLDI", IMM, M6x09_GENERAL },
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{ 0xC1, 1, "ROLWA", IND, M6x09_GENERAL },
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{ 0xC2, 0, "CLRD", INH, M6x09_GENERAL },
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{ 0xC3, 1, "CLRW", IND, M6x09_GENERAL },
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{ 0xC4, 0, "NEGD", INH, M6x09_GENERAL },
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{ 0xC5, 1, "NEGW", IND, M6x09_GENERAL },
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{ 0xC6, 0, "INCD", INH, M6x09_GENERAL },
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{ 0xC7, 1, "INCW", IND, M6x09_GENERAL },
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{ 0xC8, 0, "DECD", INH, M6x09_GENERAL },
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{ 0xC9, 1, "DECW", IND, M6x09_GENERAL },
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{ 0xCA, 0, "TSTD", INH, M6x09_GENERAL },
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{ 0xCB, 1, "TSTW", IND, M6x09_GENERAL },
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{ 0xCC, 0, "ABSA", INH, M6x09_GENERAL },
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{ 0xCD, 0, "ABSB", INH, M6x09_GENERAL },
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{ 0xCE, 0, "ABSD", INH, M6x09_GENERAL },
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{ 0xCF, 0, "BSET A,X,U", INH, M6x09_GENERAL },
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{ 0xD0, 0, "BSET D,X,U", INH, M6x09_GENERAL }
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{ 0xD0, 0, "BSETW D,X,U", INH, M6x09_GENERAL }
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};
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@ -1336,12 +1336,12 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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{
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"?", /* 0 - extended mode */
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"?", /* 1 */
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"x", /* 2 */
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"y", /* 3 */
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"X", /* 2 */
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"Y", /* 3 */
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"?", /* 4 - direct page */
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"u", /* 5 */
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"s", /* 6 */
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"pc" /* 7 - pc */
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"U", /* 5 */
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"S", /* 6 */
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"PC" /* 7 - pc */
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};
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int idx = (mode >> 4) & 7;
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@ -1357,19 +1357,19 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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switch (type & 7)
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{
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case 0x00: /* register a */
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util::stream_format(stream, "[a,%s]", index_reg[idx]);
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util::stream_format(stream, "[A,%s]", index_reg[idx]);
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break;
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case 0x01: /* register b */
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util::stream_format(stream, "[b,%s]", index_reg[idx]);
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util::stream_format(stream, "[B,%s]", index_reg[idx]);
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break;
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case 0x04: /* direct - mode */
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util::stream_format(stream, "[$%02x]", params.r8(p++));
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util::stream_format(stream, "[$%02X]", params.r8(p++));
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break;
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case 0x07: /* register d */
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util::stream_format(stream, "[d,%s]", index_reg[idx]);
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util::stream_format(stream, "[D,%s]", index_reg[idx]);
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break;
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default:
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@ -1382,23 +1382,23 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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switch (type & 7)
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{
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case 0x00: /* register a */
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util::stream_format(stream, "a,%s", index_reg[idx]);
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util::stream_format(stream, "A,%s", index_reg[idx]);
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break;
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case 0x01: /* register b */
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util::stream_format(stream, "b,%s", index_reg[idx]);
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util::stream_format(stream, "B,%s", index_reg[idx]);
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break;
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case 0x04: /* direct - mode */
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util::stream_format(stream, "$%02x", params.r8(p++));
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util::stream_format(stream, "$%02X", params.r8(p++));
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break;
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case 0x07: /* register d */
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util::stream_format(stream, "d,%s", index_reg[idx]);
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util::stream_format(stream, "D,%s", index_reg[idx]);
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break;
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default:
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util::stream_format(stream, "????,%s", index_reg[idx]);
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util::stream_format(stream, "?,%s", index_reg[idx]);
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break;
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}
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}
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@ -1430,9 +1430,9 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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val = params.r8(p++);
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if (val & 0x80)
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util::stream_format(stream, "[#$-%02x,%s]", 0x100 - val, index_reg[idx]);
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util::stream_format(stream, "[#$-%02X,%s]", 0x100 - val, index_reg[idx]);
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else
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util::stream_format(stream, "[#$%02x,%s]", val, index_reg[idx]);
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util::stream_format(stream, "[#$%02X,%s]", val, index_reg[idx]);
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break;
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case 5: // post word offset
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@ -1440,9 +1440,9 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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p += 2;
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if (val & 0x8000)
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util::stream_format(stream, "[#$-%04x,%s]", 0x10000 - val, index_reg[idx]);
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util::stream_format(stream, "[#$-%04X,%s]", 0x10000 - val, index_reg[idx]);
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else
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util::stream_format(stream, "[#$%04x,%s]", val, index_reg[idx]);
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util::stream_format(stream, "[#$%04X,%s]", val, index_reg[idx]);
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break;
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case 6: // simple
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@ -1453,7 +1453,7 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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val = params.r16(p);
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p += 2;
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util::stream_format(stream, "[$%04x]", val);
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util::stream_format(stream, "[$%04X]", val);
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break;
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}
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}
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@ -1481,9 +1481,9 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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val = params.r8(p++);
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if (val & 0x80)
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util::stream_format(stream, "#$-%02x,%s", 0x100 - val, index_reg[idx]);
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util::stream_format(stream, "#$-%02X,%s", 0x100 - val, index_reg[idx]);
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else
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util::stream_format(stream, "#$%02x,%s", val, index_reg[idx]);
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util::stream_format(stream, "#$%02X,%s", val, index_reg[idx]);
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break;
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case 5: // post word offset
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@ -1491,9 +1491,9 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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p += 2;
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if (val & 0x8000)
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util::stream_format(stream, "#$-%04x,%s", 0x10000 - val, index_reg[idx]);
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util::stream_format(stream, "#$-%04X,%s", 0x10000 - val, index_reg[idx]);
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else
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util::stream_format(stream, "#$%04x,%s", val, index_reg[idx]);
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util::stream_format(stream, "#$%04X,%s", val, index_reg[idx]);
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break;
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case 6: // simple
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@ -1504,7 +1504,7 @@ void konami_disassembler::indexed(std::ostream &stream, uint8_t mode, const data
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val = params.r16(p);
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p += 2;
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util::stream_format(stream, "$%04x", val);
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util::stream_format(stream, "$%04X", val);
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break;
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}
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}
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@ -70,8 +70,8 @@ MAIN:
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case 0x35: set_regop8(m_q.r.b); set_imm(); %CMP8; return;
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case 0x36: set_regop8(m_q.r.a); %INDEXED; %CMP8; return;
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case 0x37: set_regop8(m_q.r.b); %INDEXED; %CMP8; return;
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case 0x38: set_imm(); %SETLINE; return;
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case 0x39: %INDEXED; %SETLINE; return;
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case 0x38: set_imm(); %SETLN; return;
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case 0x39: %INDEXED; %SETLN; return;
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case 0x3A: set_regop8(m_q.r.a); %INDEXED; %ST8; return;
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case 0x3B: set_regop8(m_q.r.b); %INDEXED; %ST8; return;
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case 0x3C: set_imm(); %ANDCC; return;
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@ -189,8 +189,8 @@ MAIN:
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case 0xA9: %INDEXED; %JSR; return;
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case 0xAA: %BSR; return;
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case 0xAB: %LBSR; return;
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case 0xAC: %DECBJNZ; return;
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case 0xAD: %DECXJNZ; return;
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case 0xAC: %DBJNZ; return;
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case 0xAD: %DXJNZ; return;
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case 0xAE: %NOP; return;
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case 0xB0: %ABX; return;
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@ -201,17 +201,17 @@ MAIN:
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case 0xB5: %DIVX; return;
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case 0xB6: %BMOVE; return;
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case 0xB7: %MOVE; return;
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case 0xB8: %IMM_IM; set_d(); %LSRD; return;
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case 0xB9: %INDEXED; %LSRD; return;
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case 0xBA: %IMM_IM; set_d(); %RORD; return;
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case 0xBB: %INDEXED; %RORD; return;
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case 0xBC: %IMM_IM; set_d(); %ASRD; return;
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case 0xBD: %INDEXED; %ASRD; return;
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case 0xBE: %IMM_IM; set_d(); %ASLD; return;
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case 0xBF: %INDEXED; %ASLD; return;
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case 0xB8: %IMM_IM; set_d(); %LSRDI; return;
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case 0xB9: %INDEXED; %LSRDI; return;
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case 0xBA: %IMM_IM; set_d(); %RORDI; return;
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case 0xBB: %INDEXED; %RORDI; return;
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case 0xBC: %IMM_IM; set_d(); %ASRDI; return;
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case 0xBD: %INDEXED; %ASRDI; return;
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case 0xBE: %IMM_IM; set_d(); %ASLDI; return;
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case 0xBF: %INDEXED; %ASLDI; return;
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case 0xC0: %IMM_IM; set_d(); %ROLD; return;
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case 0xC1: %INDEXED; %ROLD; return;
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case 0xC0: %IMM_IM; set_d(); %ROLDI; return;
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case 0xC1: %INDEXED; %ROLDI; return;
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case 0xC2: set_d(); %CLR16; return;
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case 0xC3: %INDEXED; %CLR16; return;
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case 0xC4: set_d(); %NEG16; return;
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@ -227,7 +227,7 @@ MAIN:
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case 0xCE: set_d(); %ABS16; return;
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case 0xCF: %BSET; return;
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case 0xD0: %BSET2; return;
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case 0xD0: %BSETW; return;
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default: %ILLEGAL; return;
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}
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return;
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@ -455,7 +455,7 @@ EXGTFR:
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eat(2);
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return;
|
||||
|
||||
SETLINE:
|
||||
SETLN:
|
||||
@set_lines(read_operand());
|
||||
return;
|
||||
|
||||
@ -489,8 +489,8 @@ BSET:
|
||||
}
|
||||
return;
|
||||
|
||||
BSET2:
|
||||
// BSET2 does not appear to be interruptable, at least judging from the old implementation
|
||||
BSETW:
|
||||
// BSETW does not appear to be interruptable, at least judging from the old implementation
|
||||
while(m_u.w != 0)
|
||||
{
|
||||
@eat(1);
|
||||
@ -500,21 +500,21 @@ BSET2:
|
||||
}
|
||||
return;
|
||||
|
||||
DECXJNZ:
|
||||
// not sure if this affects V?
|
||||
m_x.w = set_flags<uint16_t>(CC_NZV, m_x.w, 1, m_x.w - 1);
|
||||
@eat(1);
|
||||
set_cond(cond_ne());
|
||||
goto BRANCH;
|
||||
|
||||
DECBJNZ:
|
||||
DBJNZ:
|
||||
// not sure if this affects V?
|
||||
m_q.r.b = set_flags<uint8_t>(CC_NZV, m_q.r.b, 1, m_q.r.b - 1);
|
||||
@eat(1);
|
||||
set_cond(cond_ne());
|
||||
goto BRANCH;
|
||||
|
||||
LSRD:
|
||||
DXJNZ:
|
||||
// not sure if this affects V?
|
||||
m_x.w = set_flags<uint16_t>(CC_NZV, m_x.w, 1, m_x.w - 1);
|
||||
@eat(1);
|
||||
set_cond(cond_ne());
|
||||
goto BRANCH;
|
||||
|
||||
LSRDI:
|
||||
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
|
||||
m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a;
|
||||
|
||||
@ -533,7 +533,7 @@ LSRD:
|
||||
write_operand(1, m_temp.b.l);
|
||||
return;
|
||||
|
||||
ASLD:
|
||||
ASLDI:
|
||||
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
|
||||
m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a;
|
||||
|
||||
@ -550,7 +550,7 @@ ASLD:
|
||||
write_operand(1, m_temp.b.l);
|
||||
return;
|
||||
|
||||
ASRD:
|
||||
ASRDI:
|
||||
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
|
||||
m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a;
|
||||
|
||||
@ -569,7 +569,7 @@ ASRD:
|
||||
write_operand(1, m_temp.b.l);
|
||||
return;
|
||||
|
||||
ROLD:
|
||||
ROLDI:
|
||||
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
|
||||
m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a;
|
||||
|
||||
@ -586,7 +586,7 @@ ROLD:
|
||||
write_operand(1, m_temp.b.l);
|
||||
return;
|
||||
|
||||
RORD:
|
||||
RORDI:
|
||||
// register addr.mode takes shift count from opcode operand, indexed addr.mode takes it from A
|
||||
m_bcount = is_register_addressing_mode() ? m_temp_im : m_q.r.a;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user