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Implemented I2C accesses to the Acorn Archimedes / Aristocrat MK-5 HW, fixing SRAM check [Angelo Salese]

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Added clock read-back register to the I2C device [Angelo Salese]
This commit is contained in:
Angelo Salese 2010-08-16 20:49:00 +00:00
parent 155802611f
commit ea32352618
4 changed files with 53 additions and 3 deletions
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16
src/emu/machine/i2cmem.c
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@ -384,7 +384,6 @@ void i2cmem_device::set_sda_line( int state )
}
}
WRITE_LINE_DEVICE_HANDLER( i2cmem_scl_write )
{
downcast<i2cmem_device *>( device )->set_scl_line( state );
@ -581,6 +580,21 @@ int i2cmem_device::read_sda_line()
return res;
}
READ_LINE_DEVICE_HANDLER( i2cmem_scl_read )
{
return downcast<i2cmem_device *>( device )->read_scl_line();
}
int i2cmem_device::read_scl_line()
{
int res = m_scl & 1;
verboselog( this, 2, "read scl %d\n", res );
return res;
}
//**************************************************************************
// INTERNAL HELPERS

2
src/emu/machine/i2cmem.h
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@ -102,6 +102,7 @@ public:
void set_scl_line( int state );
void set_wc_line( int state );
int read_sda_line();
int read_scl_line();
protected:
// device-level overrides
@ -154,5 +155,6 @@ WRITE_LINE_DEVICE_HANDLER( i2cmem_sda_write );
WRITE_LINE_DEVICE_HANDLER( i2cmem_scl_write );
WRITE_LINE_DEVICE_HANDLER( i2cmem_wc_write );
READ_LINE_DEVICE_HANDLER( i2cmem_sda_read );
READ_LINE_DEVICE_HANDLER( i2cmem_scl_read );
#endif /* __I2CMEM_H__ */

24
src/mame/drivers/aristmk5.c
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@ -16,7 +16,8 @@
- R0 == 1: IRQ status A force IRQ flag check failed
- R0 == 2: FIQ status force IRQ flag check failed
- R0 == 3: Timer 1 latch low val == 0xf5
- bp 0x34002a8: SRAM Check branch test
- bp 0x34002a8: SRAM Check branch test (I2C)
bp 0x34002a4:
- bp 0x34002d0: 2KHz Timer branch test
- bp 0x34002f8: DRAM emulator branch tests
- R0 == 0 "DRAM emulator found"
@ -32,6 +33,7 @@
#include "cpu/arm/arm.h"
#include "sound/dac.h"
#include "includes/archimds.h"
#include "machine/i2cmem.h"
extern UINT8 ioc_regs[0x80/4];
extern INT16 memc_pages[(32*1024*1024)/(4096)]; // the logical RAM area is 32 megs, and the smallest page size is 4k
@ -69,9 +71,16 @@ static VIDEO_UPDATE(aristmk5)
return 0;
}
static WRITE32_HANDLER( mk5_i2c_w )
{
i2cmem_sda_write(space->machine->device("i2cmem"), (data & 0x40) >> 6);
i2cmem_scl_write(space->machine->device("i2cmem"), (data & 0x80) >> 7);
}
static ADDRESS_MAP_START( aristmk5_map, ADDRESS_SPACE_PROGRAM, 32 )
AM_RANGE(0x00000000, 0x01ffffff) AM_READWRITE(archimedes_memc_logical_r, archimedes_memc_logical_w)
AM_RANGE(0x02000000, 0x02ffffff) AM_RAM AM_BASE(&archimedes_memc_physmem) /* physical RAM - 16 MB for now, should be 512k for the A310 */
AM_RANGE(0x03010420, 0x03010423) AM_WRITE(mk5_i2c_w)
AM_RANGE(0x03010810, 0x03010813) AM_READNOP //MK-5 specific, watchdog
AM_RANGE(0x03000000, 0x033fffff) AM_READWRITE(archimedes_ioc_r, archimedes_ioc_w)
AM_RANGE(0x03400000, 0x035fffff) AM_ROM AM_REGION("maincpu", 0) AM_WRITE(archimedes_memc_page_w)
@ -111,12 +120,23 @@ static MACHINE_RESET( aristmk5 )
}
}
#define NVRAM_SIZE 1024
#define NVRAM_PAGE_SIZE 16 /* max size of one write request */
static const i2cmem_interface i2cmem_interface =
{
I2CMEM_SLAVE_ADDRESS, NVRAM_PAGE_SIZE, NVRAM_SIZE
};
static MACHINE_DRIVER_START( aristmk5 )
MDRV_CPU_ADD("maincpu", ARM, 10000000) // ?
MDRV_CPU_PROGRAM_MAP(aristmk5_map)
MDRV_MACHINE_RESET( aristmk5 )
MDRV_MACHINE_START( aristmk5 )
MDRV_MACHINE_RESET( aristmk5 )
MDRV_I2CMEM_ADD("i2cmem",i2cmem_interface)
MDRV_SCREEN_ADD("screen", RASTER)
MDRV_SCREEN_REFRESH_RATE(60)

14
src/mame/machine/archimds.c
View File

@ -30,6 +30,7 @@
#include "cpu/arm/arm.h"
#include "sound/dac.h"
#include "includes/archimds.h"
#include "machine/i2cmem.h"
#ifdef MESS
#include "machine/wd17xx.h"
@ -49,6 +50,7 @@ static UINT32 vidc_sndstart, vidc_sndend, vidc_sndcur;
static emu_timer *timer[4], *snd_timer;
emu_timer *vbl_timer;
#define CONTROL 0
#define IRQ_STATUS_A 4
#define IRQ_MASK_A 6
#define IRQ_STATUS_B 8
@ -342,6 +344,16 @@ READ32_HANDLER(archimedes_ioc_r)
switch (offset & 0x1f)
{
case CONTROL:
{
UINT8 i2c_clk,i2c_data;
i2c_clk = ((i2cmem_scl_read(space->machine->device("i2cmem")) & 1) << 1);
i2c_data = (i2cmem_sda_read(space->machine->device("i2cmem")) & 1);
return (ioc_regs[CONTROL] & 0xfc) | i2c_clk | i2c_data;
}
case 1: // keyboard read
archimedes_request_irq_b(space->machine, ARCHIMEDES_IRQB_KBD_XMIT_EMPTY);
break;
@ -402,6 +414,8 @@ WRITE32_HANDLER(archimedes_ioc_w)
{
case 0: // I2C bus control
//logerror("IOC I2C: CLK %d DAT %d\n", (data>>1)&1, data&1);
i2cmem_sda_write(space->machine->device("i2cmem"), data & 0x01);
i2cmem_scl_write(space->machine->device("i2cmem"), (data & 0x02) >> 1);
break;
case IRQ_MASK_A: